Cascode circuit and cascode transistor

Abstract

The embodiment of the application relates to a common-source common-gate circuit and a common-source common-gate transistor, the circuit comprising: a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate, a Kelvin source substrate, and a drain pin, a source pin, a gate pin and a Kelvin source pin; the drain of the JFET chip is welded on the drain substrate; the MOSFET chip is stacked on the JFET chip, and the drain of the MOSFET chip is welded on the source pad of the JFET chip; the source of the MOSFET chip is connected with the source substrate through a first metal lead; the gate of the JFET chip is connected with the source of the MOSFET chip through a second metal lead, and the gate of the JFET chip is connected with the Kelvin source substrate through a third metal lead; and the gate of the MOSFET chip is connected with the gate substrate through a fourth metal lead. The embodiment of the application can reduce the power loop loop area, reduce the parasitic inductance, suppress the switch oscillation, reduce the electromagnetic interference, and directly connect the Kelvin source pin with the JFET gate, thereby solving the JFET gate potential control problem.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a common-source cascode circuit and a common-source cascode transistor. Background Technology

[0002] A common source-common gate (CSG) transistor, also known as a cascode, is based on the principle of connecting two transistors (such as a JFET (Field Effect Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor)) in a common source-common gate manner to improve device performance, including voltage withstand capability and switching speed.

[0003] In this setup, the source of the JFET is connected to the drain of the MOSFET (common source), and the gate of the JFET is connected to the source of the MOSFET (common gate). Essentially, the JFET and MOSFET are connected in series. The JFET is responsible for "handling high voltage," while the MOSFET is responsible for "low-loss conduction." Together, they achieve the effect of "high voltage + low loss."

[0004] Current Cascode transistors typically use a parallel mounting configuration, where JFETs and MOSFETs are mounted side-by-side on the substrate. This parallel mounting configuration requires long leads to connect the various nodes of the chip, resulting in higher parasitic inductance. Furthermore, the gate of the JFET is not directly connected to the Kelvin source pin, causing a gate potential delay problem. Summary of the Invention

[0005] In view of this, in order to solve some or all of the above-mentioned technical problems, embodiments of this application provide a common-source cascode circuit and a common-source cascode transistor.

[0006] In a first aspect, embodiments of this application provide a common source cascode circuit, the circuit including: a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate and a Kelvin source substrate, as well as drain pins, source pins, gate pins and Kelvin source pins; The drain substrate, source substrate, gate substrate and Kelvin source substrate are isolated from each other. The drain substrate is connected to the drain pin, the source substrate is connected to the source pin, the gate substrate is connected to the gate pin, and the Kelvin source substrate is connected to the Kelvin source pin. The drain of the JFET chip is soldered onto the drain substrate; The MOSFET chips are stacked on top of the JFET chips, and the drain of the MOSFET chips is soldered to the source pad of the JFET chips. The source of the MOSFET chip is connected to the source substrate via a first metal lead; The gate of the JFET chip is connected to the source of the MOSFET chip via a second metal lead, and the gate of the JFET chip is connected to the Kelvin source substrate via a third metal lead. The gate of the MOSFET chip is connected to the gate substrate via a fourth metal lead.

[0007] In one possible implementation, the area of ​​the drain substrate is larger than the areas of the source substrate, the gate substrate, and the Kelvin source substrate.

[0008] In one possible implementation, the drain substrate is made of a direct copper-clad ceramic substrate, and the drain of the JFET chip is soldered to the copper-clad surface of the drain substrate.

[0009] In one possible implementation, the drain of the JFET chip is soldered to the copper-clad surface via silver sintering.

[0010] In one possible implementation, the diameter of the first metal lead is larger than the diameters of the second, third, and fourth metal leads.

[0011] In one possible implementation, the number of first metal leads is at least two.

[0012] In one possible implementation, the number of second metal leads is one, and the number of third metal leads is one.

[0013] In one possible implementation, the JFET chip is made of silicon carbide, and the MOSFET is made of silicon.

[0014] Secondly, embodiments of this application provide a common-source common-gate transistor, which includes a molding compound and the aforementioned common-source common-gate circuit. The common-source common-gate circuit includes a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate, and a Kelvin source substrate, which are located inside the molding compound, while the drain pin, source pin, gate pin, and Kelvin source pin are located outside the molding compound.

[0015] In one possible implementation, the drain substrate, source substrate, gate substrate, and Kelvin source substrate are all direct copper-clad ceramic substrates. The direct copper-clad ceramic substrate includes a first copper-clad surface, a ceramic layer, and a second copper-clad surface. The first copper-clad surface and the ceramic layer are located inside the cascode transistor, and the second copper-clad surface is located on the outer surface of the cascode transistor. The drain of the JFET chip is soldered to the first copper-clad surface of the drain substrate, the drain pin is connected to the first copper-clad surface of the drain substrate, the source pin is connected to the first copper-clad surface of the source substrate, the gate pin is connected to the first copper-clad surface of the gate substrate, and the Kelvin source pin is connected to the first copper-clad surface of the Kelvin source substrate.

[0016] The cascode circuit and cascode transistor provided in this application embodiment have the drain of a JFET chip soldered onto a drain substrate, and MOSFET chips stacked on top of the JFET chip. The drain of the MOSFET chip is soldered onto the source pad of the JFET chip. The source of the MOSFET chip is connected to the source substrate via a first metal lead, the gate of the JFET chip is connected to the source of the MOSFET chip via a second metal lead, the gate of the JFET chip is connected to the Kelvin source substrate via a third metal lead, and the gate of the MOSFET chip is connected to the gate substrate via a fourth metal lead. This application embodiment realizes the construction of a cascode circuit using a stacked structure. The drain of the JFET is mounted on the substrate, and the substrate and drain pin are directly soldered without the need for leads. Furthermore, the direct stacking and soldering of the source of the JFET and the drain of the MOSFET reduces the number of leads, thereby reducing the power loop area, reducing parasitic inductance, suppressing switching oscillations, and reducing electromagnetic interference. Additionally, the Kelvin source pin is directly connected to the gate of the JFET, solving the JFET gate potential control problem and preventing the JFET source voltage from overshooting and breaking down the MOSFET when it is turned off. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0020] Figure 1 This is a schematic diagram of the common source cascode circuit provided in an embodiment of this application; Figure 2 A schematic diagram of a common-source cascode circuit provided in an embodiment of this application; Figure 3 A schematic diagram of another common-source cascode circuit provided in the embodiments of this application; Figure 4 A schematic diagram of a common-source cascode transistor provided in an embodiment of this application; Figure 5 This is a schematic diagram of the back side of a common-source, common-gate transistor provided in an embodiment of this application.

[0021] Figure label: 100 - Common source / common gate circuit; 101 - JFET chip; 102 - MOSFET chip; 103 - Drain substrate; 104 - Source substrate; 105 - Gate substrate; 106 - Kelvin source substrate; 107 - Drain pin; 108 - Source pin; 109 - Gate pin; 110 - Kelvin source pin; 111 - First metal lead; 112 - Second metal lead; 113 - Third metal lead; 114 - Fourth metal lead; 400 - Common source / common gate transistor; 401 - Molding package; 402 - Second copper cladding. Detailed Implementation

[0022] Various exemplary embodiments of this application will now be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this application.

[0023] Those skilled in the art will understand that the terms "first" and "second" in the embodiments of this application are only used to distinguish different steps, devices or modules, and do not represent any specific technical meaning, nor do they indicate the logical order between them.

[0024] It should also be understood that in this embodiment, "multiple" can refer to two or more, and "at least one" can refer to one, two or more.

[0025] It should also be understood that any component, data or structure mentioned in the embodiments of this application can generally be understood as one or more unless explicitly defined or given contrary guidance in the context.

[0026] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this application generally indicates that the preceding and following related objects have an "or" relationship.

[0027] It should also be understood that the description of the various embodiments in this application emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0028] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit the scope of this application and its application or use.

[0029] Techniques, circuits, and devices known to a person skilled in the art may not be discussed in detail, but where appropriate, such techniques, circuits, and devices should be considered part of the specification.

[0030] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0031] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. To facilitate understanding of the embodiments of this application, the application will be described in detail below with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0032] Figure 1 This is a schematic diagram of a common source and common gate circuit 100 provided in an embodiment of this application. The circuit 100 specifically includes: a JFET chip 101, a MOSFET chip 102, a drain substrate 103, a source substrate 104, a gate substrate 105 and a Kelvin source substrate 106, as well as a drain pin 107, a source pin 108, a gate pin 109 and a Kelvin source pin 110.

[0033] The drain substrate 103, source substrate 104, gate substrate 105 and Kelvin source substrate 106 are isolated from each other, that is, each substrate is kept insulated from the others.

[0034] Drain substrate 103 is connected to drain pin 107, source substrate 104 is connected to source pin 108, gate substrate 105 is connected to gate pin 109, and Kelvin source substrate 106 is connected to Kelvin source pin 110.

[0035] like Figure 1 As shown, each of the above substrates can be directly soldered to its corresponding pin.

[0036] like Figure 2As shown, it illustrates the schematic of a common-source cascode circuit, where D_J is the drain of JFET chip 101, corresponding to... Figure 1 The drain pin 107 is used; G_M is the gate pin of MOSFET chip 102, corresponding to... Figure 1 In the context of MOSFET chip 102, the gate pin 109 is used; S_M is the source pin of MOSFET chip 102, corresponding to... Figure 1 The source pin is 108; KS is the Kelvin source, corresponding to... Figure 1 Kelvin source pin 110 in the middle.

[0037] In this embodiment, the D pin (Drain) is the power current output terminal, used to carry the main current, and forms a power loop with the S pin.

[0038] The G pin (Gate) is the control signal input terminal, connected to an external drive circuit, and controlled by the gate-source voltage V. GS Controls on / off states.

[0039] The S pin (Source) is the power current input terminal, used to carry the main current. It forms a power loop with the D pin and shares the source function with the KS pin, but it is not used to drive the reference. It is the main path of the power loop.

[0040] The KS pin (Kelvin Source) serves as the reference ground for the drive circuit. It is used only as a voltage reference point for the drive signal and does not carry the main power current. It is used to eliminate source parasitic inductance, ensure accurate gate drive voltage, improve switching speed, and reduce switching losses.

[0041] In this embodiment, the drain of the JFET chip 101 (i.e. Figure 2 The D_J shown is soldered onto the drain substrate 103. Figure 1 The side of the JFET chip 101 that contacts the drain substrate 103 is the drain of the JFET chip 101.

[0042] MOSFET chips 102 are stacked on top of JFET chips 101, and the drain D_M of MOSFET chips 102 is soldered to the source pad of JFET chips 101. Figure 1 As shown, the upper surface of the JFET chip 101 is the source (S_J), and the side of the MOSFET chip 102 that contacts the upper surface of the JFET chip 101 is the drain (D_M). The two are soldered together to form a structure as shown in the diagram. Figure 2 The connection relationships are shown.

[0043] like Figure 3As shown, a three-dimensional schematic diagram of a common-source, common-gate circuit is presented. The source S_M of the MOSFET chip 102 is connected to the source substrate 104 through the first metal lead 111, thereby connecting the source of the MOSFET chip 102 to the source pin 108.

[0044] The gate G_J of JFET chip 101 is connected to the source S_M of MOSFET chip 102 via a second metal lead 112, and the gate G_J of JFET chip 101 is connected to Kelvin source substrate 106 via a third metal lead 113, thereby connecting G_J, S_M and KS pins. This connection method integrates the critical path of the drive circuit (from S_M to G_J) within the package, shortening the signal transmission path and reducing inductance.

[0045] The gate G_M of the MOSFET chip 102 is connected to the gate substrate 105 through the fourth metal lead 114, thereby connecting the gate of the MOSFET chip 102 to the gate pin 109.

[0046] The number, length, and diameter of the aforementioned leads can be set according to actual needs.

[0047] The common-source, common-gate circuit provided in this application embodiment involves soldering the drain of the JFET chip 101 onto the drain substrate 103, stacking the MOSFET chip 102 on the JFET chip 101, with the drain of the MOSFET chip 102 soldered onto the source pad of the JFET chip 101. The source of the MOSFET chip 102 is connected to the source substrate 104 via a first metal lead 111, the gate of the JFET chip 101 is connected to the source of the MOSFET chip 102 via a second metal lead 112, the gate of the JFET chip 101 is connected to the Kelvin source substrate 106 via a third metal lead 113, and the gate of the MOSFET chip 102 is connected to the gate substrate 105 via a fourth metal lead 114. This application embodiment implements a common-source, common-gate circuit constructed using a stacked structure. The drain of the JFET is mounted on the substrate, and the substrate is directly soldered to the drain pin 107 without the need for leads. Furthermore, the source of the JFET and the drain of the MOSFET are directly stacked and soldered, reducing the number of leads. This reduces the power loop area, lowers parasitic inductance, suppresses switching oscillations, and reduces electromagnetic interference. In addition, the Kelvin source pin 110 is directly connected to the JFET gate, solving the JFET gate potential control problem and preventing the JFET source voltage from overshooting and breaking down the MOSFET when it is turned off.

[0048] In some optional implementations of this embodiment, such as Figure 1 As shown, the area of ​​the drain substrate 103 is larger than the areas of the source substrate 104, the gate substrate 105, and the Kelvin source substrate 106.

[0049] refer to Figure 2 The circuit schematic shown shows that, since the drain of the JFET carries the main current, setting the area of ​​the drain substrate 103 to the maximum can improve the overall heat dissipation performance of the circuit.

[0050] In some optional implementations of this embodiment, the material of the drain substrate 103 is a direct bond ceramic substrate (DBC), and the drain of the JFET chip 101 is soldered to the copper-clad surface of the drain substrate 103.

[0051] The aforementioned DBC substrate typically includes a copper-clad layer and a ceramic layer. In this embodiment, the drain of the JFET chip 101 is soldered onto the copper-clad layer, and the ceramic layer is used for insulation from the outside. Therefore, during installation, there is no need to place an insulating pad on the outer surface of this circuit, and it can directly contact the heat sink, greatly simplifying the installation steps, significantly reducing the system thermal resistance, and improving heat dissipation efficiency.

[0052] Optional, Figure 1 The source substrate 104, gate substrate 105 and Kelvin source substrate 106 shown above can all use DBC substrates to solder each pin to the copper-clad surface, thereby achieving overall circuit insulation from the outside world and improving heat dissipation efficiency.

[0053] In some optional implementations of this embodiment, the drain of the JFET chip 101 is soldered to the copper-clad surface by silver sintering.

[0054] Silver sintering soldering offers higher thermal conductivity and lower thermal resistance compared to traditional solders (the thermal resistance of the silver sintering layer is approximately 0.16 mm²K / W, while that of traditional solder is >1.06 mm²K / W). This improves thermal conductivity and enables ultra-high reliability heat dissipation paths while achieving ultra-low inductance power circuits.

[0055] In some optional implementations of this embodiment, the diameter of the first metal lead 111 is greater than the diameter of the second metal lead 112, the third metal lead 113 and the fourth metal lead 114.

[0056] Since the first metal lead 111 is connected to the source S_M of the MOSFET chip 102, and the source of the MOSFET chip 102 needs to carry the main current, using a thicker metal lead (e.g., 12mil) is beneficial to conduct the heat of the source of the MOSFET chip 102 to the source pin 108 through the lead. Combined with the vertical heat dissipation of the drain substrate 103, the heat dissipation efficiency is further improved, and the thermal coupling problem between the stacked JFET chip 101 and the MOSFET chip 102 is solved.

[0057] In some optional implementations of this embodiment, the number of first metal leads 111 is at least two.

[0058] The number of the first metal lead 111 can be set according to actual needs. For example... Figure 1 As shown, the first metal lead 111 consists of two 12mil aluminum wires.

[0059] In this embodiment, by setting the number of first metal leads 111 to at least two, the heat from the source of the MOSFET chip 102 can be conducted to the source pin 108 more efficiently, and the resistance between the source of the MOSFET chip 102 and the source pin 108 can be reduced, thereby improving the current withstand performance of the leads.

[0060] In some optional implementations of this embodiment, the number of second metal leads 112 is one, and the number of third metal leads 113 is one.

[0061] Since the second metal lead 112 and the third metal lead 113 transmit drive signals and carry relatively small currents, they can be set to a finer wire diameter (e.g., 5 mil) and a smaller number. They can be connected in a single-wire three-node configuration (including three nodes: S_M, G_J, and KS) to reduce the inductance generated by the leads and further suppress noise interference.

[0062] In some alternative implementations of this embodiment, the JFET chip 101 is made of silicon carbide (SiC) material, and the MOSFET is made of silicon (Si) material.

[0063] SiC JFETs are normally-on devices. Their core characteristic is that the channel is always on when there is no gate voltage. The drive circuit requires negative voltage to turn off and positive voltage to turn on. The structural design is complex and there are reliability risks (such as false turn-on due to loss of negative voltage). In addition, the gate is very sensitive to electrostatic discharge and overvoltage.

[0064] This embodiment utilizes a Si MOSFET to drive a SiC JFET. By simply driving a low-voltage Si MOSFET, the normally open SiC JFET becomes normally off. Furthermore, the drive circuit is compatible with conventional Si MOSFETs or IGBTs, thereby simplifying application circuit design and improving system reliability.

[0065] Pure Si MOSFETs exhibit a sharp increase in on-resistance under high voltage (>600V), resulting in high conduction losses. Pure SiC MOSFETs offer excellent performance but are expensive and have stringent gate drive requirements (needing negative voltage turn-off or special gate resistor design).

[0066] This embodiment combines the low on-resistance (high-voltage advantage) of SiC JFETs with the easy-to-drive and fast-switching characteristics (no tailing) of Si MOSFETs. This structure enables the overall switching speed of the circuit to approach that of SiC MOSFETs, significantly reducing switching losses, making it particularly suitable for high-frequency applications and improving system efficiency.

[0067] Figure 4 A common-source cascode transistor 400 provided in this application embodiment, such as Figure 4 As shown, the common-source cascode transistor 400 includes: a molding compound 401 and a common-source cascode circuit 100 as described in any of the above embodiments.

[0068] The common source common gate circuit includes a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate, and a Kelvin source substrate, all of which are located inside the plastic package, while the drain pin, source pin, gate pin, and Kelvin source pin are located outside the plastic package.

[0069] The common-source cascode transistor provided in this application embodiment can reduce the power loop area, reduce parasitic inductance, suppress switching oscillation, and reduce electromagnetic interference by applying the above-mentioned common-source cascode circuit. Furthermore, the Kelvin source pin is directly connected to the JFET gate, which solves the problem of JFET gate potential control and avoids the JFET source voltage overshoot and breakdown of the MOSFET when the MOSFET is turned off.

[0070] In some optional implementations of this embodiment, the drain substrate, source substrate, gate substrate, and Kelvin source substrate are all direct copper-clad ceramic substrates.

[0071] The direct copper-clad ceramic substrate includes a first copper-clad surface, a ceramic layer, and a second copper-clad surface. The first copper-clad surface and the ceramic layer are located inside the cascode transistor, and the second copper-clad surface is located on the outer surface of the cascode transistor.

[0072] The drain of the JFET chip is soldered to the first copper-clad surface of the drain substrate, the drain pin is connected to the first copper-clad surface of the drain substrate, the source pin is connected to the first copper-clad surface of the source substrate, the gate pin is connected to the first copper-clad surface of the gate substrate, and the Kelvin source pin is connected to the first copper-clad surface of the Kelvin source substrate.

[0073] The first copper-clad surface (e.g., 0.3mm thick) serves as the main current path for the internal circuitry. The drain pin is directly connected to the first copper-clad surface of the drain substrate, and then directly connected to the drain of the JFET via the first copper-clad surface. Heat on the first copper-clad surface can be conducted through an insulating ceramic layer (e.g., 0.38mm thick) to the external heat sink via a second copper-clad layer. The aforementioned ceramic layer can be made of Al2O3 ceramic, with a thermal conductivity ≥25W / mK and a breakdown field strength ≥15kV / mm. Its thermal conductivity and insulation properties can meet the requirements of various scenarios.

[0074] like Figure 5 As shown, this is a schematic diagram of the back side of the cascode transistor provided in this embodiment. 402 in the diagram represents the second copper-clad surface of each substrate. The second copper-clad surface can directly contact the heat sink, conducting heat from inside the transistor to the heat sink.

[0075] In this embodiment, by using a DBC substrate as the base for welding the drain of the JFET, the insulation of the ceramic layer can completely insulate the internal circuit from the outside world. The second copper layer on the outside of the transistor can be directly connected to the heat sink without the need for an additional insulating pad, thereby greatly improving the heat dissipation efficiency of the transistor.

[0076] The manufacturing process of the cascode transistor provided in this application embodiment can be as follows: First, the drain D_J of the JFET is soldered onto the DBC substrate using silver sintering. Then, the drain D_M of the MOSFET is soldered onto the source S_J pad of the JFET using vacuum reflow soldering. Next, the soldered chip and frame surfaces are cleaned using plasma gas cleaning. Then, the drive circuit is bonded using metal wire bonding, specifically S_M+G_J is bonded to the KS pin, and G_M is bonded to the G pin. Next, the power circuit is bonded using metal wire bonding, specifically S_M is bonded to the S pin. Finally, the transistor is packaged using a molding compound.

[0077] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different circuits to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0078] The steps of the circuits or algorithms described in connection with the embodiments disclosed herein can be implemented in hardware, in a software module executed by a processor, or in a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0079] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also mean including the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0080] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A common-source cascode circuit, characterized in that, The circuit includes: a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate and a Kelvin source substrate, as well as drain pins, source pins, gate pins and Kelvin source pins; The drain substrate, source substrate, gate substrate, and Kelvin source substrate are isolated from each other. The drain substrate is connected to the drain pin, the source substrate is connected to the source pin, the gate substrate is connected to the gate pin, and the Kelvin source substrate is connected to the Kelvin source pin. The drain of the JFET chip is soldered onto the drain substrate; The MOSFET chip is stacked on the JFET chip, and the drain of the MOSFET chip is soldered to the source pad of the JFET chip. The source of the MOSFET chip is connected to the source substrate via a first metal lead; The gate of the JFET chip is connected to the source of the MOSFET chip via a second metal lead, and the gate of the JFET chip is connected to the Kelvin source substrate via a third metal lead. The gate of the MOSFET chip is connected to the gate substrate via a fourth metal lead.

2. The circuit according to claim 1, characterized in that, The area of ​​the drain substrate is larger than the area of ​​the source substrate, the gate substrate, and the Kelvin source substrate.

3. The circuit according to claim 1, characterized in that, The drain substrate is made of direct copper-clad ceramic substrate, and the drain of the JFET chip is soldered to the copper-clad surface of the drain substrate.

4. The circuit according to claim 3, characterized in that, The drain of the JFET chip is soldered to the copper-clad surface by silver sintering.

5. The circuit according to claim 1, characterized in that, The diameter of the first metal lead is greater than the diameters of the second, third, and fourth metal leads.

6. The circuit according to claim 5, characterized in that, The number of the first metal leads is at least two.

7. The circuit according to claim 5, characterized in that, The number of the second metal lead is one, and the number of the third metal lead is one.

8. The circuit according to claim 1, characterized in that, The JFET chip is made of silicon carbide, and the MOSFET is made of silicon.

9. A common-source cascode transistor, characterized in that, The common-source common-gate transistor includes: a molding compound and a common-source common-gate circuit as described in any one of claims 1-8. The common-source common-gate circuit includes a JFET chip, a MOSFET chip, a drain substrate, a source substrate, a gate substrate, and a Kelvin source substrate, which are located inside the molding compound, while the drain pin, source pin, gate pin, and Kelvin source pin are located outside the molding compound.

10. The cascode transistor according to claim 9, characterized in that, The drain substrate, the source substrate, the gate substrate, and the Kelvin source substrate are all direct copper-clad ceramic substrates; The direct copper-clad ceramic substrate includes a first copper-clad surface, a ceramic layer, and a second copper-clad surface. The first copper-clad surface and the ceramic layer are located inside the common-source cascode transistor, and the second copper-clad surface is located on the outer surface of the common-source cascode transistor. The drain of the JFET chip is soldered to the first copper-clad surface of the drain substrate. The drain pin is connected to the first copper-clad surface of the drain substrate. The source pin is connected to the first copper-clad surface of the source substrate. The gate pin is connected to the first copper-clad surface of the gate substrate. The Kelvin source pin is connected to the first copper-clad surface of the Kelvin source substrate.

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