Semiconductor device

Abstract

In one embodiment, a semiconductor device includes a plurality of first nanowires extending between a plurality of first source / drain regions, a plurality of second nanowires over the first nanowires and between a plurality of second source / drain regions, a first gate stack around the first nanowires, a second gate stack over the first gate stack and disposed around the second nanowires, wherein a first portion of the second gate stack is disposed over the second nanowires, a plurality of gate spacers over a plurality of sidewalls of the first portion of the second gate stack, and a first metal contact physically contacting a first source / drain region of the second source / drain regions, wherein an air gap is disposed between a sidewall of the first metal contact and a sidewall of a first gate spacer of the gate spacers.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and using photolithography to pattern the various material layers to form circuit elements and components on them.

[0003] The semiconductor industry continuously increases the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, enabling more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Utility Model Content

[0004] Some embodiments of this disclosure provide a semiconductor device including a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. Gate spacers are disposed above the sidewalls of the first portion of the second gate stack. A first metal contact extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein an air gap is disposed between the sidewalls of the first metal contact and the sidewalls of the first gate spacer.

[0005] Some embodiments of this disclosure provide a semiconductor device including a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. Gate spacers are disposed above the sidewalls of the first portion of the second gate stack. A first interlayer dielectric (ILD) is disposed above the back side of the first gate stack. A first metal contact extends through the first portion of the second gate stack and extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein a first air gap is disposed between the sidewalls of the first metal contact and the sidewalls of the first gate spacer. A first back-side metal contact extends through the first interlayer dielectric to physically contact the first source / drain region in the first source / drain region, wherein a second air gap is disposed between the sidewalls of the first back-side metal contact and the sidewalls of the first interlayer dielectric.

[0006] Some embodiments of this disclosure provide a semiconductor device including a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. Gate spacers are disposed above the sidewalls of the first portion of the second gate stack. A first metal contact extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein an air gap is disposed between the sidewalls of the first metal contact and the sidewalls of the first gate spacer. A first spacer layer is disposed above the sidewalls of the first metal contact, wherein the first spacer layer surrounds the first metal contact, and an air gap is disposed between the first spacer layer and the sidewalls of the first gate spacer. Attached Figure Description

[0007] When read in conjunction with the accompanying drawings, the following detailed description will provide the best understanding of all aspects of this disclosure. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1An example schematic diagram of stacked transistors, such as a complementary field-effect transistor (CFET), is shown in a three-dimensional view according to some embodiments.

[0009] Figures 2 to 25D This is a view of an intermediate stage in the fabrication of a complementary field-effect transistor according to some embodiments;

[0010] Figure 26 This is a view of an intermediate stage in the fabrication of a complementary field-effect transistor according to other embodiments.

[0011] [Symbol Explanation]

[0012] 50:Substrate

[0013] 52: Multi-layer stacking

[0014] 54: Virtual Layer

[0015] 54A: First Virtual Layer

[0016] 54B: Second Virtual Layer

[0017] 56: Semiconductor layer

[0018] 56L: Lower semiconductor layer

[0019] 56U: Upper semiconductor layer

[0020] 62: Fins

[0021] 64: Nanostructures

[0022] 64A: First Virtual Nanostructure

[0023] 64B: Second Virtual Nanostructure

[0024] 66: Nanostructures

[0025] 66L: Lower Semiconductor Nanostructure

[0026] 66M: Semiconductor Nanostructures

[0027] 66U: Semiconductor Nanostructure

[0028] 70: Quarantine Zone

[0029] 72: Dummy Dielectric Layer

[0030] 74: Dummy gate layer

[0031] 76: Masking layer

[0032] 82: Dummy Dielectric

[0033] 84: Dummy gate

[0034] 86: Mask

[0035] 90: Gate spacer

[0036] 90A: Gate spacer

[0037] 90B: Gate spacer

[0038] 94: Source / Drain Recess

[0039] 94A: First source / drain recess

[0040] 94B: Second source / drain recess

[0041] 94C: Third source / drain dip

[0042] 95: Zone 1

[0043] 96A: Sidewall concavity

[0044] 96B: Open

[0045] 97: Second District

[0046] 98: Internal spacers

[0047] 99: Third District

[0048] 100: Isolation Structure

[0049] 108: Source / Drain Region

[0050] 108L: Lower epitaxial source / drain region

[0051] 108U: Epitaxial Source / Drain Region

[0052] 112: First contact etch stop layer

[0053] 114: First layer interlayer dielectric

[0054] 120: Semiconductor device

[0055] 122: Second contact etch stop layer

[0056] 124: Second layer interlayer dielectric

[0057] 126: Etching Stop Layer

[0058] 128: Third interlayer dielectric

[0059] 132: Gate Dielectric

[0060] 134: Gate electrode

[0061] 134L: Lower gate electrode

[0062] 134U: Upper gate electrode

[0063] 134U1 First Gate Electrode Layer

[0064] 134U2 Second Gate Electrode Layer

[0065] 134U3 Third Gate Electrode Layer

[0066] 136: Opening

[0067] 136A: Opening

[0068] 136B: Opening

[0069] 136C: Open

[0070] 137: Protective layer

[0071] 138: Sacrifice Layer

[0072] 139: Sacrificial spacer

[0073] 140: Spacer

[0074] 142: Metal-Semiconductor Alloy Region

[0075] 143: Conductive materials

[0076] 144: Metal Contacts

[0077] 146: Air gap

[0078] 148: Dielectric layer

[0079] 149: Bitline

[0080] 150: Dielectric layer

[0081] 151: Etching Stop Layer

[0082] 152: Contact perforation

[0083] 153: Contact perforation

[0084] 154: Etching Stop Layer

[0085] 156: Interlayer Dielectric

[0086] 158: Interlayer Dielectric

[0087] 159: Opening

[0088] 159A: Opening

[0089] 159B: Opening

[0090] 159C: Opening

[0091] 160: Sacrificial spacer

[0092] 162: Spacer

[0093] 164: Metal-Semiconductor Alloy Region

[0094] 165: Conductive materials

[0095] 166: Metal Contacts

[0096] 167: Contact perforation

[0097] 168: Air gap

[0098] 170: Dielectric layer

[0099] 172: Conductive wire

[0100] 174: Dielectric layer

[0101] 176: Conductive wire

[0102] 178: Etching Stop Layer

[0103] 180: Isolation Structure

[0104] A-A': Cross section

[0105] B-B': Cross section

[0106] BL: Bitline

[0107] D-D': line

[0108] E-E': line

[0109] PD: Pull-down transistor

[0110] PG: Transmission gate transistor

[0111] PU: Pull-down transistor

[0112] VSS: Voltage source supply

[0113] W1: Width

[0114] W2: Width

[0115] W3: Width

[0116] W4: Width Detailed Implementation

[0117] The following disclosure provides numerous different embodiments or examples of various features for implementing this disclosure. Specific examples of elements and arrangements are described below to simplify the content of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the description below, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Additionally, reference numerals and / or words may be repeated in various examples. This repetition is for simplicity and clarity and is not, in itself, merely a relationship between the various embodiments and / or configurations discussed.

[0118] Furthermore, the spatially related terms used herein, such as “below,” “under,” “below,” “above,” and “on,” are for descriptive purposes to describe the relationship between one element or feature and another, as shown in the figures. These spatially related terms are intended to cover different orientations of the device during use or operation, in addition to those shown in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein can be interpreted accordingly.

[0119] According to various embodiments, a complementary field-effect transistor (CFET) is formed. The CFET includes a lower nanostructure transistor and an upper nanostructure transistor. For example, in one embodiment, the CFET may be configured as part of a Static Random Memory (SRAM) cell, the CFET including an n-type nanostructure transistor (e.g., an upper nanostructure transistor) in the N-channel metal-oxide-semiconductor (NMOS) portion of the CFET and a p-type nanostructure transistor (e.g., a lower nanostructure transistor) in the P-channel metal-oxide-semiconductor (PMOS) portion of the CFET. The NMOS portion of the CFET may be disposed in a region of the SRAM cell, hereinafter referred to as the NMOS portion of the SRAM cell. The PMOS portion of the CFET may be disposed in a region of the SRAM cell, hereinafter referred to as the PMOS portion of the SRAM cell. In one embodiment, an air gap may be formed around bit line contacts (e.g., electrically connecting bit lines) in the bit line (BL) region of the NMOS portion of the static random-access memory (SRAM) cell. However, no air gap is formed in the node region of the NMOS portion of the SRAM cell to surround the first node contacts (e.g., electrically connecting internal storage nodes), nor is an air gap formed to surround voltage source supply (VSS) contacts (e.g., electrically connecting the source of the NMOS portion of a complementary field-effect transistor) in the first region of the NMOS portion of the SRAM cell. The air gap can be formed by first depositing a sacrificial silicon layer. The sacrificial silicon layer is then selectively removed to leave space where the sacrificial silicon layer was previously deposited. Furthermore, an air gap can be formed in the node region of the PMOS portion of the static random access memory cell to surround the second node contact (e.g., electrically connectable to the internal storage node), and an air gap can be formed in the first region of the PMOS portion of the static random access memory cell to surround the voltage drain supply (VDD) contact (e.g., electrically connectable to the source of the PMOS portion of the complementary field-effect transistor).

[0120] Advantageous features of one or more embodiments disclosed herein allow for a reduction in capacitance associated with bit line contacts. As a result, the total capacitance of the bit lines in the static random access memory (SRAM) cell can be reduced, and less charge is required to change the bit line voltage during read / write operations. This makes read / write operations in the SRAM cell faster. Therefore, the speed of SRAM cell operation can be improved. Furthermore, since no air gap is formed around the first node contact and the voltage source supply (VSS) contact in the NMOS portion of the SRAM cell, the VSS contact and the first node contact can be formed with larger dimensions (e.g., a larger width) because there is no need to accommodate the space occupied by the air gap. The increased size of the first node contact and the VSS contact reduces the resistance through these contacts, thereby improving the efficiency of the SRAM cell. Furthermore, by selectively adding air gaps around the second node contact and VDD contact in the PMOS portion of the static random access memory cell, a better match can be achieved between the device performance of the n-type nanostructure transistor in the NMOS portion of the complementary field-effect transistor and the device performance of the p-type nanostructure transistor in the PMOS portion of the complementary field-effect transistor.

[0121] Figure 1 Example schematic diagrams of stacked transistors, such as complementary field-effect transistors (CFETs), are shown according to some embodiments. Figure 1 This is a 3D view; for clarity, some features of the complementary field-effect transistor have been omitted.

[0122] Complementary field-effect transistors (CFPTs) comprise multiple vertically stacked nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, multi-bridge channel (MBC) transistors, nanoribbon transistors, gate-all-around (GAA) transistors, etc.). For example, a complementary field-effect transistor may include a lower nanostructure transistor of a first device type (e.g., n-type / p-type) and an upper nanostructure transistor of a second device type (e.g., p-type / n-type), the second device type being the opposite of the first. Specifically, a complementary field-effect transistor may include a lower PMOS transistor and an upper NMOS transistor, or vice versa. Each nanostructure transistor includes a semiconductor nanostructure 66 (including a lower semiconductor nanostructure 66L and an upper semiconductor nanostructure 66U), with the semiconductor nanostructure 66 serving as the channel region of the nanostructure transistor. The semiconductor nanostructure 66 may be a nanosheet, nanowire, etc. The lower semiconductor nanostructure 66L is used for the lower nanostructure transistor, and the upper semiconductor nanostructure 66U is used for the upper nanostructure transistor. Channel isolation material (in) Figure 1 It is not explicitly stated in the text that the reference is... Figure 19A and Figure 19B It can be used to separate and electrically insulate the upper semiconductor nanostructure 66U and the lower semiconductor nanostructure 66L.

[0123] Gate dielectric 132 extends along the top, sidewalls, and bottom surface of semiconductor nanostructure 66. Gate electrodes 134 (including a lower gate electrode 134L and an upper gate electrode 134U) are located above gate dielectric 132 and surround semiconductor nanostructure 66. Source / drain regions 108 (including a lower epitaxial source / drain region 108L and an upper epitaxial source / drain region 108U) are disposed on opposite sides of gate dielectric 132 and gate electrode 134. Source / drain regions 108 may individually or integrally refer to a source or drain, depending on the context. Isolation features may be formed to separate a desired source / drain region 108 and / or a desired gate electrode 134. For example, lower gate electrode 134L may optionally be separated from upper gate electrode 134U. Alternatively, lower gate electrode 134L may be coupled to upper gate electrode 134U. Furthermore, upper epitaxial source / drain region 108U may be separated by one or more dielectric layers (in... Figure 1 It is not explicitly stated in the text that the reference is... Figure 19A and Figure 19BThe gate and source / drain regions are separated from the epitaxial source / drain region 108L. This isolation feature between the channel region, gate, and source / drain regions allows for vertically stacked transistors, thus improving device density. Due to the vertical stacking characteristics of complementary field-effect transistors, this schematic diagram can also be referred to as a stacked transistor or a folding transistor.

[0124] Figure 1 Further, reference cross sections used in the following figures are shown. Reference cross section A-A' is parallel to the longitudinal axis of the semiconductor nanostructure 66 of the complementary field-effect transistor (FET) and, for example, the direction of current between the source / drain regions 108 of the FET. Cross section B-B' is perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 134 of the FET. For clarity, these reference cross sections are referenced in the following figures.

[0125] Some of the embodiments discussed herein are discussed in the context of complementary field-effect transistors. Other embodiments may be considered from aspects used in nanostructure transistors (e.g., nanowire transistors, nanosheet transistors, multi-bridge channel (MBC) transistors, nanoribbon transistors, gate-all-around (GAA) transistors, etc.).

[0126] Figures 2 to 26 This is a view of an intermediate stage in the manufacture of a semiconductor device 120 including a complementary field-effect transistor, according to some embodiments. Figure 2 , Figure 3 and Figure 4 It is shown as follows Figure 1 A 3D view similar to a 3D view. Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 , Figure 15 , Figure 16 , Figure 17 , Figure 18A , Figure 18B , Figure 19A , Figure 20 , Figure 21 , Figure 22 , Figure 23 , Figure 24 , Figure 25A and Figure 26 Show along such Figure 1 A cross-sectional view of a cross section similar to the reference cross section A-A'. Figure 19B Show along such Figure 1 A cross-sectional view of a cross section similar to the reference cross section B-B'.

[0127] exist Figure 2 In this embodiment, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor or a semiconductor-on-insulator (SOI) substrate, and can be doped (e.g., doped with p-type or n-type doping) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. Generally, a semiconductor-on-insulator substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer, typically a silicon substrate or a glass substrate, is provided above the substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, compound semiconductors including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide, or combinations thereof.

[0128] A multilayer stack 52 is formed above the substrate 50. The multilayer stack 52 includes alternating dummy layers 54 (including a first dummy layer 54A and a second dummy layer 54B) and semiconductor layers 56 (including a lower semiconductor layer 56L and an upper semiconductor layer 56U). A subset of the lower semiconductor layer 56L and the first dummy layer 54A is disposed below the second dummy layer 54B. Another subset of the upper semiconductor layer 56U and the first dummy layer 54A is disposed above the second dummy layer 54B. As will be described in more detail later, the dummy layers 54 will be removed and the semiconductor layers 56 will be patterned to form channel regions of complementary field-effect transistors (CFPTs). Specifically, the lower semiconductor layer 56L will be patterned to form channel regions of the lower nanostructure transistors of the complementary field-effect transistors, and the upper semiconductor layer 56U will be patterned to form channel regions of the upper nanostructure transistors of the complementary field-effect transistors.

[0129] The multilayer stack 52 is shown as including a specific number of dummy layers 54 and a specific number of semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of dummy layers 54 and semiconductor layers 56. Each layer of the multilayer stack 52 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0130] The first dummy layer 54A is formed of a first semiconductor material, and the second dummy layer 54B is formed of a second semiconductor material. The first and second semiconductor materials can be selected from candidate semiconductor materials of the substrate 50. The semiconductor materials of the first dummy layer 54A and the second dummy layer 54B will be described in more detail later. The first and second semiconductor materials have high etch selectivity towards each other. Thus, the material of the second dummy layer 54B can be removed at a higher rate in subsequent processes than the material of the first dummy layer 54A.

[0131] Semiconductor layer 56 (including lower semiconductor layer 56L and upper semiconductor layer 56U) is formed of one or more semiconductor materials. The semiconductor materials can be selected from candidate semiconductor materials of substrate 50. Lower semiconductor layer 56L and upper semiconductor layer 56U can be formed of the same semiconductor material or different semiconductor materials. In some embodiments, both lower semiconductor layer 56L and upper semiconductor layer 56U are formed of semiconductor materials suitable for both p-type and n-type devices, such as silicon. In some embodiments, lower semiconductor layer 56L is formed of a semiconductor material suitable for p-type devices, such as germanium or silicon-germanium, and upper semiconductor layer 56U is formed of a semiconductor material suitable for n-type devices, such as silicon or carbon-doped silicon. The semiconductor material of semiconductor layer 56 will be described in more detail later. The semiconductor material of semiconductor layer 56 has high etch selectivity for the semiconductor material of dummy layer 54. Thus, the material of dummy layer 54 can be removed at a higher rate in subsequent processes than the material of semiconductor layer 56.

[0132] Some layers of the multilayer stack 52 may be thicker than other layers of the multilayer stack 52. The thickness of the second dummy layer 54B may be different (e.g., greater than or less than) the thickness of each first dummy layer 54A. In some embodiments, the second dummy layer 54B has a small thickness, for example, less than the thickness of each first dummy layer 54A. In other embodiments, the second dummy layer 54B has a large thickness, for example, greater than the thickness of each first dummy layer 54A. Furthermore, the thickness of each semiconductor layer 56 may be different (e.g., greater than or less than) the thickness of each first dummy layer 54A and / or the second dummy layer 54B. In some embodiments, the second dummy layer 54B may be thicker than each semiconductor layer 56. In other embodiments, each semiconductor layer 56 may be thicker than each dummy layer 54.

[0133] In some embodiments, the first dummy layer 54A is formed of silicon-germanium, the second dummy layer 54B is formed of doped silicon, and the semiconductor layer 56 is formed of silicon. The silicon in the semiconductor layer 56 may be undoped or lightly doped at this step of the process. In some embodiments, the second dummy layer 54B is formed of silicon doped with n-type or p-type impurities. The n-type impurity may be phosphorus, arsenic, etc. The p-type impurity may be boron, etc. Using doped silicon in the second dummy layer 54B allows for high etch selectivity for both the first dummy layer 54A and the second dummy layer 54B. For example, the second dummy layer 54B may be at least partially replaced by an isolation structure. As part of a replacement process, the second dummy layer 54B may be removed by an etchant that is selective for the second dummy layer 54B. Therefore, the second dummy layer 54B can be removed at a higher rate than the first dummy layer 54A and the semiconductor layer 56.

[0134] exist Figure 3In this embodiment, fins 62 are formed in substrate 50, and nanostructures 64 and 66 (including a first dummy nanostructure 64A, a second dummy nanostructure 64B, a lower semiconductor nanostructure 66L, a middle semiconductor nanostructure 66M, and an upper semiconductor nanostructure 66U) are formed in a multilayer stack 52. In some embodiments, nanostructures 64 and 66 and fins 62 can be formed in the multilayer stack 52 and substrate 50, respectively, by etching trenches in the multilayer stack 52 and substrate 50. Etching can be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. Etching can be anisotropic. Nanostructures 64 and 66 formed by etching multiple layers stacked 52 can be defined as follows: a first dummy nanostructure 64A from a first dummy layer 54A; a second dummy nanostructure 64B from a second dummy layer 54B; a lower semiconductor nanostructure 66L from some lower semiconductor layers 56L; an upper semiconductor nanostructure 66U from some upper semiconductor layers 56U; and a middle semiconductor nanostructure 66M from some lower semiconductor layers 56L and some upper semiconductor layers 56U. The first dummy nanostructure 64A and the second dummy nanostructure 64B can be further collectively referred to as dummy nanostructure 64. The lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U can be further collectively referred to as semiconductor nanostructure 66.

[0135] As described in more detail later, various nanostructures 64, 66 will be removed to form the channel region of the complementary field-effect transistor. Specifically, the lower semiconductor nanostructure 66L will serve as the channel region of the lower nanostructure transistor of the complementary field-effect transistor. Furthermore, the upper semiconductor nanostructure 66U will serve as the channel region of the upper nanostructure transistor of the complementary field-effect transistor.

[0136] The middle semiconductor nanostructure 66M is a semiconductor nanostructure 66, located directly above / below (e.g., at a contact point) the second dummy nanostructure 64B. Depending on the height of the subsequently formed source / drain regions, the middle semiconductor nanostructure 66M may or may not be adjacent to any source / drain regions, and may or may not serve as a functional channel region for the complementary field-effect transistor. The second dummy nanostructure 64B will subsequently be replaced by an isolation structure. The isolation structure and the middle semiconductor nanostructure 66M define the boundary between the lower and upper nanostructure transistors.

[0137] The fins 62 and nanostructures 64, 66 can be patterned using appropriate methods. For example, the fins 62 and nanostructures 64, 66 can be patterned using one or more photolithography processes that include dual or multiple patterning processes. Generally, dual or multiple patterning processes combine photolithography and self-alignment processes to form patterns with, for example, a spacing smaller than that obtained by a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can subsequently be used to pattern the fins 62 and nanostructures 64, 66. In some embodiments, a mask (or other layer) may be retained over the nanostructures 64, 66.

[0138] Although each fin 62 and nanostructure 64, 66 is shown to have a generally constant width, in other embodiments, the fin 62 and / or nanostructure 64, 66 may have sloping sidewalls such that the width of each fin 62 and / or nanostructure 64, 66 continuously increases in the direction toward the substrate 50. In this embodiment, each nanostructure 64, 66 may have a different width and be trapezoidal.

[0139] Further, isolation region 70 is formed over substrate 50 and between adjacent semiconductor fins 62. Isolation region 70 may include pads and filler material above the pads. Each pad and filler material may include a dielectric material, such as an oxide (e.g., silicon oxide), a nitride (e.g., silicon nitride), or a combination thereof. Formation of isolation region 70 may include depositing dielectric material and performing planarization processes, such as chemical mechanical polishing (CMP), mechanical polishing, etc., to remove excess portions of the dielectric material, such as those above nanostructures 64, 66. Deposition processes may include ALD, high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), etc., or combinations thereof. In some embodiments, isolation region 70 includes silicon oxide formed by an FCVD process followed by an annealing process. The dielectric material is then recessed to define isolation region 70. The dielectric material can be recessed so that the upper part of the semiconductor fins 62 and nanostructures 64 and 66 extends above the isolation region 70.

[0140] The previously described process is merely one example of how fins 62 and nanostructures 64, 66 can be formed. In some embodiments, fins 62 and / or nanostructures 64, 66 can be formed using masking and epitaxial growth processes. For example, a dielectric layer can be formed above the top surface of substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form fins 62 and / or nanostructures 64, 66. The epitaxial structures may include the previously described alternating semiconductor materials, such as a first semiconductor material, a second semiconductor material, and doped silicon of the second dummy nanostructure 64B. In some embodiments, when the epitaxial structure is epitaxially grown, the epitaxial growth material can be in-situ doped during growth, which eliminates the need for prior and / or subsequent implantation, although in-situ and implemented doping can be used together.

[0141] In one embodiment, the semiconductor nanostructure 66 may have a lower doping concentration than the first dummy nanostructure 64A. In some embodiments, the first dummy nanostructure 64A has a doping concentration greater than 10. 20 atom / cm 3 The doping concentration, while the semiconductor nanostructure 66 has a doping concentration of 10 17 atom / cm 3 Up to 10 19 atom / cm 3 The doping concentration is within a certain range. Therefore, the desired etching selectivity among the materials of the first dummy nanostructure 64A, the second dummy nanostructure 64B, and the semiconductor nanostructure 66 can still be achieved. Therefore, as described in more detail later, the removal rate of the first dummy nanostructure 64A can be faster than the removal rates of the second dummy nanostructure 64B and the semiconductor nanostructure 66.

[0142] exist Figure 4In this configuration, a dummy dielectric layer 72 is formed over fins 62 and / or nanostructures 64, 66. The dummy dielectric layer 72 can be, for example, silicon oxide, silicon nitride, combinations thereof, etc., and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a masking layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dummy dielectric layer 72 and then planarized by a process such as chemical mechanical planarization (CMP). The masking layer 76 can be deposited over the dummy gate layer 74. The dummy gate layer 74 can be a conductive or non-conductive material and can be selected from the group including amorphous silicon, polysilicon, poly-SiGe, metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 74 can be deposited using physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing selected materials. The dummy gate layer 74 can be formed of other materials having high etch selectivity for insulating materials. The mask layer 76 may include, for example, silicon nitride, silicon oxynitride, etc. In the illustrated embodiment, the dummy dielectric layer 72 covers the isolation region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the isolation region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or nanostructures 64, 66.

[0143] exist Figure 5 In this process, mask layer 76 can be patterned using acceptable photolithography and etching techniques to form mask 86. The pattern of mask 86 can then be transferred to dummy gate layer 74 and dummy dielectric layer 72 to form dummy gate 84 and dummy dielectric 82, respectively. Dummy gate 84 covers the respective channel regions of nanostructures 64, 66. The pattern of mask 86 can be used to physically separate each dummy gate 84 from adjacent dummy gates 84. Dummy gate 84 may also have a length direction substantially perpendicular to the length direction of the individual fins 62. After patterning, such as by any acceptable etching technique, mask 86 can optionally be removed.

[0144] exist Figure 6In this configuration, gate spacer 90 is formed over nanostructures 64 and 66 and over the exposed sidewalls of mask 86 (if present), dummy gate 84, and dummy dielectric 82. Gate spacer 90 can be formed by conformally forming one or more dielectric materials, followed by etching. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may also be used. Any acceptable etching process, such as dry etching, wet etching, etc., or combinations thereof, can be performed to pattern the dielectric material. Etching may be anisotropic. During etching, the dielectric material has a portion remaining over the sidewalls of dummy gate 84 (thus forming gate spacer 90). In some embodiments, the dielectric material may also have a portion remaining over the sidewalls of fin 62 and / or nanostructures 64 and 66 during etching.

[0145] Furthermore, implantation for lightly doped source / drain (LDD) regions (not described separately) can be performed. Lightly doped source / drain implantation can be performed before the formation of the gate spacer 90. Appropriate types of impurities can be implanted to the desired depth of the nanostructures 64, 66. The lightly doped source / drain regions may have the same conductivity type as the source / drain regions, which will subsequently be formed between the semiconductor nanostructures 66. Additionally, the lightly doped source / drain regions in the lower semiconductor nanostructure 66L may have an opposite conductivity type to the lightly doped source / drain regions in the upper semiconductor nanostructure 66U. In some embodiments, the lower semiconductor nanostructure 66L has p-type lightly doped source / drain regions, and the upper semiconductor nanostructure 66U has n-type lightly doped source / drain regions. In some embodiments, the lower semiconductor nanostructure 66L has n-type lightly doped source / drain regions, and the upper semiconductor nanostructure 66U has p-type lightly doped source / drain regions. The n-type impurity can be any n-type impurity discussed previously, and the p-type impurity can be any p-type impurity discussed previously. The lightly doped source / drain regions can have a doping level of 10. 17 atom / cm 3 Up to 10 20 atom / cm 3 The impurity concentration is within a certain range. Annealing can be used to repair implant damage and can activate implant impurities. In some embodiments, the growth material of nanostructures 64, 66 can be doped in situ during growth, which can eliminate the need for implantation, although in-situ and implantation doping can be used together.

[0146] It is worth noting that previous disclosures typically describe the process for forming spacers and lightly doped source / drain regions. Other processes and sequences are also possible. For example, fewer or additional spacers can be used, different sequences of steps can be used, additional spacers can be formed and removed, and / or so on.

[0147] Source / drain recesses 94 are formed in the fins 62, nanostructures 64, 66, and substrate 50. For example, a first source / drain recess 94A may be formed in the fins 62, nanostructures 64, 66, and substrate 50 in a first region 95 of the semiconductor device 120; a second source / drain recess 94B may be formed in the fins 62, nanostructures 64, 66, and substrate 50 in a second region 97 of the semiconductor device 120; and a third source / drain recess 94C may be formed in the fins 62, nanostructures 64, 66, and substrate 50 in a third region 99 of the semiconductor device 120. Epitaxial source / drain regions will then be formed in the source / drain recesses 94. The source / drain recesses 94 may extend through the nanostructures 64, 66 and into the substrate 50. The etchable fins 62 allow the bottom surface of the source / drain recess 94 to be positioned above, below, or flush with the top surface of the isolation region 70. In the example shown, the top surface of the isolation region 70 is above the bottom surface of the source / drain recess 94. The source / drain recess 94 can be formed by etching the fins 62, nanostructures 64, 66, and substrate 50 using anisotropic etching processes such as RIE, NBE, etc. During the etching process used to form the source / drain recess 94, the gate spacer 90 and the fins 62, nanostructures 64, 66, and substrate 50 are masked. A single etching process or multiple etching processes can be used to etch each layer of nanostructures 64, 66, and / or fins 62. After the source / drain recess 94 reaches the desired depth, timed etch processes can be used to stop the etching of the source / drain recess 94.

[0148] exist Figure 7 In this process, the sidewalls of the first dummy nanostructure 64A, exposed by the source / drain recess 94, are recessed to form a sidewall recess 96A. Furthermore, the second dummy nanostructure 64B is removed to form an opening 96B between the lower semiconductor nanostructure 66L (collectively referred to as the lower semiconductor nanostructure 66L) and the upper semiconductor nanostructure 66U (collectively referred to as the upper semiconductor nanostructure 66U). The sidewall recess 96A is then filled with a spacer. The opening 96B is then filled with an isolation structure.

[0149] The sidewall recess 96A can be formed by recessing the first dummy nanostructure 64A using any acceptable etching process. The etching is selective for the first dummy nanostructure 64A (e.g., selectively etching the material of the first dummy nanostructure 64A at a rate faster than the material of the semiconductor nanostructure 66). The etching can be isotropic. Although the sidewalls of the first dummy nanostructure 64A appear straight after etching, the sidewalls of the first dummy nanostructure 64A can be concave or convex.

[0150] The opening 96B can be formed by removing the second dummy nanostructure 64B using any acceptable etching process. The etching is selective for the second dummy nanostructure 64B (e.g., selectively etching the material of the second dummy nanostructure 64B at a rate faster than the material of the semiconductor nanostructure 66). The etching can be isotropic. The dummy gate 84 can adhere to and support the upper semiconductor nanostructure 66U such that the upper semiconductor nanostructure 66U does not collapse after the opening 96B is formed.

[0151] In some embodiments, the same etching process is used to recess the sidewalls of the first dummy nanostructure 64A and remove the second dummy nanostructure 64B. For example, the second dummy nanostructure 64B can be completely removed without completely removing the first dummy nanostructure 64A, and the first dummy nanostructure 64A can be recessed without significantly recessing the semiconductor nanostructure 66. The etching process is selective among the first dummy nanostructure 64A, the second dummy nanostructure 64B, and the semiconductor nanostructure 66. Specifically, the etching process selectively etches the material of the first dummy nanostructure 64A at a rate faster than the material of the semiconductor nanostructure 66, and also selectively etches the material of the second dummy nanostructure 64B at a rate faster than the material of the first dummy nanostructure 64A. Therefore, the etching rate of the first dummy nanostructure 64A is less than the etching rate of the second dummy nanostructure 64B, but greater than the etching rate of the semiconductor nanostructure 66. In some embodiments, the first dummy nanostructure 64A is formed of silicon-germanium, the second dummy nanostructure 64B is formed of doped silicon with a high doping concentration, and the semiconductor nanostructure 66 is formed of doped silicon with a low doping concentration. The etching process is dry etching using chlorine gas, with or without plasma. The etching process etches the doped silicon with a high doping concentration at a faster rate than the doped silicon with a low doping concentration.

[0152] The intermediate semiconductor nanostructure 66M is exposed through opening 96B. In some embodiments, an etching process thins the intermediate semiconductor nanostructure 66M. Furthermore, the thickness of the intermediate semiconductor nanostructure 66M may be different from (e.g., less than) the thickness of the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U. In some embodiments, after the etching process, the thickness of the intermediate semiconductor nanostructure 66M is 0% to 20% thinner than the thickness of the lower semiconductor nanostructure 66L and the upper semiconductor nanostructure 66U.

[0153] exist Figure 8 Internal spacers 98 are formed in the sidewall recesses 96A and above the sidewalls of the reserved portion of the first dummy nanostructure 64A. As will be described in more detail later, source / drain regions will then be formed in the source / drain recesses 94, and the first dummy nanostructure 64A will be replaced by a corresponding gate structure. The internal spacers 98 serve as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacers 98 can be used to prevent damage to the subsequently formed source / drain regions by subsequent etching processes (e.g., etching processes for forming the gate structure). Additionally, isolation structures 100 are formed in the openings 96B and between the intermediate semiconductor nanostructures 66M. The isolation structures 100 and the intermediate semiconductor nanostructures 66M will define the boundaries between the lower and upper nanostructure transistors.

[0154] The internal spacer 98 and the isolation structure 100 are formed by conformally forming an insulating material in the source / drain recess 94, the sidewall recess 96A, and the opening 96B, followed by etching of the insulating material. In one embodiment, the insulating material may be different from the dielectric material of the gate spacer 90. The insulating material may be a carbon-containing dielectric material, such as silicon carbonitride, silicon carbon oxynitride, silicon oxynitride, etc. Other low-k materials with a k value of less than about 3.5 may be used. The insulating material may be formed by a deposition process such as ALD, CVD, etc. The etching of the insulating material may be anisotropic. For example, the etching process may be dry etching such as RIE, NBE, etc. When etched, the insulating material is partially retained in the sidewall recess 96A (thus forming the internal spacer 98) and partially retained in the opening 96B (thus forming the isolation structure 100).

[0155] Although the outer walls of the internal spacers 98 and the isolation structure 100 are shown flush with the sidewalls of the semiconductor nanostructure 66, the outer walls of the internal spacers 98 and the isolation structure 100 may extend beyond or recess from the sidewalls of the semiconductor nanostructure 66. Therefore, the internal spacers 98 and the isolation structure 100 may partially fill, fully fill, or overfill the sidewall recesses 96A and openings 96B, respectively. Furthermore, although the sidewalls of the internal spacers 98 and the isolation structure 100 are shown as straight, those sidewalls may be concave or convex.

[0156] The isolation structure 100 has a similar size to the second dummy nanostructure 64B that it replaces. Furthermore, the isolation structure 100 may have a large thickness, for example, greater than the semiconductor nanostructure 66 and the first dummy nanostructure 64A, or the isolation structure 100 may have a small thickness, for example, smaller than the semiconductor nanostructure 66 and the first dummy nanostructure 64A.

[0157] exist Figure 9 In this embodiment, a suitable masking layer (e.g., photoresist, bottom anti-reflective coating (BARC), etc.) may be formed in a first source / drain recess 94A in a first region 95 of the semiconductor device 120 to mask the first source / drain recess 94A. Simultaneously, a lower epitaxial source / drain region 108L is formed in a second source / drain recess 94B in a second region 97 and a third source / drain recess 94C in a third region 99. In one embodiment, the second region 97 is disposed between the first region 95 and the third region 99. The lower epitaxial source / drain region 108L is used for the lower nanostructure transistor of a complementary field-effect transistor, such as the PMOS portion of a complementary field-effect transistor of a static random-access memory (SRAM) cell. In one embodiment, the PMOS portion of the complementary field-effect transistor may be disposed in a region of the SRAM cell, which may subsequently be referred to as the PMOS portion of the SRAM cell (e.g., a portion of the semiconductor device 120 is disposed below the isolation structure 100).

[0158] The lower epitaxial source / drain region 108L contacts the lower semiconductor nanostructure 66L but not the upper semiconductor nanostructure 66U. In some embodiments, the lower epitaxial source / drain region 108L applies stress to individual channel regions of the lower semiconductor nanostructure 66L, thereby improving performance. The lower epitaxial source / drain region 108L is formed in the second source / drain recess 94B and the third source / drain recess 94C, such that the stack of lower semiconductor nanostructures 66L is disposed between the lower epitaxial source / drain regions 108L. In some embodiments, an internal spacer 98 is used to separate the lower epitaxial source / drain region 108L and the first dummy nanostructure 64A, which will subsequently be replaced by a gate structure in a subsequent process.

[0159] The lower epitaxial source / drain region 108L is epitaxially grown in the lower portions of the second source / drain recess 94B and the third source / drain recess 94C. For example, the lower epitaxial source / drain region 108L can be grown laterally from the exposed sidewalls of the lower semiconductor nanostructure 66L, or laterally from the bottom surface of the fin 62 / substrate 50 in the source / drain recess 94. During the epitaxy of the lower epitaxial source / drain region 108L, the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U in the second source / drain recess 94B and the third source / drain recess 94C can be masked to prevent unwanted epitaxial growth over the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U. After the lower epitaxial source / drain region 108L is grown, the mask over the middle semiconductor nanostructure 66M and / or the upper semiconductor nanostructure 66U can then be removed. Furthermore, the masking layer in the first source / drain recess 94A in the first region 95 of the semiconductor device 120 can be removed using a suitable etching process. The lower epitaxial source / drain region 108L has a conductivity type suitable for a device type of lower nanostructure transistor. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region, such as the PMOS portion for a complementary field-effect transistor, as an example. In some embodiments, the lower epitaxial source / drain region 108L is an n-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon, the lower epitaxial source / drain region 108L may include a material to which tensile strain is applied to the lower semiconductor nanostructure 66L, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the lower epitaxial source / drain region 108L is a p-type source / drain region. For example, if the lower semiconductor nanostructure 66L is silicon-germanium, then the lower epitaxial source / drain region 108L may include a material to which compressive strain is applied to the lower semiconductor nanostructure 66L, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The lower epitaxial source / drain region 108L may have surfaces protruding from individual upper surfaces of the lower semiconductor nanostructure 66L and have facets.

[0160] In one embodiment, the lower epitaxial source / drain region 108L is in-situ doped during growth. Alternatively, in other embodiments, the lower epitaxial source / drain region 108L may be implanted with dopant to form the source / drain region, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain region may have a [percentage missing] 10 19 atom / cm 3 and 10 21 atom / cm 3 The doping concentration is within the range. The n-type and / or p-type doping used for the source / drain regions can be any of the doping previously discussed.

[0161] Due to the epitaxial process used to form the lower epitaxial source / drain regions 108L, the upper surface of the lower epitaxial source / drain regions 108L has facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent lower epitaxial source / drain regions 108L remain separate after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source / drain regions 108L of the same nanostructure transistor to merge.

[0162] After the lower epitaxial source / drain region 108L is formed, a first contact etchstop layer (CESL) 112 and / or a first inter-layer dielectric (ILD) 114 may also be formed in the source / drain recess 94, for example, above the fin 62 of the first source / drain recess 94A, above the lower epitaxial source / drain region 108L of the second source / drain recess 94B, and above the lower epitaxial source / drain region 108L of the third source / drain recess 94C. The first interlayer dielectric 114 can be disposed between the upper epitaxial source / drain region 108U and the lower epitaxial source / drain region 108L subsequently formed in the second source / drain recess 94B and the third source / drain recess 94C, and between the upper epitaxial source / drain region 108U and the fin 62 subsequently formed in the first source / drain recess 94A.

[0163] The first interlayer dielectric 114 can be formed of a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may be used.

[0164] The first contact etch stop layer 112 can be formed between the first interlayer dielectric 114 and the lower epitaxial source / drain region 108L in the second source / drain recess 94B and the third source / drain recess 94C, and between the first interlayer dielectric 114 and the fin 62 in the first source / drain recess 94A. The first contact etch stop layer 112 can be formed of a dielectric material with high etch selectivity to the dielectric material of the first interlayer dielectric 114, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process such as CVD, ALD, etc.

[0165] The first contact etch stop layer 112 and / or the first interlayer dielectric 114 may be formed by depositing materials for the first contact etch stop layer 112 and for the first interlayer dielectric 114, followed by an etch-back process. In some embodiments, the first interlayer dielectric 114 is first etched, leaving the first contact etch stop layer 112 unetched. An isotropic etching process is then performed to remove the portion of the first contact etch stop layer 112 above the first interlayer dielectric 114. After the recess, the sidewalls of the upper semiconductor nanostructure 66U are exposed in the first source / drain recess 94A, the second source / drain recess 94B, and the third source / drain recess 94C.

[0166] After the first contact etch stop layer 112 and / or the first interlayer dielectric 114 are formed in the source / drain recess 94, an upper epitaxial source / drain region 108U is formed in the source / drain recess 94. The upper epitaxial source / drain region 108U is used for the upper nanostructure transistor of a complementary field-effect transistor, such as the NMOS (N-channel Metal-Oxide-Semiconductor) portion of a complementary field-effect transistor in a static random access memory cell. The first interlayer dielectric 114 thus acts as an isolation region to prevent short circuits between the upper and lower nanostructure transistors. In one embodiment, the NMOS portion of the complementary field-effect transistor may be disposed in a region of the static random access memory cell, which may subsequently be referred to as the NMOS portion of the static random access memory cell (e.g., a portion of the semiconductor device 120 disposed above the isolation structure 100).

[0167] The epitaxial source / drain region 108U contacts the upper semiconductor nanostructure 66U but not the lower semiconductor nanostructure 66L. In some embodiments, the epitaxial source / drain region 108U applies stress to individual channel regions of the upper semiconductor nanostructure 66U to improve performance. The epitaxial source / drain region 108U is formed in the source / drain recess 94 such that each stack of the upper semiconductor nanostructure 66U is disposed between individual adjacent pairs of the epitaxial source / drain region 108U. In some embodiments, an internal spacer 98 is used to separate the epitaxial source / drain region 108U from the first dummy nanostructure 64A, which will be replaced by a gate structure in a subsequent process.

[0168] The upper epitaxial source / drain region 108U is epitaxially grown in the upper portion of the source / drain recess 94 (e.g., first source / drain recess 94A, second source / drain recess 94B, and third source / drain recess 94C). For example, the upper epitaxial source / drain region 108U can be laterally grown from the exposed sidewalls of the upper semiconductor nanostructure 66U. The upper epitaxial source / drain region 108U has a conductivity type suitable for the device type of the upper nanostructure transistor. The conductivity type of the upper epitaxial source / drain region 108U may be relative to the conductivity type of the lower epitaxial source / drain region 108L. In other words, the upper epitaxial source / drain region 108U may be doped opposite to the lower epitaxial source / drain region 108L. In some embodiments, the upper epitaxial source / drain region 108U is an n-type source / drain region, such as the NMOS portion for a complementary field-effect transistor, as an example. For example, if the upper semiconductor nanostructure 66U is silicon, the epitaxial source / drain region 108U may include a material to which tensile stress is applied, such as silicon, carbon-doped silicon, phosphorus-doped silicon, silicon phosphide, silicon arsenide, etc. In some embodiments, the epitaxial source / drain region 108U is a p-type source / drain region. For example, if the upper semiconductor nanostructure 66U is silicon-germanium, the epitaxial source / drain region 108U may include a material to which compressive stress is applied, such as silicon-germanium, boron-doped silicon-germanium, boron-doped silicon, germanium, germanium-tin, etc. The epitaxial source / drain region 108U may have a surface protruding from an individual upper surface of the upper semiconductor nanostructure 66U, and may have facets.

[0169] The epitaxial source / drain regions of 108U can be implanted with dopant to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have a density of 10... 19 atom / cm 3 and 10 21 atom / cm 3The doping concentration is within the range. The n-type and / or p-type doping used for the source / drain regions can be any of the doping previously discussed. In some embodiments, the epitaxial source / drain regions 108U are in-situ doped during growth.

[0170] Due to the epitaxial process used to form the epitaxial source / drain regions 108U, the upper surface of the epitaxial source / drain regions 108U has facets that extend laterally outward beyond the sidewalls of the nanostructures 64, 66. In some embodiments, adjacent epitaxial source / drain regions 108U remain separate after the epitaxial process is completed. In other embodiments, these facets cause adjacent epitaxial source / drain regions 108U of the same nanostructure transistor to merge.

[0171] After the epitaxial source / drain region 108U is formed, a second contact etch stop layer 122 and / or a second interlayer dielectric 124 may also be formed above the epitaxial source / drain region 108U. The second interlayer dielectric 124 is disposed above the epitaxial source / drain region 108U. The second interlayer dielectric 124 can be formed of a dielectric material, which can be deposited by any method, such as CVD, plasma-assisted chemical vapor deposition (PECVD), or FCVD. The dielectric material may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), etc. Other dielectric materials formed by any acceptable process may be used.

[0172] The second contact etch stop layer 122 can be formed between the second interlayer dielectric 124 and the epitaxial source / drain region 108U. The second contact etch stop layer 122 can be formed of a dielectric material with high etch selectivity to the dielectric material of the second interlayer dielectric 124, such as silicon nitride, silicon oxide, silicon oxynitride, etc., and can be formed by any suitable deposition process such as CVD, ALD, etc.

[0173] The second contact etch stop layer 122 and / or the second interlayer dielectric 124 may be formed by depositing materials for the second contact etch stop layer 122 and for the second interlayer dielectric 124. A removal process is then performed to make the top surface of the second interlayer dielectric 124 flush with the top surface of the gate spacer 90 and the mask 86 (if present) or dummy gate 84. In some embodiments, a planarization process may be used, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, etc. The planarization process may also remove the mask 86 above the dummy gate 84 and a portion of the gate spacer 90 along the sidewalls of the mask 86. After the planarization process, the top surfaces of the second interlayer dielectric 124, the gate spacer 90, and the mask 86 (if present) or dummy gate 84 are substantially coplanar (within process variations). Therefore, the top surface of the mask 86 (if present) or dummy gate 84 is exposed through the second interlayer dielectric 124. In the illustrated embodiment, the mask 86 is retained after the removal process. In other embodiments, the mask 86 is removed, so that the top surface of the dummy gate 84 is exposed through the second interlayer dielectric 124.

[0174] exist Figure 10 In one or more etching steps, a dummy gate 84 is removed, causing a recess to form between gate spacers 90. A portion of the dummy dielectric 82 in the recess is also removed. In some embodiments, the dummy gate 84 and dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gases to selectively etch the material of the dummy gate 84 at a rate faster than the materials of the second interlayer dielectric 124, the isolation structure 100, the internal spacers 98, and the gate spacers 90. Each recess between the gate spacers 90 exposes and / or covers a portion of the nanostructures 64, 66 that act as channel regions in the formed device. The portion of the nanostructures 64, 66 acting as channel regions are disposed between adjacent pairs of the lower epitaxial source / drain region 108L or between adjacent pairs of the upper epitaxial source / drain region 108U. During removal, the dummy dielectric 82 can be used to etch a stop layer while the dummy gate 84 is etched. After the dummy gate 84 is removed, the dummy dielectric 82 can then be removed.

[0175] Next, the retained portion of the first dummy nanostructure 64A is removed to form openings in the region between the semiconductor nanostructures 66. The retained portion of the first dummy nanostructure 64A can be removed by any acceptable etching process, selectively etching the material of the first dummy nanostructure 64A at a rate faster than the materials of the semiconductor nanostructure 66, the internal spacer 98, and the isolation structure 100. The etching can be isotropic. For example, when the first dummy nanostructure 64A is formed of silicon germanium, the semiconductor nanostructure 66 is formed of silicon, the internal spacer 98 is formed of silicon carbonitride, and the isolation structure 100 is formed of silicon carbonitride, the etching process can be wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), etc. In some embodiments, a trimming process (not described separately) is performed to reduce the thickness of the exposed portions of the semiconductor nanostructure 66 and to extend the openings between the semiconductor nanostructures 66.

[0176] Next, gate dielectric 132 and gate electrode 134 (including lower gate electrode 134L and upper gate electrode 134U) are formed to replace the gate. Each pair of gate dielectric 132 and gate electrode 134 (including upper gate electrode 134U and / or lower gate electrode 134L) may be collectively referred to as a "gate structure". Each pair of gate dielectric 132 and gate electrode 134 (including upper gate electrode 134U and / or lower gate electrode 134L) may also be collectively referred to as a "gate stack". Each gate structure extends along at least three sides (e.g., top surface, sidewalls, and bottom surface) of the channel region of the semiconductor nanostructure 66. The gate structure may also extend along the sidewalls and / or top surface of the semiconductor fin 62.

[0177] Gate dielectric 132 includes one or more gate dielectric layers disposed around the lower semiconductor nanostructure 66L, the upper semiconductor nanostructure 66U, and the isolation structure 100. Specifically, gate dielectric 132 is disposed above the top surface of fin 62, above the top surface, sidewalls, and bottom surface of semiconductor nanostructure 66, and above the sidewalls of gate spacer 90. Gate dielectric 132 surrounds all (e.g., four) sides of semiconductor nanostructure 66. Gate dielectric 132 may be formed of oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, etc. Additionally or alternatively, gate dielectric 132 may be formed of a high dielectric constant dielectric material (e.g., a dielectric material having a k-value greater than about 7.0), such as hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, metal oxides or silicates. The dielectric material of gate dielectric 132 may be formed by molecular beam deposition (MBD), ALD, PECVD, etc. Although a single-layer gate dielectric 132 is shown, the gate dielectric 132 may include any number of interface layers and any number of main layers. For example, the gate dielectric 132 may include a dielectric layer and an upper high-dielectric-constant dielectric layer.

[0178] The lower gate electrode 134L includes one or more gate electrode layers disposed above the gate dielectric 132 and around the lower semiconductor nanostructure 66L. The lower gate electrode 134L is disposed in the lower portion of a recess between the gate spacers 90 and in an opening between the lower semiconductor nanostructure 66L. The lower gate electrode 134L can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the lower gate electrode 134L may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0179] The lower gate electrode 134L is formed of a material suitable for a device type of lower nanostructure transistor. For example, the lower gate electrode 134L may include one or more work function adjustment layers formed of a work function adjustment metal suitable for a device type of lower nanostructure transistor. In some embodiments, the lower gate electrode 134L includes an n-type work function adjustment layer, which may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, or combinations thereof. In some embodiments, the lower gate electrode 134L includes a p-type work function adjustment layer, which may be formed of a p-type work function adjustment metal, such as titanium nitride, tantalum nitride, or combinations thereof. Additionally or alternatively, the lower gate electrode 134L may include a dipole-inducing element suitable for a device type of lower nanostructure transistor. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

[0180] The upper gate electrode 134U includes one or more gate electrode layers disposed above the gate dielectric 132 and around the upper semiconductor nanostructure 66U. The upper gate electrode 134U is disposed in the upper portion of a recess between the gate spacers 90 and in an opening between the upper semiconductor nanostructure 66U. The upper gate electrode 134U can be formed of a metallic material, such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, or multilayers thereof. Although a single-layer gate electrode is shown, the upper gate electrode 134U may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and filler materials.

[0181] The upper gate electrode 134U is formed of a material suitable for the device type of an upper nanostructure transistor. For example, the upper gate electrode 134U may include one or more work function adjustment layers formed of a work function adjustment metal suitable for the device type of an upper nanostructure transistor. In some embodiments, the upper gate electrode 134U includes an n-type work function adjustment layer, which may be formed of an n-type work function adjustment metal, such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, or combinations thereof. In some embodiments, the upper gate electrode 134U includes a p-type work function adjustment layer, which may be formed of a p-type work function adjustment metal, such as titanium nitride, tantalum nitride, or combinations thereof. The work function adjustment metal of the upper gate electrode 134U may be different from or the same as the work function adjustment metal of the lower gate electrode 134L. Additionally or alternatively, the upper gate electrode 134U may include an induced dipole element suitable for the device type of an upper nanostructure transistor. Acceptable induced dipole elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof. The induced dipole element of the upper gate electrode 134U may be different from or the same as the induced dipole element of the lower gate electrode 134L.

[0182] In some embodiments, an isolation layer (not shown separately) is formed between the lower gate electrode 134L and the upper gate electrode 134U. The isolation layer serves as an isolation feature between the lower gate electrode 134L and the upper gate electrode 134U. The isolation layer may be formed of a dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, combinations thereof, etc., which can be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), etc. Other dielectric materials formed by any acceptable process may also be used. In embodiments where the isolation layer is formed, the isolation layer and the isolation structure 100 together isolate the upper gate electrode 134U and the lower gate electrode 134L. Thus, the upper nanostructure transistor can be isolated from the lower nanostructure transistor by the combination of the isolation structure 100 and the isolation layer. In some embodiments where the isolation layer is omitted, the upper nanostructure transistor may be coupled to the lower nanostructure transistor. When the isolation layer is omitted, the lower gate electrode 134L may be physically and electrically coupled to the upper gate electrode 134U.

[0183] As an example of forming a gate structure, one or more gate dielectric layers may be deposited in the recesses between the gate spacers 90 and the openings between the semiconductor nanostructures 66. The gate dielectric layers may also be deposited above the second interlayer dielectric 124 and the top surface of the gate spacers 90. Subsequently, one or more lower gate electrode layers may be deposited above the gate dielectric layers and in the retained portions of the recesses between the gate spacers 90 and the openings between the semiconductor nanostructures 66. The lower gate electrode layers are then recessed. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be performed to recess the lower gate electrode layers. The etching may be isotropic, such as an etch-back process, removing the lower gate electrode layers from the upper portion of the recesses between the gate spacers 90, such that the lower gate electrode layers remain in the openings between the lower semiconductor nanostructures 66L. In embodiments forming an isolation layer, an isolation material is conformally formed on the lower gate electrode layer and then recessed. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be performed to recess the isolation material. Subsequently, one or more upper gate electrode layers may be deposited over an insulating material (if present) or a lower gate electrode layer, and in the retained portions of the recesses between the gate spacers 90 and the openings between the upper semiconductor nanostructures 66U. A removal process is performed to remove excess portions of the upper gate electrode layers located above the top surfaces of the gate spacers 90 and the interlayer dielectric 124, such that the upper gate electrode layers remain in the openings between the upper semiconductor nanostructures 66U. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., may be used. After the removal process, the gate dielectric layer has portions retained in the recesses between the gate spacers 90 and in the openings between the semiconductor nanostructures 66 (thus forming the gate dielectric 132). After the removal process, the lower gate electrode layer has portions retained in the lower portion of the recesses between the gate spacers 90 and in the openings between the lower semiconductor nanostructures 66L (thus forming the lower gate electrode 134L). After the removal process, the upper gate electrode layer has a portion remaining in the upper recess between the gate spacers 90 and in the opening between the upper semiconductor nanostructures 66U (thus forming the upper gate electrode 134U). When a planarization process is used, the top surfaces of the gate spacers 90, the second interlayer dielectric 124, the gate dielectric 132, and the upper gate electrode 134U are coplanar (within process variations).

[0184] exist Figure 11In this configuration, a third interlayer dielectric 128 is deposited over the gate spacer 90, the second contact etch stop layer 122, the second interlayer dielectric 124, and the upper gate electrode 134U. In some embodiments, the third interlayer dielectric 128 is a flow film formed by a flow-type CVD method and subsequently cured. In some embodiments, the third interlayer dielectric 128 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method (such as CVD, PECVD, etc.).

[0185] In some embodiments, an etch stop layer (ESL) 126 is formed between the third interlayer dielectric 128 and the gate spacer 90, the second contact etch stop layer 122, the second interlayer dielectric 124, and the upper gate electrode 134U. The etch stop layer 126 may include a dielectric material having high etch selectivity to the dielectric material of the third interlayer dielectric 128, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0186] exist Figure 12 An opening 136 is formed, extending through the third interlayer dielectric 128, the etch stop layer 126, the second interlayer dielectric 124, and the second contact etch stop layer 122 to expose the top surface of the epitaxial source / drain region 108U. For example, the opening 136 includes an opening 136A in the first region 95, an opening 136B in the second region 97, and an opening 136C in the third region 99. The opening 136 can be formed using acceptable photolithography and etching techniques. In some embodiments, a protective layer 137 is formed in the opening 136, for example above the top surface of the third interlayer dielectric 128 and the epitaxial source / drain region 108U, and above the sidewalls of the third interlayer dielectric 128, the etch stop layer 126, and the gate spacer 90. The protective layer 137 can be conformally formed using a deposition process, such as CVD, ALD, etc. The protective layer 137 can include a dielectric material with high etch selectivity to the material of the subsequently formed sacrificial layer 138 (described below). For example, the protective layer 137 may include, for example, silicon nitride, silicon oxynitride, etc. The protective layer 137 can then be patterned using appropriate photolithography and etching techniques to remove portions of the protective layer 137 above the top surface of the third interlayer dielectric 128 and above the sidewalls of the third interlayer dielectric 128, the etch stop layer 126, and a portion of the gate spacer 90. The remaining portion of the protective layer 137 is disposed above the top surface of the upper epitaxial source / drain region 108U.

[0187] exist Figure 13In this structure, a sacrificial layer 138 is formed in the opening 136, for example, above the top surface of the interlayer dielectric 128 and the protective layer 137, and above the sidewalls of the interlayer dielectric 128, the etch stop layer 126, and the gate spacer 90. The sacrificial layer 138 can be conformally formed using deposition processes such as CVD, ALD, etc. The sacrificial layer 138 may comprise, for example, undoped silicon, silicon oxide, etc. The sacrificial layer 138 may have a thickness T1 in the range of 2 nm to 3 nm.

[0188] exist Figure 14 In this process, a sacrificial layer 138 is patterned to remove a portion of the sacrificial layer 138 above the top surface of the third interlayer dielectric 128, as well as portions of the sacrificial layer 138 in openings 136B and 136C in the second region 97 and the third region 99, respectively. Furthermore, portions of the sacrificial layer 138 are removed from the bottom surface of opening 136A and above the upper sidewall of opening 136A in the first region 95. The remaining portions of the sacrificial layer 138 form sacrificial spacers 139, disposed above the sidewalls of opening 136A, for example, above the sidewalls of the third interlayer dielectric 128, etch stop layer 126, and gate spacer 90 in opening 136A.

[0189] To pattern the sacrificial layer 138, a suitable masking layer (e.g., photoresist, bottom anti-reflective coating (BARC) layer, etc.) can be formed to partially fill the opening 136A in the first region 95 of the semiconductor device 120 to mask the opening 136A. Simultaneously, a first etching process is performed to remove portions of the sacrificial layer 138 in the openings 136B and 136C in the second region 97 and third region 99, respectively. Furthermore, during the first etching process, a portion of the sacrificial layer 138 above the upper sidewall of the opening 136A (e.g., above the masking layer in the opening 136A) and a portion of the sacrificial layer 138 above the top surface of the third interlayer dielectric 128 are removed. The first etching process can be, for example, a dry etching process performed using chlorine or the like as an etchant.

[0190] After performing the first etching process, the masking layer in the opening 136A in the first region 95 can be removed using a suitable etching process. A second etching process can then be performed to remove the horizontal portion of the sacrificial layer 138 above the bottom surface of the opening 136A, exposing the top surface of the protective layer 137 in the opening 136A. The second etching process can be, for example, a dry etching process performed using chlorine or the like as an etchant. After performing the first and second etching processes, the remaining portion of the sacrificial layer 138 above the sidewall of the opening 136A forms a sacrificial spacer 139.

[0191] exist Figure 15In this configuration, spacer 140 is formed above sacrificial spacer 139 in opening 136A of the first region 95. Spacer 140 is also formed in openings 136B and 136C of the second region 97 and third region 99, respectively, for example, above the sidewalls of the third interlayer dielectric 128, etch stop layer 126, and gate spacer 90. Spacer 140 can also be formed by using a suitable deposition process, such as CVD, ALD, etc., to form the spacer layer, followed by a patterning of the spacer layer using a suitable etching process, such as isotropic etching (e.g., wet etching) or anisotropic etching (e.g., dry etching). The spacer layer may include a dielectric material, such as silicon nitride. The spacer layer may be formed above the top surface of the third interlayer dielectric 128 and the guard layer 137, and above the sidewalls of the third interlayer dielectric 128, etch stop layer 126, and gate spacer 90. Following the etching process, spacer 140 may remain above sacrificial spacer 139 in opening 136A of the first region 95, and above the sidewalls in openings 136B and 136C of the second and third regions 97, respectively. After the spacer 140 is formed, opening 136 may extend through protective layer 137 to expose the top surface of epitaxial source / drain region 108U. Opening 136 may be extended through protective layer 137 using, for example, acceptable photolithography and etching techniques. In one embodiment, after opening 136A extends through protective layer 137, a portion of protective layer 137 remains below spacer 140 and sacrificial spacer 139 in opening 136A.

[0192] exist Figure 16 and Figure 17 In this configuration, a metal contact 144 is formed in the opening 136. For example, the metal contact 144 may be formed to extend through the third interlayer dielectric 128, the etch stop layer 126, and between adjacent upper gate electrodes 134U to electrically couple the epitaxial source / drain regions 108U. Figure 16 In the opening 136, a gasket (not shown separately), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material 143 are formed in the opening 136 (e.g., opening 136A, opening 136B, and opening 136C). The gasket may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material 143 may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc.

[0193] exist Figure 17In this process, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess material from the top surface of the third interlayer dielectric 128, including the pads and conductive material 143. In one embodiment, the planarization process may also remove portions of the spacers 140, sacrificial spacers 139, and the third interlayer dielectric 128, such that after the planarization process, the top surfaces of the spacers 140, sacrificial spacers 139, and the third interlayer dielectric 128, the pads, and the metal contacts 144 are substantially coplanar (within process variations).

[0194] Optionally, a metal-semiconductor alloy region 142 is formed at the interface between the epitaxial source / drain region 108U and the metal contact 144. The metal-semiconductor alloy region 142 can be a silicide region formed from metal silicides (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), or a silicon germanide region formed from both metal silicides and metal germanides. The metal-semiconductor alloy region 142 can be formed prior to the material of the metal contact 144 by depositing metal in the opening 136 followed by a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the epitaxial source / drain region 108U (e.g., silicon, silicon germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other noble metals, other refractory metals, rare earth metals, or alloys thereof. Metals can be deposited using deposition processes such as ALD, CVD, and PVD. Following the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the opening 136, for example, from the surface of the metal-semiconductor alloy region 142. The material of the metal contact 144 can then be formed over the metal-semiconductor alloy region 142.

[0195] exist Figure 18AIn this process, the sacrificial spacer 139 in the first region 95 is removed to form a recess between the gate spacer 90 and the spacer 140. The recess is adjacent to the spacer 140 and is located above the protective layer 137 and the epitaxial source / drain region 108U in the first region 95. The recess may also be between the spacer 140 and the third interlayer dielectric 128 in the first region 95, and between the spacer 140 and the etch stop layer 126 in the first region 95. In one embodiment, the recess surrounds the spacer 140 and the metal contact 144 in the first region 95. The sacrificial spacer 139 can be removed by performing any acceptable etching process, such as an etching process selectively etching the material of the sacrificial spacer 139 (e.g., selectively etching the material of the sacrificial spacer 139 at a rate faster than the materials of the spacer 140 and the third interlayer dielectric 128). In one embodiment, performing the etching process may include performing a dry or wet etching process using chlorine, hydrogen fluoride, or the like as an etchant. The width W1 of each recess can be substantially the same as the thickness T1 of the sacrificial spacer 139. For example, the width W1 can be in the range of 2 nm to 3 nm. In this embodiment, the entire sacrificial spacer 139 is removed such that after the etching process, no residual portion of the sacrificial spacer 139 remains on the protective layer 137 in the first region 95. Therefore, the protective layer 137 in the first region 95 is exposed in the recess. In another embodiment, only a portion of the sacrificial spacer 139 is removed such that after the etching process, some residual portion of the sacrificial spacer 139 remains above the protective layer 137 in the first region 95. It is worth noting that no recesses are formed in the second region 97 and the third region 99. In other embodiments, the etching process that removes the sacrificial spacer 139 may also partially etch a portion of the protective layer 137 and the upper epitaxial source / drain region 108U below the sacrificial spacer 139. Therefore, the recess can extend through the protective layer 137 and partially through the upper epitaxial source / drain region 108U to form a "tooth-like" feature at the edge of the upper epitaxial source / drain region 108U, such as Figure 18B As shown in the image.

[0196] After the sacrificial spacer 139 is removed, in some embodiments, an etch stop layer (ESL) 151 is formed over the inter-third layer dielectric 128, the spacer 140, and the metal contact 144. The etch stop layer 151 may comprise a dielectric material having high etch selectivity to the dielectric material of the inter-third layer dielectric 128, such as silicon nitride, silicon oxide, silicon oxynitride, etc.

[0197] After the etch stop layer 151 is formed, an implantation process can be performed to introduce doping into a portion of the third interlayer dielectric 128. The implantation process can be used to introduce an implant material (or dopant) such as germanium into a portion of the third interlayer dielectric 128 beneath the etch stop layer 151 to promote expansion of the material in the third interlayer dielectric 128. This expansion of the material in the third interlayer dielectric 128 can cause the third interlayer dielectric 128 to seal the top of the recess between the spacer 140 in the first region 95 and the third interlayer dielectric 128, as well as the top of the recess between the spacer 140 in the first region 95 and the etch stop layer 126. Thus, after the implantation process, an air gap 146 is formed around a portion of the spacer 140 and the metal contact 144 in the first region 95. In one embodiment, the top surface of the protective layer 137 or the epitaxial source / drain region 108U in the first region 95 is exposed to the air gap 146.

[0198] exist Figure 19A and Figure 19B In this configuration, a dielectric layer 150 is disposed above an etch stop layer 151. The dielectric layer 150 can be formed of any suitable dielectric material, such as silicon nitride, silicon oxide, etc., and can be formed by deposition processes such as CVD, ALD, etc. A contact via 152 is then formed to extend through the dielectric layer 150 and the etch stop layer 151 to electrically couple the metal contact 144 in the first region 95. As an example of forming the contact via 152, an opening for the contact via 152 is formed through the dielectric layer 150 and the etch stop layer 151. The opening can be formed using acceptable lithography and etching techniques. Pads (not shown separately), such as diffusion barrier layers, adhesive layers, etc., and conductive material are formed in the opening. Pads can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloys, silver, gold, aluminum, nickel, etc. A planarization process, such as CMP, can be performed to remove excess material from the top surface of the dielectric layer 150. The retained padding and conductive material form a contact through-hole 152 in the opening. The contact through-hole 152 can be used to electrically connect the metal contact 144 in the first region 95 to the subsequently formed bit line 149.

[0199] Further reference Figure 19A and Figure 19BA dielectric layer 148 may be deposited over the dielectric layer 150 and the contact via 152. The dielectric layer 148 can be formed of any suitable dielectric material, such as silicon nitride, silicon oxide, etc., and can be formed by deposition processes such as CVD, ALD, etc. After forming the dielectric layer 148, bit lines 149 may be formed in the dielectric layer 148. The bit lines 149 may include conductive strips and can be electrically connected to the metal contacts 144 in the first region 95 through the contact via 152. To form the bit lines 149, trenches may be formed in the dielectric layer 148. The trenches may be formed using acceptable photolithography and etching techniques. Subsequently, the trenches may be filled with conductive materials using CVD, physical vapor deposition (PVD), electro-chemical plating (ECP), electroless plating, etc. The conductive material may include materials such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, and multilayers thereof. Any excess conductive material can be removed by a planarization process, such as chemical mechanical polishing (CMP). The bit line 149 may extend along a length direction perpendicular to the length direction of the gate electrode 134. In one embodiment, a sub-region of the first region 95 disposed within the NMOS portion of the static random access memory cell may also be referred to as the bit line region of the semiconductor device 120. In one embodiment, a sub-region of the second region 97 disposed within the NMOS portion of the static random access memory cell may also be referred to as the node region of the semiconductor device 120. In one embodiment, the metal contact 144 in a sub-region of the third region 99 disposed within the NMOS portion of the static random access memory cell may be a voltage source supply (VSS) contact (e.g., electrically connected to the source of the NMOS portion of a complementary field-effect transistor).

[0200] An advantage can be achieved by removing the sacrificial spacer 139 in the first region 95 to form a recess in the adjacent spacer 140, the recess being located above the protective layer 137 and the epitaxial source / drain region 108U in the first region 95. The recess can be formed around the spacer 140 and the metal contact 144 in the first region 95, wherein the metal contact 144 in the first region 95 is a bit line contact and is electrically connected to the subsequently formed bit line 149. After removing the sacrificial spacer 139, an etch stop layer (ESL) 151 is formed over the third interlayer dielectric 128, the spacer 140, and the metal contact 144. After forming the etch stop layer 151, an implantation process is performed to introduce a dopant (e.g., germanium) into a portion of the third interlayer dielectric 128 to promote the expansion of the material in the third interlayer dielectric 128. The expansion of the material of the third interlayer dielectric 128 can cause the third interlayer dielectric 128 to seal the top of the recess between the spacer 140 in the first region 95 and the third interlayer dielectric 128, as well as the top of the recess between the spacer 140 in the first region 95 and the etch stop layer 126. Thus, after the implantation process is performed, an air gap 146 is formed around a portion of the spacer 140 and the metal contact 144 in the first region 95. The air gap 146 may have a width W1 in the range of 2 nm to 3 nm. No air gap is formed around a portion of the spacer 140 and the metal contact 144 in the second region 97 or the third region 99.

[0201] These advantages include the air gap 146 having a width W1 in the range of 2nm to 3nm, allowing for a reduction in capacitance associated with bit line contacts (e.g., metal contacts 144 in the first region 95). Therefore, the combined capacitance of bit line 149 and bit line contacts (e.g., metal contacts 144 in the first region 95) can be reduced, and less charge is required to change the voltage of bit line 149 during read / write operations. This makes read / write operations in static random access memory (SRAM) cells faster. Therefore, the speed of SRAM cell operations can be improved. Furthermore, since no air gap is formed around the partial spacers 140 and partial metal contacts 144 in each of the second and third regions 97 and 99, each metal contact 144 in the second and third regions 99 can be formed with a larger size (e.g., a larger width) because there is no need to accommodate the space occupied by the air gap. The increased size of the metal contacts 144 in each second zone 97 and each third zone 99 leads to a decrease in resistance through these metal contacts 144, which in turn improves the performance of static random access memory cells.

[0202] exist Figure 20Then, a planarization process can be performed on the back side of the semiconductor device 120 (e.g., on substrate 50). In some embodiments, the planarization process may include a combination of, for example, CMP and / or etch-back processes. The planarization and / or etching processes can remove substrate 50 and fins 62, thereby exposing isolation region 70. Subsequently, one or more etching processes are performed to remove isolation region 70. Etch stop layer 154 may be deposited over the back side of semiconductor device 120, for example over gate dielectric 132, lower gate electrode 134L, first contact etch stop layer 112, first interlayer dielectric 114, and lower epitaxial source / drain region 108L. Etch stop layer 154 may include a dielectric material with high etch selectivity to the dielectric material of subsequently formed interlayer dielectric 156, such as silicon nitride, silicon oxide, silicon oxynitride, etc. After the etch stop layer 154 is formed, interlayer dielectric 156 is deposited over the back side of semiconductor device 120, for example over etch stop layer 154. The interlayer dielectric 156 is a flow film formed by a flow-type CVD method and subsequently cured. In some embodiments, the interlayer dielectric 156 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc. A removal process is then performed to make the bottom surface of the interlayer dielectric 156 and the etch stop layer 154 flush with the bottom surface of the first contact etch stop layer 112 and the lower epitaxial source / drain region 108L. In some embodiments, planarization processes, such as chemical mechanical polishing (CMP), etch-back processes, combinations thereof, etc., can be used.

[0203] exist Figure 21 In this configuration, interlayer dielectric 158 may be deposited over the back side of semiconductor device 120, for example, over etch stop layer 154, interlayer dielectric 156, first contact etch stop layer 112, first interlayer dielectric 114, and lower epitaxial source / drain region 108L. Interlayer dielectric 158 is a flow film formed by a flow-type CVD method and subsequently cured. In some embodiments, interlayer dielectric 158 is formed of a dielectric material such as PSG, BSG, BPSG, USG, etc., and can be deposited by any suitable method, such as CVD, PECVD, etc. After forming interlayer dielectric 158, an opening 159 is formed extending through interlayer dielectric 158, interlayer dielectric 156, and etch stop layer 154 to expose the bottom surfaces of lower epitaxial source / drain region 108L and first interlayer dielectric 114. For example, opening 159 includes opening 159A in the first region 95 and openings 159B and 159C in the second region 97 and the third region 99. Opening 159A exposes the bottom surface of the first contact etch stop layer 112 and the first interlayer dielectric 114, while openings 159B and 159C expose the bottom surface of the lower epitaxial source / drain region 108L. Opening 159 can be formed using acceptable photolithography and etching techniques.

[0204] exist Figure 22 In this process, sacrificial spacers 160 may be formed above the sidewalls of openings 159 (e.g., openings 159A, 159B, and 159C), such as above the sidewalls of etch stop layer 154 and above a portion of the sidewalls of interlayer dielectric 158. Sacrificial spacers 160 may be used as in... Figure 13 and Figure 14 The spacer 162 is formed using a similar process and similar materials as previously described for forming the sacrificial spacer 139. After the sacrificial spacer 160 is formed, the spacer 162 is formed in the openings 159 in the first region 95, the second region 97, and the third region 99. The spacer 162 can be formed using methods as described above. Figure 15 The spacer 140 is formed using a similar process and similar materials as previously described.

[0205] exist Figure 23 and Figure 24 In this configuration, a metal contact 166 is formed in the opening 159. For example, the metal contact 166 may be formed to extend through the interlayer dielectric 156 and the etch stop layer 154 to electrically couple the lower epitaxial source / drain regions 108L in the second region 97 and the third region 99. Figure 23 In the design, a gasket (not shown separately), such as a diffusion barrier layer, an adhesive layer, etc., and a conductive material 165 are formed in the opening 159 (e.g., opening 159A, opening 159B, and opening 159C). The gasket may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material 165 may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc.

[0206] exist Figure 24 In this process, a planarization process, such as chemical mechanical polishing (CMP), is performed to remove excess material from the top surfaces of the interlayer dielectric 156 and the etch stop layer 154, including the pads and conductive material 165. The retained conductive material 165 and pads in the opening 159 form the metal contact 166. In one embodiment, the planarization process may also remove portions of the interlayer dielectric 158, sacrificial spacer 160, and spacer 162, such that after the planarization process, the top surfaces of spacer 162, sacrificial spacer 160, interlayer dielectric 156, etch stop layer 154, and metal contact 166 are substantially coplanar (within process variations). Optionally, a metal-semiconductor alloy region 164 is formed at the interface between the lower epitaxial source / drain region 108L and the metal contact 166. The metal-semiconductor alloy region 164 can be used as shown in... Figure 17 The same process and similar materials used to form the metal-semiconductor alloy region 142 as previously described are employed to form it.

[0207] Further reference Figure 24The sacrificial spacer 160 in the first region 95, the second region 97, and the third region 99 is removed to form a recess between the spacer 162 and the etch stop layer 154. The sacrificial spacer 160 can be used as shown in... Figure 18A A similar process and etchant as previously described are used to remove the sacrificial spacer 139. The recess is located adjacent to the spacer 162 and above the lower epitaxial source / drain region 108L in the second region 97 and the third region 99. The recess may also be located above the first contact etch stop layer 112 and / or the first interlayer dielectric 114 in the first region 95. In one embodiment, the recess surrounds the spacer 162 and the metal contact 166 in each of the first region 95, the second region 97, and the third region 99.

[0208] Figure 25A and Figures 25C to 25D The air gap 168 is shown forming around the spacer 162 and the metal contact 166 in each of the first zone 95, the second zone 97 and the third zone 99. Figure 25A Show along Figure 25C The cross-sectional view of line D-D' shown, and / or along Figure 25D The cross-sectional view of line E-E' shown. Figure 25C Shown in Figure 25A The top view of the semiconductor device 120 shown. Figure 25D Shown in Figure 25A The semiconductor device 120 shown is shown in the bottom view. Figure 25B A top view of a semiconductor device 120 having a plurality of gate spacers and a plurality of gate electrode layers is shown according to other embodiments. Figure 25A In this process, dielectric layer 170 can be deposited over the back side of semiconductor device 120, for example, over spacers 162, interlayer dielectric 156, etch stop layer 154, and metal contacts 166. The dielectric layer 170 is formed such that the recesses between spacers 162 and etch stop layer 154 in the first region 95, second region 97, and third region 99 are sealed. Thus, air gaps 168 are formed surrounding spacers 162 and metal contacts 166 in each of the first region 95, second region 97, and third region 99. Dielectric layer 170 can be formed from any suitable dielectric material, such as silicon nitride, silicon oxide, etc., and can be formed by deposition processes such as CVD, ALD, etc. In one embodiment, the width W2 of each air gap 168 is in the range of 2 nm to 3 nm. In one embodiment, the metal contact 144 in the second region 97 and the third region 99 may have a width W3, and the metal contact 166 in each of the first region 95, the second region 97 and the third region 99 may have a width W4, wherein the width W4 is less than the width W3.

[0209] After forming the dielectric layer 170, conductive lines 172 can be formed in the dielectric layer 170. The conductive lines 172 can be back-side power rails, etc., and may include conductive strips electrically connected to the metal contacts 166 in the second region 97. To form the conductive lines 172, trenches can be formed in the dielectric layer 170. The trenches can be formed using acceptable photolithography and etching techniques. The trenches can then be filled with a conductive material using CVD, physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, etc. The conductive material can include materials such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, and multilayers thereof. Any excess conductive material can be removed by a planarization process, such as chemical mechanical polishing (CMP).

[0210] After forming dielectric layer 170 and conductive lines 172, dielectric layer 174 may be deposited over the back side of semiconductor device 120, for example, over dielectric layer 170 and conductive lines 172. Dielectric layer 174 may be formed of any suitable dielectric material, such as silicon nitride, silicon oxide, etc., and may be formed by deposition processes such as CVD, ALD, etc. After forming dielectric layer 174, conductive lines 176 may be formed in dielectric layer 174. Conductive lines 176 may include conductive strips electrically connected to metal contacts 166 in second region 97. To form conductive lines 176, trenches may be formed in dielectric layer 174. Trenches may be formed using acceptable photolithography and etching techniques. Subsequently, the trenches may be filled with conductive materials using CVD, physical vapor deposition (PVD), electrochemical plating (ECP), electroless plating, etc. The conductive material may include materials such as Cu, Al, Ti, Ta, W, Pt, Ni, Cr, Ru, TiN, TaN, combinations thereof, and multilayers thereof. Any excess conductive material can be removed by a planarization process, such as chemical mechanical polishing (CMP). In one embodiment, a sub-region of the first region 95 disposed within the PMOS portion of the static random access memory cell may subsequently be referred to as a dummy region of the semiconductor device 120. In one embodiment, a sub-region of the second region 97 disposed within the PMOS portion of the static random access memory cell may subsequently be referred to as a node region of the semiconductor device 120. In one embodiment, the metal contact 166 in a sub-region of the third region 99 disposed within the PMOS portion of the static random access memory cell may be a voltage drain supply (VDD) contact (e.g., electrically connected to the source of the PMOS portion of a complementary field-effect transistor). Conductive lines 172 and 176 may be used to electrically couple the gate electrode 134 to the metal contact 166 of the node region of the PMOS portion of the static random access memory cell.

[0211] The advantage can be achieved by removing the sacrificial spacer 160 in the first region 95, the second region 97, and the third region 99 to form a recess between spacer 162 and etch stop layer 154. The recess is formed in the PMOS portion of the static random access memory cell and is disposed around spacer 162, specifically over the lower epitaxial source / drain region 108L in the second region 97 and the third region 99. Dielectric layer 170 can be deposited over spacer 162, interlayer dielectric 156, etch stop layer 154, and metal contact 166 to seal the recess and form air gaps 168 between spacer 162 and etch stop layer 154 in the first region 95, the second region 97, and the third region 99. Each air gap 168 may surround spacer 162 and metal contact 166 in each of the first region 95, the second region 97, and the third region 99. The metal contact 144 in the second zone 97 and the third zone 99 may have a width W3, and the metal contact 166 in each of the first zone 95, the second zone 97 and the third zone 99 may have a width W4, wherein the width W4 is less than the width W3.

[0212] These advantages include the ability to achieve a better match between the device performance of n-type nanostructure transistors in the NMOS portion of a static random access memory (SRAM) and that of p-type nanostructure transistors in the PMOS portion of a SRAM, by forming an air gap 168 around the metal contacts 166 in the second region 97 and the third region 99 (e.g., VDD contacts in the PMOS portion of a SRAM cell). This is because p-type nanostructure transistors typically have better device performance than n-type nanostructure transistors when they have similar dimensions. The use of the air gap 168 around the metal contacts 166 in the second region 97 and the third region 99 allows the width W4 of the metal contacts 166 in the second region 97 and the third region 99 to be adjusted to be smaller than the width W3 of the metal contacts 144 in the second region 97 and the third region 99. This modification to the geometry of the metal contact 166 affects the overall electrical characteristics of the p-type nanostructure transistors in the PMOS portion of the static random access memory (SRAM) cell and allows for adjustment of the device performance of the p-type nanostructure transistors to match the device performance of the n-type nanostructure transistors in the NMOS portion of the SRAM cell. Therefore, SRAM cell operation can be optimized.

[0213] Figure 25BA top view of a semiconductor device 120 having multiple gate spacers and multiple gate electrode layers according to other embodiments is shown. For example, gate spacers 90A and 90B may be disposed above the sidewalls of gate structures 134U / 132. Gate spacer 90A may include a first material different from the material of gate spacer 90B. In one embodiment, the upper gate electrode 134U of gate structure 134U / 132 may include more than one gate electrode layer (e.g., a first gate electrode layer 134U1, a second gate electrode layer 134U2, and a third gate electrode layer 134U3) disposed above gate dielectric 132. Figure 25B The diagram shows the PMOS portion of a static random access memory cell, where an air gap 146 surrounds the metal contacts 144 and spacers 140 in the first region 95. The metal contacts 144 in the first region 95 may also be referred to as bit line contacts. It can be seen that there is no air gap surrounding the spacers 140 and metal contacts 144 in the second region 97 (e.g., the node region). It can also be seen that there is no air gap surrounding the spacers 140 and metal contacts 144 in the third region 99. Figure 25B An isolation structure 180 is also shown, which can be used to electrically insulate the portions of the gate structures 132 / 134U from each other. Each isolation structure 180 can be formed using suitable photolithography and etching techniques to create an opening between the portions of the gate structures 132 / 134U, which is then filled with a dielectric material (e.g., silicon oxide).

[0214] Figure 25C Show Figure 25A The top view of the semiconductor device 120 shown. Figure 25CComplementary field-effect transistors (Field-Effect Transistors) are shown for the NMOS portion of a Static Random Access Memory (SRAM) cell. In various embodiments, these complementary Field-Effect Transistors may include, for example, pull-down (PD) transistors and pass-gate (PG) transistors, with the pull-down transistor disposed between second region 97 and third region 99, and the pass-gate transistor disposed between first region 95 and second region 97. Metal contacts 144 electrically connect the epitaxial source / drain regions 108U in first region 95, second region 97, and third region 99. For example, the metal contact 144 in first region 95 may be referred to as a bit line contact and may be used to electrically connect bit lines 149 (e.g., through contact vias 152) to the drain of the pass-gate (PG) transistor to allow data to be read from and written from the SRAM cell. The metal contact 144 in second region 97 may be electrically connected to the storage node of the SRAM cell. Metal contact 144 (also referred to as voltage source supply (VSS) contact) in zone 99 is electrically connected to the pull-down transistor (PD) of the static random access memory cell. This connection allows the pull-down (PD) transistor to effectively pull the memory node to ground during write operations or when maintaining a logic "0" state. Figure 25C The isolation structure 180 and the electrically insulated gate structure 134U / 132 are also shown. The metal contact 144 in the third region 99 is electrically connected to other metal layers of the semiconductor device 120 through the contact via 153.

[0215] Figure 25D Shown in Figure 25A The semiconductor device 120 shown is shown in the bottom view. Figure 25D A complementary field-effect transistor (FET) is shown for the PMOS portion of a static random-access memory (SRAM) cell. In various embodiments, these FETs may include, for example, pull-down (PD) transistors disposed between a second region 97 and a third region 99. A metal contact 166 is electrically connected to the epitaxial source / drain regions 108L in the second region 97 and the third region 99. For example, the metal contact 166 in the first region 95 may be referred to as a dummy contact. The metal contact 166 in the second region 97 may be electrically connected to the storage node of the SRAM cell. The metal contact 166 in the third region 99 (also referred to as a voltage drain supply (VDD) contact) may be electrically connected to the source region of the pull-down (PD) transistor of the SRAM cell. This connection provides the positive supply voltage required for the pull-up (PU) transistor to pull the storage node to a high state when needed. Figure 25D It also shows the 180 electrically insulating portion of the isolation structure and the 134U / 132 gate structure.

[0216] Figure 25DConductive lines 172 and 176 are also shown, which can be used to electrically couple the gate electrode 134 to the node region (e.g., disposed in the second region 97) of the PMOS portion of the static random access memory cell via contact via 167. In one embodiment, conductive lines 172 and 176 can also facilitate coupling between the lower gate electrode 134L and the upper gate electrode 134U, and provide a connection between the PMOS and NMOS of the static random access memory cell.

[0217] Figure 26 Semiconductor device 120 is illustrated according to some other embodiments. Unless otherwise stated, the same reference numerals in this embodiment represent those formed by the same process. Figures 1 to 25D The same components are used in the embodiments shown. Therefore, the process steps and materials used will not be repeated herein.

[0218] Figure 26 The embodiments shown can be similar to Figure 25A The embodiments shown, except in Figure 26 In the illustrated embodiment, no air gap 168 is formed to surround the metal contacts 166 in each of the first regions 95, second regions 97, and third regions 99. Thus, the absence of an air gap 168 results in physical contact between the sidewalls of the metal contacts 166 and the material of surrounding components (e.g., etch stop layer 178, etc.). The etch stop layer 178 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, etc. However, in… Figure 26 In the illustrated embodiment, there is an air gap 146 surrounding a portion of the spacer 140 and the metal contact 144 in the first region 95 (previously in...). Figures 1 to 25D (As described in the text).

[0219] The embodiments disclosed herein have several advantageous features. The embodiments include forming air gaps around bit line contacts (e.g., electrically connected bit lines) in the bit line region of the NMOS portion of a static random-access memory (SRAM) cell. The NMOS portion of the SRAM cell may be a region of the SRAM cell that includes an NMOS portion of a complementary field-effect transistor (CFPT). The PMOS portion of the SRAM cell may be a region of the SRAM cell that includes a PMOS portion of a CFPT. No air gap is formed around a first node contact (e.g., electrically connected to an internal storage node) in the node region of the NMOS portion of the SRAM cell, and no air gap is formed around a voltage source supply (VSS) contact (e.g., electrically connected to the source of the NMOS portion of the CFPT) in the first region of the NMOS portion of the SRAM cell. The air gaps can be formed by first depositing a sacrificial silicon layer. The sacrificial silicon layer is then selectively removed to leave space where the sacrificial silicon layer was previously deposited. Furthermore, the air gap can be formed to surround a second node contact (e.g., electrically connecting an internal storage node) in the node region of the PMOS portion of the static random memory cell, and the air gap can be formed to surround a voltage drain supply (VDD) contact (e.g., electrically connecting the source of the PMOS portion of a complementary field-effect transistor) in the first region of the PMOS portion of the static random memory cell.

[0220] One or more embodiments disclosed herein allow for a reduction in capacitance associated with bit line contacts. Therefore, the total capacitance of the bit lines in a static random access memory (SRAM) cell can be reduced, and less charge is required to change the bit line voltage during read / write operations. This makes read / write operations in the SRAM cell faster. Consequently, the operating speed of the SRAM cell can be improved. Furthermore, since no air gap is formed around each first node contact and voltage source supply (VSS) contact in the NMOS portion of the SRAM cell, the VSS contacts and first node contacts can be formed with larger dimensions (e.g., larger widths) because there is no need to accommodate the space occupied by air gaps. The increased size of the first node contacts and VSS contacts results in a decrease in resistance through these contacts, which in turn improves the performance of the SRAM cell. Furthermore, by selectively adding air gaps around each second node contact and VDD contact in the PMOS portion of the static random access memory cell, a better match can be achieved between the device performance of the n-type nanostructure transistor in the NMOS portion of the complementary field-effect transistor and the device performance of the p-type nanostructure transistor in the PMOS portion of the complementary field-effect transistor.

[0221] According to one embodiment, a semiconductor device includes a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure and between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. A gate spacer is disposed above a sidewall of the first portion of the second gate stack. A first metal contact extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein an air gap is disposed between the sidewall of the first metal contact and the sidewall of the first gate spacer. In one embodiment, the semiconductor device is a memory device, and the semiconductor device further includes a bit line above and electrically connected to the first metal contact. In one embodiment, the semiconductor device further includes a first spacer layer above the sidewall of the first metal contact, wherein the first spacer layer surrounds the first metal contact. In one embodiment, an air gap is disposed between the first spacer layer and the sidewall of the first gate spacer. In one embodiment, the air gap has a width in the range of 2 nm to 3 nm. In one embodiment, the air gap surrounds the first metal contact and the first spacer layer. In one embodiment, the semiconductor device further includes a second metal contact extending between a third gate spacer and a fourth gate spacer in the gate spacers to physically contact a second source / drain region in the second source / drain region, wherein no air gap is provided between the sidewall of the second metal contact and the sidewall of the third gate spacer. A second spacer layer is placed above the sidewall of the second metal contact, surrounding the second metal contact, and physically contacting the third and fourth gate spacers. In one embodiment, the second metal contact is electrically connected to a storage node.

[0222] According to one embodiment, a semiconductor device includes a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. Gate spacers are disposed above the sidewalls of the first portion of the second gate stack. A first interlayer dielectric (ILD) is disposed above the back side of the first gate stack. A first metal contact extends through the first portion of the second gate stack and extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein a first air gap is disposed between the sidewalls of the first metal contact and the sidewalls of the first gate spacer. A first back-side metal contact extends through the first interlayer dielectric to physically contact the first source / drain region in the first source / drain region, wherein a second air gap is disposed between the sidewalls of the first back-side metal contact and the sidewalls of the first interlayer dielectric. In one embodiment, the semiconductor device further includes a second metal contact extending through a first portion of the second gate stack and extending between a third gate spacer and a fourth gate spacer in the gate spacers to physically contact a second source / drain region in a second source / drain region. A first spacer layer is above the sidewall of the second metal contact, wherein the first spacer layer surrounds the second metal contact, and wherein the first spacer layer physically contacts the third and fourth gate spacers. In one embodiment, the second metal contact overlaps with a first back-side metal contact. In one embodiment, the width of the first back-side metal contact is smaller than the width of the second metal contact. In one embodiment, the width of the first air gap is in the range of 2 nm to 3 nm. In one embodiment, the first air gap surrounds the first metal contact. In one embodiment, the semiconductor device further includes a bit line above and electrically connected to the first metal contact.

[0223] According to one embodiment, a method of forming a semiconductor device includes forming a multilayer stack over a semiconductor substrate, the multilayer stack including alternating semiconductor nanostructures and dummy nanostructures. A lower source / drain region is formed, wherein a lower semiconductor nanostructure of the semiconductor nanostructure extends between the lower source / drain regions. An upper source / drain region is formed over the lower source / drain region, wherein an upper semiconductor nanostructure of the semiconductor nanostructure extends between the upper source / drain regions. A lower gate stack and an upper gate stack replace the dummy nanostructures, the lower gate stack surrounding the lower semiconductor nanostructure and the upper gate stack surrounding the upper semiconductor nanostructure, wherein a first portion of the upper gate stack is disposed over the upper semiconductor nanostructure, and gate spacers are disposed over the sidewalls of the first portion of the upper gate stack. A first metal contact is formed extending through the first portion of the upper gate stack and between a first gate spacer and a second gate spacer to physically contact the first upper source / drain region, wherein an air gap is disposed between the sidewalls of the first metal contact and the sidewalls of the first gate spacer. In one embodiment, the method further includes forming a bit line above and electrically connected to the first metal contact. In one embodiment, the method further includes forming a first spacer layer above a sidewall of the first metal contact, wherein the first spacer layer surrounds the first metal contact, wherein an air gap surrounds the first spacer layer and the first metal contact, wherein the air gap has a width in the range of 2 nm to 3 nm. In one embodiment, the method further includes forming a second metal contact extending through a first portion of the upper gate stack and extending between a third gate spacer and a fourth gate spacer in the gate spacers to physically contact a second upper source / drain region in the upper source / drain region. A second spacer layer is formed above a sidewall of the second metal contact, wherein the second spacer layer surrounds the second metal contact, and wherein the second spacer layer physically contacts the third and fourth gate spacers. In one embodiment, the method further includes forming a third metal contact extending through a first portion of the upper gate stack and between a fifth gate spacer and a sixth gate spacer in the gate spacers to physically contact a third upper source / drain region in the upper source / drain region. A third spacer layer is formed above the sidewall of the third metal contact, wherein the third spacer layer surrounds the third metal contact, and wherein the third spacer layer physically contacts the fifth and sixth gate spacers.

[0224] According to one embodiment, a semiconductor device includes a first nanostructure extending between first source / drain regions. A second nanostructure extends above the first nanostructure between second source / drain regions. A first gate stack surrounds the first nanostructure. A second gate stack is disposed above the first gate stack and around the second nanostructure, wherein a first portion of the second gate stack is disposed above the second nanostructure. A gate spacer is disposed above the sidewall of the first portion of the second gate stack. A first metal contact extends between the first gate spacer and the second gate spacer to physically contact the first source / drain region in the second source / drain region, wherein an air gap is disposed between the sidewall of the first metal contact and the sidewall of the first gate spacer. A first spacer layer is disposed above the sidewall of the first metal contact, surrounding the first metal contact, wherein an air gap is disposed between the first spacer layer and the sidewall of the first gate spacer.

[0225] The features of many embodiments outlined above will enable those skilled in the art to better understand the viewpoint of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or adapting other processes and structures to achieve the same purpose and / or attain the same benefits as the embodiments described herein. Those skilled in the art will also understand that such equivalent architectures do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: Multiple first nanostructures extend between multiple first source / drain regions; Multiple second nanostructures are situated above the multiple first nanostructures, and the multiple second nanostructures extend between multiple second source / drain regions; A first gate stack surrounds the plurality of first nanostructures; A second gate stack is disposed above the first gate stack and around the plurality of second nanostructures, wherein a first portion of the second gate stack is disposed above the plurality of second nanostructures; Multiple gate spacers are located above multiple sidewalls of the first portion of the second gate stack. as well as A first metal contact extends between a first gate spacer and a second gate spacer among the plurality of gate spacers to physically contact a first source / drain region among the plurality of second source / drain regions, wherein an air gap is disposed between a sidewall of the first metal contact and a sidewall of the first gate spacer.

2. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device is a memory device, and the semiconductor device further includes a bit line above the first metal contact and electrically connected to the first metal contact.

3. The semiconductor device as claimed in claim 1, characterized in that, The air gap has a width that is in the range of 2nm to 3nm.

4. The semiconductor device as claimed in claim 1, characterized in that, Further includes: A second metal contact extends between a third gate spacer and a fourth gate spacer among the plurality of gate spacers to physically contact a second source / drain region among the plurality of second source / drain regions, wherein no air gap is provided between a sidewall of the second metal contact and a sidewall of the third gate spacer. as well as A second spacer layer is disposed above a plurality of sidewalls of the second metal contact, wherein the second spacer layer surrounds the second metal contact and wherein the second spacer layer physically contacts the third gate spacer and the fourth gate spacer.

5. The semiconductor device as claimed in claim 4, characterized in that, The second metal contact is electrically connected to a storage node.

6. A semiconductor device, characterized in that, include: Multiple first nanostructures extend between multiple first source / drain regions; Multiple second nanostructures are situated above the multiple first nanostructures, and the multiple second nanostructures extend between multiple second source / drain regions; A first gate stack surrounds the plurality of first nanostructures; A second gate stack is disposed above the first gate stack and around the plurality of second nanostructures, wherein a first portion of the second gate stack is disposed above the plurality of second nanostructures; Multiple gate spacers are located above multiple sidewalls of the first portion of the second gate stack. A first interlayer dielectric is located above a back side of the first gate stack; A first metal contact extends through the first portion of the second gate stack and extends between a first gate spacer and a second gate spacer among the plurality of gate spacers to physically contact a first source / drain region among the plurality of second source / drain regions, wherein a first air gap is disposed between a sidewall of the first metal contact and a sidewall of the first gate spacer. as well as A first back-side metal contact extends through the first interlayer dielectric to physically contact one of the plurality of first source / drain regions, wherein a second air gap is disposed between one sidewall of the first back-side metal contact and one sidewall of the first interlayer dielectric.

7. The semiconductor device as claimed in claim 6, characterized in that, Further includes: A second metal contact extends through the first portion of the second gate stack and between a third gate spacer and a fourth gate spacer of the plurality of gate spacers to physically contact a second source / drain region of the plurality of second source / drain regions; and A first spacer layer is disposed above a plurality of sidewalls of the second metal contact, wherein the first spacer layer surrounds the second metal contact and wherein the first spacer layer physically contacts the third gate spacer and the fourth gate spacer.

8. The semiconductor device as claimed in claim 7, characterized in that, The second metal contact overlaps with the first back-side metal contact.

9. The semiconductor device as claimed in claim 8, characterized in that, The width of the first back-side metal contact is smaller than the width of the second metal contact.

10. A semiconductor device, characterized in that, include: Multiple first nanostructures extend between multiple first source / drain regions; Multiple second nanostructures are situated above the multiple first nanostructures, and the multiple second nanostructures extend between multiple second source / drain regions; A first gate stack surrounds the plurality of first nanostructures; A second gate stack is disposed above the first gate stack and around the plurality of second nanostructures, wherein a first portion of the second gate stack is disposed above the plurality of second nanostructures; Multiple gate spacers are located above multiple sidewalls of the first portion of the second gate stack. A first metal contact extends between a first gate spacer and a second gate spacer among the plurality of gate spacers to physically contact a first source / drain region among the plurality of second source / drain regions, wherein an air gap is disposed between a sidewall of the first metal contact and a sidewall of the first gate spacer. as well as A first spacer layer is provided above a plurality of sidewalls of the first metal contact, wherein the first spacer layer surrounds the first metal contact, and wherein the air gap is disposed between the first spacer layer and the sidewall of the first gate spacer.

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