A silicon-on-insulator wafer

Abstract

The application discloses a silicon-on-insulator wafer and relates to the technical field of semiconductor preparation. The silicon-on-insulator wafer comprises a substrate wafer and a device wafer, the substrate wafer comprises a first bonding surface, the device wafer comprises a second bonding surface, the edges of the first bonding surface and the second bonding surface are provided with a first chamfer, the central angle of the first chamfer is any value in a range from 0.5° to 5°, and the chamfer radius is any value in a range from 0.2 μm to 50 μm. The silicon-on-insulator wafer can provide continuous support for the edges of the device wafer during the bonding and thinning of the device wafer, significantly inhibits the edge overhang and peeling phenomenon, improves the stability and flatness of the bonding interface, avoids the edge removal step in the traditional silicon-on-insulator wafer process, and thus simplifies the process flow and reduces the manufacturing cost.

Description

Technical Field

[0001] This utility model relates to semiconductor fabrication, specifically to a silicon-on-insulator wafer. Background Technology

[0002] Silicon-on-Insulator (SOI) wafers have become an important substrate material for the manufacture of advanced integrated circuits, radio frequency devices, and power devices due to their excellent characteristics such as low parasitic capacitance, fast switching speed, and good device isolation performance. The typical fabrication process of SOI wafers involves bonding a device wafer to a substrate wafer to form a buried oxide layer (BOX layer) between them, followed by thinning and polishing of the device wafer to obtain the required top silicon thickness.

[0003] However, in traditional SOI fabrication, because the substrate wafer typically employs a large chamfer structure to avoid the risk of edge chipping and fragmentation during cutting and handling, when the device wafer is thinned after bonding with the substrate wafer, the edge of the device layer often cannot completely adhere to the edge of the substrate, resulting in a certain suspended region. Under the subsequent chemical mechanical polishing (CMP) or thinning stress, this suspended region is prone to becoming a stress concentration point, leading to problems such as top silicon layer lifting, peeling, or interface crack propagation, resulting in wafer structure damage, decreased yield, and reduced reliability.

[0004] In existing technologies, edge trimming of the device layer after bonding is typically used to eliminate overhanging areas before thinning. However, this method not only increases the number of process steps and process complexity, but also may introduce additional risks of particulate contamination, and new structural defects are easily introduced during the edge trimming process. Utility Model Content

[0005] One objective of this invention is to provide a silicon-on-insulator (SiI) wafer that solves the cost problem in existing SiI wafers where the substrate wafer has a large chamfer, requiring edge removal after bonding.

[0006] Another objective of this invention is to improve the uniformity of interface contact and the density of bonding.

[0007] According to the purpose of this utility model, this utility model provides a silicon-on-insulator wafer, which includes a substrate wafer and a device wafer bonded together. The substrate wafer includes a first bonding surface, and the device wafer includes a second bonding surface. The edges of the first bonding surface and the second bonding surface are provided with a first rounding. The central angle of the first rounding is any value between 0.5° and 5°, and the rounding radius is any value between 0.2μm and 50μm.

[0008] Optionally, the bottom edge of the substrate wafer away from the first bonding surface is provided with the first rounded edge.

[0009] Optionally, the top edge of the device wafer away from the second bonding surface is provided with the first rounding.

[0010] Optionally, the surface roughness Ra of the substrate wafer is ≤10nm, and the subsurface damage depth is ≤5µm.

[0011] Optionally, the substrate wafer is formed by cutting a silicon ingot, and the cutting method is laser stealth cutting.

[0012] Optionally, the pulse energy of the laser stealth cutting process is any value between 0.5µJ and 2µJ, the overlap rate is any value between 200kHz and 1000kHz, and the pulse width is any value between 300fs and 1000fs.

[0013] Optionally, the focal depth of the laser stealth cutting process is any value between 300μm and 1000μm.

[0014] Optionally, the post-processing method for the silicon ingot cutting is thermal annealing or surface polishing.

[0015] This invention provides continuous support for the edges of the substrate wafer and the device wafer in a silicon-on-insulator (SiI) wafer by setting a first rounding at the edges, with the central angle of the first rounding being any value between 0.5° and 5° and the chamfer radius being any value between 0.2μm and 50μm. This significantly suppresses edge hanging and peeling phenomena, improves the stability and flatness of the bonding interface, and avoids the edge removal step in the traditional SiI wafer fabrication process, thereby simplifying the process flow and reducing manufacturing costs.

[0016] Furthermore, by controlling the surface roughness of the substrate wafer 10 to Ra≤10nm and the subsurface damage depth to ≤5µm, the present invention reduces the surface roughness, thereby giving the substrate wafer 10 a higher degree of flatness and smoothness. This effectively reduces stress concentration caused by surface micro-protrusions, processing marks, etc., thus providing more uniform interface contact and higher bonding density in subsequent bonding, peeling and other processes.

[0017] The above description is only an overview of the technical solution of this utility model. In order to better understand the technical means of this utility model and to implement it in accordance with the contents of the specification, the preferred embodiments of this utility model are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0018] The following sections will describe some specific embodiments of the present invention in a detailed manner by way of example and not limitation, with reference to the accompanying drawings. The same reference numerals in the drawings denote the same or similar parts or components. Those skilled in the art should understand that these drawings are not necessarily drawn to scale. In the drawings: Figure 1 This is a schematic structural diagram of silicon on insulator according to an embodiment of the present invention; Figure 2 This is a partial schematic structural diagram of silicon on insulator according to an embodiment of the present invention; Figure 3 This is a schematic structural diagram of silicon on insulator according to another embodiment of the present invention; Figure 4 This is a schematic structural flowchart of a method for preparing silicon-on-insulator according to an embodiment of the present invention.

[0019] Figure label: 100-Silicon on Insulator Wafer, 10-Substrate Wafer, 11-First Rounding, 12-First Bonding Surface, 13-Buried Oxide Layer, 14-Bottom Surface, 20-Device Wafer, 21-Second Bonding Surface, 22-Top Surface. Detailed Implementation

[0020] The specific embodiments of this utility model will be further described in detail below with reference to the accompanying drawings and examples. The following examples are used to illustrate this utility model, but are not intended to limit the scope of this utility model.

[0021] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0022] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0023] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0024] Figure 1 This is a schematic structural diagram of silicon-on-insulator according to one embodiment of the present invention. Figure 2 This is a partial schematic structural diagram of silicon-on-insulator according to an embodiment of the present invention. Figure 3 This is a schematic structural diagram of silicon-on-insulator according to another embodiment of the present invention. Figure 4 This is a schematic structural flowchart of a method for preparing silicon-on-insulator according to an embodiment of the present invention.

[0025] like Figure 1 As shown, this utility model provides a silicon-on-insulator (SBI) wafer 100, which includes a substrate wafer 10 and a device wafer 20 bonded together. The substrate wafer includes a first bonding surface, and the device wafer includes a second bonding surface. The edges of the first and second bonding surfaces are provided with a first rounded edge 11, and the central angle α of the first rounded edge 11 is (see...). Figure 2 The chamfer angle is any value between 0.5° and 5°, and the chamfer width W (see...) Figure 2 The value of is any value between 10μm and 150μm, and the chamfer radius is any value between 0.2μm and 50μm. Here, the central angle of the first chamfer 11 can be 0.5°, 1°, 1.5°, 2°, 2.5°, 3°, 3.5°, 4°, 4.5°, or 5°, or any other value between 0.5° and 5°. The chamfer width can be 10μm, 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, 130μm, 140μm, or 150μm, or any other value between 10μm and 150μm. The chamfer radius can be 0.2μm, 0.5μm, 1.0μm, 5.0μm, 10μm, 20μm, 30μm, 40μm, or 50μm, or any other value between 0.2μm and 50μm.

[0026] In this embodiment, a first rounding is provided at the edges of the substrate wafer 10 and the device wafer 20 of the silicon-on-insulator wafer 100. The central angle of the first rounding is any value between 0.5° and 5°, and the chamfer radius is any value between 0.2μm and 50μm. This provides continuous support for the edges of the device wafer 20 during the bonding process and the thinning process of the device wafer 20, significantly suppressing edge hanging and peeling phenomena, improving the stability and flatness of the bonding interface, and avoiding the edge removal step in the traditional silicon-on-insulator wafer 100 process, thereby simplifying the process flow and reducing manufacturing costs. Here, a second rounding is provided at the bottom edge of the substrate wafer 10. The size of the second rounding can be the same as the first rounding 11, or it can be the same as the rounding size in conventional processes (refer to...). Figure 3 The radius of the earth is generally 300μm-1000μm.

[0027] like Figure 3 As shown, in a further embodiment, the bottom surface 14 of the substrate wafer 10, away from the first bonding surface 12, is provided with a first rounded edge 11, that is, an arc transition structure is formed on the lower surface edge (i.e., the non-bonding surface side) of the substrate wafer 10. In this embodiment, by providing the first rounded edge 11 on the bottom surface 14 of the substrate wafer 10, away from the first bonding surface 12, the stress concentration at the edge of the substrate wafer 10 is effectively alleviated. This prevents edge chipping or microcracks during the handling, bonding, and subsequent heat treatment of the silicon-on-insulator wafer, while improving the overall mechanical strength and warpage control of the silicon-on-insulator wafer 100. In addition, the arc transition structure can also reduce the risk of edge film buildup or residual film during cleaning and coating processes, ensuring the flatness and reliability of the subsequent bonding interface, thereby improving the process stability and product yield of the silicon-on-insulator wafer 100.

[0028] In a further embodiment, the edge of the top surface 22 of the device wafer 20 away from the second bonding surface 21 is provided with a first rounded edge 11. In this embodiment, by providing the first rounded edge 11 at the edge of the top surface 22 of the device wafer 20 away from the second bonding surface 21, the edge morphology of the device wafer 20 has a rounded transition structure, thereby effectively reducing the risk of crack initiation caused by sharp edges during thermal stress release after bonding or subsequent thin film deposition and polishing processes, and avoiding peeling or damage to the thin-film device area on the top surface. At the same time, the rounded transition structure helps to improve the uniformity of the film layer on the top surface of the device wafer 20, reduce abrupt changes in film thickness at the edges, and improve the electrical and structural integrity of the device area edge.

[0029] In this embodiment, compared to the first rounding 11 on the substrate wafer 10 away from the first bonding surface 12, which is mainly used to enhance the overall mechanical support and prevent bottom edge cracking, the first rounding 11 on the device wafer 20 away from the second bonding surface 21 focuses on alleviating stress concentration in the top film layer and improving the edge reliability and surface flatness of the device area. The two complement each other in terms of their level of action and influence, thereby comprehensively improving the mechanical and interface stability of the silicon-on-insulator wafer 100.

[0030] In a further embodiment, the surface roughness Ra of the substrate wafer 10 is ≤10nm, and the subsurface damage depth is ≤5µm. In this embodiment, by controlling the surface roughness Ra of the substrate wafer 10 to ≤10nm and the subsurface damage depth to ≤5µm, the reduced surface roughness gives the substrate wafer 10 a higher degree of flatness and smoothness. This effectively reduces stress concentration caused by surface micro-protrusions, processing marks, etc., thereby providing more uniform interface contact and higher bonding density in subsequent bonding, peeling, and other processes. At the same time, the reduction in subsurface damage depth limits the propagation depth of microcracks and defects generated in processes such as cutting and chamfering into the wafer interior, significantly suppressing problems such as crack propagation, warping, or peeling interface failure caused by stress release.

[0031] In this embodiment, when both surface roughness and subsurface damage depth meet the aforementioned ranges, the residual stress distribution and interface bonding state of the silicon-on-insulator wafer 100 surface layer can be optimized overall, forming a continuous and stable structural integrity from the surface to the subsurface. This results in higher structural stability and process compatibility of the substrate wafer 10 during laser stealth dicing, bonding, and subsequent lift-off processes. Consequently, interface delamination, fragmentation, and yield fluctuations during the lift-off process are significantly reduced, and the fabrication consistency and reliability of the silicon-on-insulator wafer 100 are comprehensively improved.

[0032] In a further embodiment, the substrate wafer 10 is formed by cutting a silicon ingot using a laser stealth dicing process. In this embodiment, by using a laser stealth dicing process to cut the silicon ingot to form the substrate wafer 10, non-contact internal energy focusing and delamination fracture can be achieved during the cutting process, avoiding the significant mechanical stress and surface scratches generated by traditional diamond wire cutting or mechanical cutting methods.

[0033] In this embodiment, laser stealth dicing forms a modified layer inside the silicon ingot and achieves dissociation along the modified layer, eliminating the need for direct force on the dicing surface. This effectively reduces surface roughness, dicing marks, and microcracks, providing more ideal surface conditions for subsequent chamfering, bonding, and lift-off processes. Furthermore, since energy is concentrated primarily within the material rather than on the surface, the heat-affected zone and microcrack depth generated during dicing are significantly reduced, resulting in a marked improvement in the subsurface integrity of the wafer and further enhancing the structural stability of lift-off and bonding. Simultaneously, laser stealth dicing possesses high-precision focusing control capabilities, enabling precise control over wafer thickness and geometry, ensuring dimensional matching and bonding alignment accuracy between the substrate wafer 10 and the device wafer 20 in subsequent processes. Moreover, due to the significantly reduced mechanical load and damage risk during dicing, the probability of wafer breakage and edge chipping defects is significantly reduced, thereby improving overall wafer yield and the consistency of subsequent processes.

[0034] In a further embodiment, the pulse energy of the laser stealth cutting process is any value between 0.5µJ and 2µJ, the overlap rate is any value between 200kHz and 1000kHz, and the pulse width is any value between 300fs and 1000fs. That is, the pulse energy can be 0.5µJ, 1µJ, 1.5µJ, or 2µJ, or any other value between 0.5µJ and 2µJ; the overlap rate can be 200kHz, 300kHz, 400kHz, 500kHz, 600kHz, 700kHz, 800kHz, 900kHz, or 1000kHz, or any other value between 200kHz and 1000kHz; and the pulse width can be 300fs, 400fs, 500fs, 600fs, 700fs, 800fs, 900fs, or 1000fs, or any other value between 300fs and 1000fs. In this embodiment, by setting the pulse energy of the laser stealth dicing process to a parameter range of 0.5µJ-2µJ, the overlap rate to 200kHz-1000kHz, and the pulse width to 300fs-1000fs, stable and controllable formation of the modified layer and fracture path guidance can be achieved inside the silicon ingot. This effectively suppresses the expansion of the heat-affected zone while ensuring the cutting depth and positional accuracy, avoiding microcrack generation or surface ablation caused by excessively high energy, and also preventing poor cutting continuity or rough cross-section caused by excessively low energy. This not only obtains a wafer cutting cross-section with low surface roughness and small subsurface damage depth, but also significantly improves the stability and consistency of the cutting process, providing a high-quality substrate foundation for subsequent processes such as chamfering, device wafer bonding, and thinning and polishing, thereby improving the overall structural integrity and fabrication yield of silicon-on-insulator wafer 100.

[0035] In a further embodiment, the focal depth of the laser stealth dicing process is any value between 300μm and 1000μm, that is, the focal depth can be 300μm, 400μm, 500μm, 600μm, 700μm, 800μm, 900μm, or 1000μm, or any other value between 300μm and 1000μm. In this embodiment, by controlling the focal depth of the laser stealth dicing process within the range of 300μm-1000μm, the laser energy can be precisely focused on the predetermined modified layer position inside the silicon ingot, achieving controllable induction of the fracture layer. This effectively avoids problems such as surface ablation, edge chipping, or exposure of the cutting notch caused by too shallow a focal depth, and also prevents modified layer displacement, fracture discontinuity, or cutting path deviation caused by too deep a focal depth.

[0036] In a further embodiment, the post-processing method for silicon ingot cutting is thermal annealing or surface polishing. In this embodiment, by introducing thermal annealing or surface polishing after laser stealth cutting of the silicon ingot, residual stress and potential defects generated inside or on the surface of the wafer during the cutting process can be further eliminated. This effectively repairs microcracks and lattice distortions caused by the fracture of the modified layer, thereby significantly reducing the subsurface damage depth and improving the atomic-level surface smoothness. Simultaneously, thermal annealing can improve the crystal integrity and mechanical strength of the material, while surface polishing helps to obtain lower roughness and higher bonding interface quality.

[0037] like Figure 4 As shown, in this embodiment, the method for fabricating silicon-on-insulator wafer 100 includes: first, fabricating a substrate wafer 10 with a first rounded corner 11, and growing a buried oxide layer 13 on the periphery of the substrate wafer 10 using a furnace tube high-temperature oxidation process; then, performing Si-SiO2 bonding and high-temperature annealing treatment on the device wafer 20 and the substrate wafer 10 to prepare a bonded wafer; and finally, performing thinning and polishing treatment on the device wafer 20 to prepare silicon-on-insulator wafer 100.

[0038] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0039] The embodiments described above are merely illustrative of several implementations of this utility model, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these all fall within the protection scope of this utility model. Therefore, the protection scope of this utility model patent should be determined by the appended claims.

Claims

1. A silicon-on-insulator wafer, characterized in that, The silicon-on-insulator wafer includes a substrate wafer and a device wafer bonded together. The substrate wafer includes a first bonding surface, and the device wafer includes a second bonding surface. The edges of the first bonding surface and the second bonding surface are provided with a first rounding. The central angle of the first rounding is any value between 0.5° and 5°, and the rounding radius is any value between 0.2μm and 50μm.

2. The silicon-on-insulator wafer according to claim 1, characterized in that, The substrate wafer has the first rounded edge on its bottom surface away from the first bonding surface.

3. The silicon-on-insulator wafer according to claim 2, characterized in that, The device wafer has the first rounded edge on its top surface away from the second bonding surface.

4. The silicon-on-insulator wafer according to claim 3, characterized in that, The surface roughness Ra of the top surface and the bottom surface is ≤10nm, and the subsurface damage depth is ≤5µm.

5. The silicon-on-insulator wafer according to any one of claims 1-4, characterized in that, Both the substrate wafer and the device wafer are formed by cutting silicon ingots, and the silicon ingots are cut using a laser stealth cutting process.

6. The silicon-on-insulator wafer according to claim 5, characterized in that, The pulse energy of the laser stealth cutting process is any value between 0.5µJ and 2µJ, the overlap rate is any value between 200kHz and 1000kHz, and the pulse width is any value between 300fs and 1000fs.

7. The silicon-on-insulator wafer according to claim 6, characterized in that, The focal depth of the laser stealth cutting process is any value between 300μm and 1000μm.

8. The silicon-on-insulator wafer according to claim 7, characterized in that, The post-processing method for the silicon ingot cutting is thermal annealing or surface polishing.

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