Thin film transistor backplane structure and display panel

Abstract

The utility model provides a kind of thin film transistor backplate structure and display panel, the doping concentration of the ohmic contact layer of thin film transistor backplate structure is higher and closer to the position of second metal layer;The thickness of first metal layer and second metal layer is greater than the first thickness, in the case where first metal layer and second metal layer are the first thickness, the pixel charging rate reaches the target charging rate corresponding to high-order display mode. By setting the doping concentration of the ohmic contact layer to gradually increase from the amorphous silicon layer to the second metal layer, a lower contact resistance is formed in the ohmic contact layer, which increases the on-state current. At the same time, increasing the thickness of the first metal layer and the second metal layer allows the resistance of the first metal layer and the second metal layer to be reduced, further improving the charging rate and meeting the charging rate requirement of high-order display.

Description

Technical Field

[0001] This utility model relates to the field of display panels, and in particular to a thin-film transistor backplane structure and a display panel. Background Technology

[0002] High refresh rate, high resolution and other advanced display technologies have better rated display effects; however, in high-level displays, the charging time of pixels is shortened, and there is a problem of insufficient charging leading to poor display effect; in the existing technology, in order to ensure the charging rate under high-level display, polycrystalline silicon or oxide semiconductors with high on-state current are used to prepare TFT (Thin Film Transistor), but these materials are expensive. Utility Model Content

[0003] The main objective of this invention is to propose a thin-film transistor backplane structure and display panel, aiming to solve the problem of how to achieve high-end displays using low-cost materials in the prior art.

[0004] To achieve the above objectives, the present invention provides a thin-film transistor backplane structure, the thin-film transistor backplane structure including a substrate; A first metal layer is disposed on the substrate; An insulating layer is disposed on the first metal layer; An amorphous silicon layer is disposed on the insulating layer; An ohmic contact layer is disposed on the amorphous silicon layer; A second metal layer is disposed on the ohmic contact layer; in: The doping concentration is higher closer to the second metal layer in the ohmic contact layer; The thickness of the first metal layer and the second metal layer is greater than the first thickness. When the thickness of the first metal layer and the second metal layer is the first thickness, the pixel charging rate reaches the target charging rate corresponding to the high-order display mode.

[0005] Optionally, the ohmic contact layer includes a plurality of overlapping doped layers; The closer the doped layer is to the second metal layer, the higher the doping concentration.

[0006] Optionally, the profile angle of the first metal layer is smaller than the first angle. The profile angle of the first metal layer is the angle between the side of the first metal layer and the substrate. When the profile angle of the first metal layer is smaller than the first angle, the insulating layer completely covers the first metal layer.

[0007] Optionally, the thin-film transistor backplane structure further includes an insulating passivation layer disposed on the second metal layer; wherein: The contour angle of the second metal layer is smaller than the second angle. The contour angle of the second metal layer is the angle between the side of the second metal layer and the substrate. When the contour angle of the second metal layer is smaller than the second angle, the insulating passivation layer completely covers the second metal layer.

[0008] Optionally, a doped end is formed on the side of the ohmic contact layer near the channel, wherein the doped end does not contact the second metal layer.

[0009] Optionally, the amorphous silicon layer, the ohmic contact layer, and the second metal layer are aligned on the side away from the channel.

[0010] Optionally, the amorphous silicon layer includes channel amorphous silicon located in the channel region and non-channel amorphous silicon located in the non-channel region; wherein: The thickness of the channel amorphous silicon is less than the thickness of the non-channel amorphous silicon.

[0011] Optionally, at the crossover point between the first metal layer and the second metal layer, the insulating layer is disposed on the first metal layer; The amorphous silicon layer is disposed on the insulating layer; The ohmic contact layer is disposed on the amorphous silicon layer; The second metal layer is disposed on the ohmic contact layer.

[0012] Optionally, in the direction perpendicular to the metal trace of the second metal layer, the width of the ohmic contact layer is greater than the width of the metal trace; The width of the amorphous silicon layer is greater than the width of the ohmic contact layer; The width of the insulating layer is greater than the width of the amorphous silicon layer.

[0013] In addition, to achieve the above objectives, the present invention also provides a display panel, the display panel including a thin-film transistor backplane structure, the thin-film transistor backplane structure being configured as described above.

[0014] This invention proposes a thin-film transistor (TFT) backplane structure and a display panel. The TFT backplane structure includes a substrate; a first metal layer disposed on the substrate; an insulating layer disposed on the first metal layer; an amorphous silicon layer disposed on the insulating layer; an ohmic contact layer disposed on the amorphous silicon layer; and a second metal layer disposed on the ohmic contact layer. The doping concentration of the ohmic contact layer is higher closer to the second metal layer. The thickness of the first and second metal layers is greater than a first thickness. When the first and second metal layers are at the first thickness, the pixel charging rate reaches the target charging rate corresponding to a high-order display mode. By setting the doping concentration of the ohmic contact layer to gradually increase from the amorphous silicon layer to the second metal layer, a lower contact resistance is formed in the ohmic contact layer, resulting in an increase in the on-state current. Simultaneously, increasing the thickness of the first and second metal layers reduces their resistance, further improving the charging rate. Therefore, based on the use of amorphous silicon material, the on-state current is increased, meeting the charging rate requirements of high-order displays. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of one embodiment of the thin-film transistor backplane structure of this utility model; Figure 2 This is a schematic diagram of the ohmic contact layer in the backplane structure of the thin-film transistor of this utility model; Figure 3 This is a schematic diagram of the ohmic contact layer in the backplane structure of the thin-film transistor of this utility model; Figure 4 This is a top view of the thin-film transistor backplane structure of this utility model; Figure 5 This is a schematic diagram showing the cross-line position of the thin-film transistor backplane structure of this utility model; Figure 6 This utility model relates to the backplane structure of a thin-film transistor. Figure 5 Cross-sectional view of the middle section (BB); Figure 7 This utility model relates to the backplane structure of a thin-film transistor. Figure 5 CC cross-section view.

[0017] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0018] Explanation of icon numbers: Detailed Implementation

[0019] It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0020] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0021] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0022] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0023] This utility model provides a thin-film transistor backplane structure for use in display panels. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of an embodiment of the thin-film transistor backplane structure of this utility model. In this embodiment, the thin-film transistor backplane structure includes a substrate 10; A first metal layer 20 is disposed on the substrate 10; An insulating layer 30 is disposed on the first metal layer 20; An amorphous silicon layer 40 is disposed on the insulating layer 30; An ohmic contact layer 50 is disposed on the amorphous silicon layer 40; A second metal layer 60 is disposed on the ohmic contact layer 50; in: The doping concentration in the ohmic contact layer 50 is higher closer to the second metal layer 60; The thickness of the first metal layer 20 and the second metal layer 60 is greater than the first thickness. When the thickness of the first metal layer 20 and the second metal layer 60 is the first thickness, the pixel charging rate reaches the target charging rate corresponding to the high-order display mode.

[0024] The substrate 10 serves as the bottom support for the TFT backplane. The specific type can be set according to actual needs, such as glass substrate 10.

[0025] The first metal layer 20 and the second metal layer 60 are used to transmit electrical signals. The specific type of signal to be transmitted can be set according to actual needs, such as the first metal layer 20 transmitting gate scan signals and the second metal layer 60 transmitting data signals.

[0026] The insulating layer 30 is used to insulate the first metal layer 20 and the second metal layer 60. Since the first metal layer 20 and the second metal layer 60 transmit different electrical signals, it is necessary to provide an insulating layer 30 between the first metal layer 20 and the second metal layer 60 to ensure the isolated transmission of different signals.

[0027] The amorphous silicon layer 40 is a semiconductor layer made of amorphous material; the amorphous silicon layer 40 is through which charge carriers are transported. The channel region of the amorphous silicon layer 40 is located between the gate electrode and the source / drain electrode of the TFT. The switching on and off of the TFT is achieved by controlling the preference of the gate electrode.

[0028] The ohmic contact layer 50 is a doped semiconductor layer disposed between the amorphous silicon layer 40 and the second metal layer 60. The ohmic contact layer 50 is used to achieve low resistance and linear contact between the semiconductor and the metal, so that current can be injected and extracted efficiently. The specific material of the ohmic contact layer 50 can be set according to actual needs, such as setting it to an amorphous silicon layer 40 doped with nitrogen (N) element, with a doping concentration of N.

[0029] Since amorphous silicon has a smaller on-state current than crystalline silicon, in order to ensure the charging rate under amorphous silicon material, this embodiment improves the pixel charging rate by making special settings for the ohmic contact layer 50 and the metal layer. First, the doping concentration in the ohmic contact layer 50 is set to gradually increase from the amorphous silicon layer 40 to the second metal layer 60, forming a gentle band gradient, which can effectively reduce the barrier height for electrons to be injected from the second metal layer 60 into the channel of the amorphous silicon layer 40, reduce the contact resistance, and thus effectively improve the on-state current.

[0030] Meanwhile, by setting the thickness of the first metal layer 20 and the second metal layer 60 to be greater than a first thickness, the resistance of the first metal layer 20 and the second metal layer 60 can be reduced, further improving the transmission efficiency of electrical signals. The specific value of the first thickness can be set based on actual needs, such as 6300 Å. It is understood that in the prior art, the thickness of the first metal layer 20 and the second metal layer 60 is generally around 4000 Å. In this embodiment, the resistance of the metal is effectively reduced by increasing the thickness of the first metal layer 20 and the second metal layer 60.

[0031] By adjusting the doping concentration and metal layer thickness, the charging rate can be effectively improved. The target charging rate is the charging rate required for high-end display applications and can be set based on the actual requirements of the high-end display, such as 85%.

[0032] In this embodiment, by setting the doping concentration of the ohmic contact layer 50 to gradually increase from the amorphous silicon layer 40 to the second metal layer 60, a lower contact resistance is formed in the ohmic contact layer 50, thereby increasing the on-state current. At the same time, by increasing the thickness of the first metal layer 20 and the second metal layer 60, the resistance of the first metal layer 20 and the second metal layer 60 can be reduced, further improving the charging rate. Thus, based on the use of amorphous silicon material, the on-state current is improved, meeting the charging rate requirements of high-end displays.

[0033] Further, see Figure 2 The ohmic contact layer 50 includes multiple doped layers that are stacked together. The doping concentration of the doped layer is higher the closer it is to the second metal layer 60.

[0034] To facilitate fabrication, in this embodiment, the ohmic contact layer 50 is composed of multiple overlapping doped layers; and the doping concentration of the doped layer is higher the closer it is to the second metal layer 60, thereby achieving a gradual increase in doping concentration towards the second metal layer 60.

[0035] The number of doped layers can be set according to actual needs; for example, if the number of doped layers is 4, specifically including a first doped layer 51, a second doped layer 52, a third doped layer 53, and a fourth doped layer 54; the first doped layer 51 is disposed on the amorphous silicon layer 40, the second doped layer 52 is disposed on the first doped layer 51, the third doped layer 53 is disposed on the second doped layer 52, the fourth doped layer 54 is disposed on the third doped layer 53, and the second metal layer 60 is disposed on the fourth doped layer 54. In this case, the doping concentration of each doped layer is: first doped layer 51 < second doped layer 52 < third doped layer 53 < fourth doped layer 54; the specific doping concentration of each doped layer can be set according to actual needs while meeting the size requirements.

[0036] Further, see Figure 3The contour angle of the first metal layer 20 is less than the first angle. The contour angle of the first metal layer 20 is the angle between the side of the first metal layer 20 and the substrate 10. When the contour angle of the first metal layer 20 is less than the first angle, the insulating layer 30 completely covers the first metal layer 20.

[0037] When the insulating layer 30 is prepared on the first metal layer 20, the thickness of the first metal layer 20 is increased and the sides of the first metal layer 20 are steeper. Therefore, there is a greater possibility of wire breakage in the insulation, which leads to a decrease in insulation performance and may even cause a breakdown risk. Therefore, in order to improve the coverage reliability of the insulating layer 30 under such circumstances, the contour angle of the first metal layer 20 is set to be smaller than the first angle, so that the sides of the first metal layer 20 are gentler and the insulating layer 30 can completely cover the first metal layer 20, achieve good insulation performance, and avoid the occurrence of wire breakage and breakdown problems.

[0038] The specific value of the first angle can be set based on actual needs. It can be understood that the smaller the contour angle of the first metal layer 20, the gentler the side. However, due to the certain requirements on the thickness of the first metal layer 20, the first metal layer 20 will occupy a larger area. On the other hand, the larger the contour angle of the first metal layer 20, the steeper the side. However, the first metal layer 20 occupies a smaller area. Therefore, the value of the contour angle can be determined comprehensively based on the actual needs for height and area. Specifically, the contour angle value can be taken between 30° and 40°.

[0039] Furthermore, the thin-film transistor backplane structure further includes an insulating passivation layer 70 disposed on the second metal layer 60; wherein: The contour angle of the second metal layer 60 is smaller than the second angle. The contour angle of the second metal layer 60 is the angle between the side of the second metal layer 60 and the substrate 10. When the contour angle of the second metal layer 60 is smaller than the second angle, the insulating passivation layer 70 completely covers the second metal layer 60.

[0040] PV (Passivation Layer) is the uppermost insulating thin film layer of the TFT structure, used to protect the TFT device.

[0041] When the insulating passivation layer 70 is fabricated on the second metal layer 60, the thickness of the second metal layer 60 is increased, and the sides of the second metal layer 60 are steeper. Therefore, there is a greater possibility of wire breakage in the insulation. Therefore, in order to improve the coverage reliability of the insulating passivation layer 70 under these circumstances, the contour angle of the second metal layer 60 is set to be smaller than the second angle, so that the sides of the second metal layer 60 are gentler and the insulating passivation layer 70 can completely cover the second metal layer 60, thereby achieving good insulation between the TFT and the external environment.

[0042] The specific value of the second angle can be set based on actual needs. It can be understood that the smaller the contour angle of the second metal layer 60, the gentler the side surface. However, due to the certain requirements on the thickness of the second metal layer 60, the second metal layer 60 will occupy a larger area. On the other hand, the larger the contour angle of the second metal layer 60, the steeper the side surface, but the second metal layer 60 occupies a smaller area. Therefore, the value of the contour angle can be determined comprehensively based on the actual needs for height and area. Specifically, the contour angle value can be taken between 30° and 40°. The contour angles of the first metal layer 20 and the second metal layer 60 can be set to be the same.

[0043] Furthermore, a doped end is formed on the side of the ohmic contact layer 50 near the channel, wherein the doped end does not contact the second metal layer 60.

[0044] The ohmic contact layer 50 protrudes relative to the side of the second metal layer 60 on the side near the channel. The protruding part is the doped end tail. The doped end is used to buffer the electric field, improve carrier injection, and suppress short-channel effects.

[0045] The specific length of the doped end can be set according to actual needs. It should be noted that if the length of the doped end is too long, it will lead to a larger parasitic resistance and affect the performance of the short-channel TFT. If the length of the doped end is too short, it will increase the leakage current. Therefore, the length of the doped end can be set according to the actual structural characteristics, such as between 0.8 and 1 μm.

[0046] Further, see Figure 4 The amorphous silicon layer 40, the ohmic contact layer 50, and the second metal layer 60 are aligned on the side away from the channel.

[0047] In the prior art, on the side away from the channel, the amorphous silicon layer 40 extends outward relative to the second metal layer 60 to compensate for alignment errors. However, this method leads to an increase in the TFT area, thus affecting the high-resolution settings in high-order displays. In this application, by aligning the amorphous silicon layer 40, the ohmic contact layer 50, and the second metal layer 60 on the side away from the channel, the area of ​​the amorphous silicon layer 40 can be reduced as much as possible, thereby reducing the TFT footprint and achieving a more compact TFT setup, thus enabling a higher resolution setting. Specifically, during the alignment process, the amorphous silicon layer 40 and the ohmic contact layer 50 can be aligned along the contour angle direction of the second metal layer 60 after the second metal layer 60 is fabricated.

[0048] Further, see Figure 3The amorphous silicon layer 40 includes a channel amorphous silicon 41 located in the channel region and a non-channel amorphous silicon 42 located in the non-channel region; wherein: The thickness of the channel amorphous silicon 41 is less than the thickness of the non-channel amorphous silicon 42.

[0049] It is understandable that the transport of charge carriers in a TFT mainly occurs in the region of the amorphous silicon layer 40 near the gate, rather than the entire amorphous silicon layer 40. Therefore, making the amorphous silicon layer 40 thinner will not affect the transport of charge carriers, while making the amorphous silicon layer 40 thicker will lead to an increase in parasitic capacitance and generate more losses. Therefore, in this embodiment, making the thickness of the channel amorphous silicon 41 thinner can increase the on-state current.

[0050] Since the non-channel amorphous silicon 42 needs to contact the ohmic contact layer 50 to contact the second metal layer 60, it is necessary to ensure that the non-channel amorphous silicon 42 has a certain thickness to improve contact reliability. In order to ensure the contact reliability of the non-channel amorphous silicon 42 and the improvement of the on-state current of the channel amorphous silicon 41, the thicknesses of the non-channel amorphous silicon 42 and the channel amorphous silicon 41 are set separately in this embodiment. The non-channel amorphous silicon 42 is set to be thicker, while the channel amorphous silicon 41 is set to be thinner, thereby simultaneously achieving the improvement of contact reliability and on-state current.

[0051] The specific thicknesses of non-channel amorphous silicon 42 and channel amorphous silicon 41 can be set according to actual needs, such as setting non-channel amorphous silicon 42 to 1400 Å and channel amorphous silicon 41 to 800 Å.

[0052] Further, see Figure 5 and Figure 6 At the crossover position between the first metal layer 20 and the second metal layer 60, the insulating layer 30 is disposed on the first metal layer 20; The amorphous silicon layer 40 is disposed on the insulating layer 30; The ohmic contact layer 50 is disposed on the amorphous silicon layer 40; The second metal layer 60 is disposed on the ohmic contact layer 50.

[0053] The crossover location cro is the location where the first metal layer 20 and the second metal layer 60 outside the TFT form a crossover.

[0054] In the prior art, only an insulating layer 30 is provided at the crossover position to achieve insulation between the first metal layer 20 and the second metal layer 60. However, in this application, the thickness of the first metal layer 20 and the second metal layer 60 is increased. Therefore, the side of the first metal layer 20 becomes steeper, and the second metal layer 60 is more prone to breakage during ramping, or even breakdown. Therefore, in order to ensure insulation performance, in this embodiment, an amorphous silicon layer 40 and an ohmic contact layer 50 are provided at the crossover position between the first metal layer 20 and the second metal layer 60 in the non-TFT body area. This increases the thickness between the first metal layer 20 and the second metal layer 60, facilitates the ramping setting of the second metal layer 60, improves the reliability of the second metal layer 60, and avoids breakage problems.

[0055] In specific settings, to avoid color shift, the thickness of the insulating layer 30 needs to be set. It is understandable that if the insulating layer 30 is too thick, the total height of the TFT structure will be too high, which will lead to the coverage problem of the insulating passivation layer 70, causing deformation and thus resulting in color shift. On the other hand, if the insulating layer 30 is too thin, it will reduce the insulation performance between the first metal layer 20 and the second metal layer 60. Therefore, the thickness of the insulating layer 30 needs to be set in a balanced way to avoid color shift and ensure insulation performance. For example, it can be set to 3500±500Å.

[0056] Further, see Figure 7 In the direction perpendicular to the metal traces of the second metal layer 60, the width of the ohmic contact layer 50 is greater than the width of the metal traces. The width of the amorphous silicon layer 40 is greater than the width of the ohmic contact layer 50; The width of the insulating layer 30 is greater than the width of the amorphous silicon layer 40.

[0057] The increased height of the first metal layer 20 and the second metal layer 60, as well as the increased height of the amorphous silicon layer 40 and the ohmic contact layer 50, leads to an increase in the overall height at the cross-line position, which can easily cause the prepared insulating passivation layer 70 to have incomplete coverage.

[0058] In this embodiment, at the cross-line position, the width of different layers gradually narrows from bottom to top, so that the TFT as a whole presents a stepped shape; under this case, the preparation of the insulating passivation layer 70 can achieve good coverage and ensure the reliability of the panel.

[0059] This utility model also protects a display panel, which includes a thin-film transistor (TFT) backplane structure. The structure of the TFT backplane structure can be referred to the above embodiments, and will not be repeated here. Therefore, since the display panel of this embodiment adopts the above-described TFT backplane structure technology, the display panel has all the beneficial effects of the above-described TFT backplane structure.

[0060] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0061] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural or procedural transformations made based on the description and drawings of this utility model, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this utility model.

Claims

1. A thin-film transistor backplane structure, characterized in that, The thin-film transistor backplane structure includes a substrate; A first metal layer is disposed on the substrate; An insulating layer is disposed on the first metal layer; An amorphous silicon layer is disposed on the insulating layer; An ohmic contact layer is disposed on the amorphous silicon layer; A second metal layer is disposed on the ohmic contact layer; in: The doping concentration is higher closer to the second metal layer in the ohmic contact layer; The thickness of the first metal layer and the second metal layer is greater than the first thickness. When the thickness of the first metal layer and the second metal layer is the first thickness, the pixel charging rate reaches the target charging rate corresponding to the high-order display mode.

2. The thin-film transistor backplane structure as described in claim 1, characterized in that, The ohmic contact layer includes multiple overlapping doped layers; The closer the doped layer is to the second metal layer, the higher the doping concentration.

3. The thin-film transistor backplane structure as described in claim 1, characterized in that, The contour angle of the first metal layer is less than the first angle. The contour angle of the first metal layer is the angle between the side of the first metal layer and the substrate. When the contour angle of the first metal layer is less than the first angle, the insulating layer completely covers the first metal layer.

4. The thin-film transistor backplane structure as described in claim 1, characterized in that, The thin-film transistor backplane structure further includes an insulating passivation layer disposed on the second metal layer; wherein: The contour angle of the second metal layer is smaller than the second angle. The contour angle of the second metal layer is the angle between the side of the second metal layer and the substrate. When the contour angle of the second metal layer is smaller than the second angle, the insulating passivation layer completely covers the second metal layer.

5. The thin-film transistor backplane structure as described in claim 1, characterized in that, The ohmic contact layer has a doped end on the side near the channel, wherein the doped end is not in contact with the second metal layer.

6. The thin-film transistor backplane structure as described in claim 1, characterized in that, The amorphous silicon layer, the ohmic contact layer, and the second metal layer are aligned on the side away from the channel.

7. The thin-film transistor backplane structure as described in claim 1, characterized in that, The amorphous silicon layer includes channel amorphous silicon located in the channel region and non-channel amorphous silicon located in the non-channel region; wherein: The thickness of the channel amorphous silicon is less than the thickness of the non-channel amorphous silicon.

8. The thin-film transistor backplane structure as described in claim 1, characterized in that, At the crossover point between the first metal layer and the second metal layer, the insulating layer is disposed on the first metal layer; The amorphous silicon layer is disposed on the insulating layer; The ohmic contact layer is disposed on the amorphous silicon layer; The second metal layer is disposed on the ohmic contact layer.

9. The thin-film transistor backplane structure as described in claim 8, characterized in that, In the direction perpendicular to the metal trace of the second metal layer, the width of the ohmic contact layer is greater than the width of the metal trace; The width of the amorphous silicon layer is greater than the width of the ohmic contact layer; The width of the insulating layer is greater than the width of the amorphous silicon layer.

10. A display panel, characterized in that, The display panel includes a thin-film transistor backplane structure as described in any one of claims 1 to 9.

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