A bidirectional ESD protection device and electronic equipment

Abstract

The utility model discloses a kind of two-way ESD protection devices and electronic equipment, two-way ESD protection device includes: substrate;Semiconductor epitaxial layer, located in one side of substrate;Semiconductor epitaxial layer includes oppositely arranged first surface and second surface, and first surface is the surface of semiconductor epitaxial layer far from one side of substrate;Semiconductor epitaxial layer includes the first doped region and the second doped region of same conductive type, and both are located in first surface;The conductive type of first doped region and semiconductor epitaxial layer is different;The conductive type of substrate and semiconductor epitaxial layer is different;At least one isolation groove, from the first surface between first doped region and second doped region downwardly extends into substrate;First electrode, contact with first doped region;Second electrode, contact with second doped region.The technical scheme provided by the utility model reduces the epitaxial thickness of device and the depth of grooving, improves the voltage resistance of device and reduces the capacitance of device.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and in particular to a bidirectional ESD protection device and electronic device. Background Technology

[0002] ESD (Electro-Static Discharge) protection is an important part of IC (Integrated Circuit) design. ESD protection devices play a role in protecting the internal circuitry from damage caused by electrostatic discharge.

[0003] Bidirectional ESD devices are an indispensable component of ESD protection circuits in circuit applications, and these devices need to meet both positive and negative withstand voltage requirements. In related technologies, vertically structured bidirectional ESD devices suffer from low breakdown voltage due to limitations in epitaxial thickness and groove depth. Laterally structured bidirectional ESD devices avoid these limitations, but still cannot meet the high withstand voltage requirements and have large capacitance. Therefore, how to reduce the epitaxial thickness and groove depth of bidirectional ESD devices while improving their withstand voltage and reducing their capacitance has become a pressing technical problem for those skilled in the art. Utility Model Content

[0004] This utility model provides a bidirectional ESD protection device and electronic device, which reduces the epitaxial thickness and groove depth of the bidirectional ESD device while improving the withstand voltage and reducing the capacitance of the device.

[0005] According to one aspect of this utility model, a bidirectional ESD protection device is provided, comprising:

[0006] Substrate;

[0007] A semiconductor epitaxial layer is located on one side of the substrate; the semiconductor epitaxial layer includes a first surface and a second surface disposed opposite to each other, the first surface being the surface of the semiconductor epitaxial layer away from the substrate; the semiconductor epitaxial layer includes a first doped region and a second doped region of the same conductivity type, both located on the first surface; wherein the first doped region has a different conductivity type than the semiconductor epitaxial layer; the substrate has a different conductivity type than the semiconductor epitaxial layer;

[0008] At least one isolation trench, the at least one isolation trench extending downward from a first surface located between the first doped region and the second doped region into the substrate;

[0009] The first electrode is in contact with the first doped region;

[0010] The second electrode is in contact with the second doped region.

[0011] Optionally, the first electrode is electrically connected to the signal port to be protected, and the second electrode is grounded; or, the second electrode is connected to the signal port to be protected, and the first electrode is grounded.

[0012] The substrate, the first doped region, and the second doped region are all N-type; the semiconductor epitaxial layer is P-type.

[0013] Optionally, the angle between the extension direction of the isolation trench and the direction perpendicular to the substrate is greater than or equal to 0° and less than or equal to 5°.

[0014] Optionally, the bidirectional ESD protection device further includes an isolation layer located in the isolation trench.

[0015] Optionally, the bidirectional ESD protection device further includes a dielectric layer located on the first surface of the semiconductor epitaxial layer;

[0016] The dielectric layer includes a first opening and a second opening; wherein the first opening exposes the first doped region, and the second opening exposes the second doped region; the first electrode contacts the first doped region through the first opening, and the second electrode contacts the first doped region through the second opening.

[0017] Optionally, the at least one isolation trench includes: a first isolation trench located on opposite sides of the first doped region and a second isolation trench located on opposite sides of the second doped region.

[0018] Optionally, the depth of the isolation trench ranges from 5µm to 30µm;

[0019] The thickness of the semiconductor epitaxial layer ranges from 5µm to 35µm;

[0020] The thickness of the substrate ranges from 90µm to 200µm.

[0021] Optionally, the resistivity of the substrate ranges from [specific value]. ;

[0022] The resistivity range of the semiconductor epitaxial layer is: .

[0023] Optionally, the bidirectional ESD protection device further includes:

[0024] A passivation layer is located on the side of the first electrode away from the semiconductor epitaxial layer, on the side of the second electrode away from the semiconductor epitaxial layer, and between the first electrode and the second electrode.

[0025] According to one aspect of the present invention, an electronic device is provided, including the bidirectional ESD protection device described in any embodiment of the present invention.

[0026] This utility model provides a bidirectional ESD protection device and electronic device. The bidirectional ESD protection device includes: a substrate; a semiconductor epitaxial layer located on one side of the substrate; the semiconductor epitaxial layer includes a first surface and a second surface disposed opposite to each other, the first surface being the surface of the semiconductor epitaxial layer away from the substrate; the semiconductor epitaxial layer includes a first doped region and a second doped region of the same conductivity type, both located on the first surface; wherein the first doped region has a different conductivity type than the semiconductor epitaxial layer; the substrate has a different conductivity type than the semiconductor epitaxial layer; at least one isolation trench, the at least one isolation trench extending downward from the first surface located between the first doped region and the second doped region into the substrate; a first electrode in contact with the first doped region; and a second electrode in contact with the second doped region. The technical solution provided by this utility model, by adjusting the bidirectional ESD device with a vertical structure to a bidirectional ESD device with a horizontal structure, can reduce the epitaxial thickness and the trench depth, thereby avoiding the problem of high withstand voltage being difficult to achieve due to the limitations of epitaxial thickness and trench depth; moreover, by changing the NPN structure in the bidirectional ESD protection device to an NPNP structure, the withstand voltage of the bidirectional ESD protection device can be further improved, and the capacitance of the bidirectional ESD protection device can also be reduced.

[0027] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this utility model, nor is it intended to limit the scope of this utility model. Other features of this utility model will become readily apparent from the following description. Attached Figure Description

[0028] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a schematic diagram of the structure of a bidirectional ESD protection device provided in an embodiment of the present invention;

[0030] Figure 2 This is a schematic diagram of another bidirectional ESD protection device provided in this embodiment of the present invention;

[0031] Figure 3 This is a schematic diagram of another bidirectional ESD protection device provided in this embodiment of the present invention;

[0032] Figure 4 This is a schematic diagram of another bidirectional ESD protection device provided in this embodiment of the present invention. Detailed Implementation

[0033] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0034] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this utility model are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the utility model described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0035] This utility model embodiment provides a bidirectional ESD protection device. Figure 1 This is a schematic diagram of the structure of a bidirectional ESD protection device provided in an embodiment of this utility model, with reference to... Figure 1 Bidirectional ESD protection devices include:

[0036] Substrate 10;

[0037] A semiconductor epitaxial layer 20 is located on one side of the substrate 10. The semiconductor epitaxial layer 20 includes a first surface 201 and a second surface 202 disposed opposite to each other. The first surface 201 is the surface of the semiconductor epitaxial layer 20 away from the substrate 10. The semiconductor epitaxial layer 20 includes a first doped region 221 and a second doped region 222 of the same conductivity type, both located on the first surface 201. The first doped region 221 has a different conductivity type than the semiconductor epitaxial layer 20. The substrate 10 has a different conductivity type than the semiconductor epitaxial layer 20.

[0038] At least one isolation trench 40 extends downward from a first surface 201 located between a first doped region 221 and a second doped region 222 into the substrate 10;

[0039] The first electrode 31 is in contact with the first doped region 221;

[0040] The second electrode 32 is in contact with the second doped region 222.

[0041] Specifically, substrate 10 may be a semiconductor substrate. In some embodiments, the material of substrate 10 may include, for example, but not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, substrate 10 may be a material having <111> A oriented silicon substrate 10. A semiconductor epitaxial layer 20 is located on one side of the substrate 10. The material of the substrate 10 may be the same as or different from the material of the semiconductor epitaxial layer 20. Generally, the semiconductor epitaxial layer 20 may include semiconductor materials from group IV semiconductors, IV-IV compound semiconductor materials, III-V compound semiconductor materials, or a combination of the above materials. Examples of semiconductor materials from group IV semiconductors include, in particular, silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include, in particular, silicon carbide (SiC) and silicon germanium (SiGe). Examples of III-V compound semiconductor materials include, in particular, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). The conductivity type of the semiconductor epitaxial layer 20 is different from that of the substrate 10.

[0042] The surface of the semiconductor epitaxial layer 20 closest to the substrate 10 (i.e., the second surface 202) may or may not be in contact with the substrate 10. When the surface of the semiconductor epitaxial layer 20 closest to the substrate 10 is not in contact with the substrate 10, a buffer layer may be provided between the substrate 10 and the semiconductor epitaxial layer 20. The buffer layer may be in contact with the semiconductor epitaxial layer 20. The buffer layer is used to reduce lattice and thermal mismatch between the substrate 10 and the semiconductor epitaxial layer 20, thereby solving defects caused by mismatch / difference.

[0043] The semiconductor epitaxial layer 20 includes a doped region 22 with a different conductivity type than the semiconductor epitaxial layer 20. The doped region 22 is formed by ion implantation on the first surface 201 of the semiconductor epitaxial layer 20. The thickness of the doped region 22 is less than the thickness of the semiconductor epitaxial layer 20. A PN junction is formed between the doped region 22 and the semiconductor epitaxial layer 21 located on the side of the doped region closer to the substrate 10, and a PN junction is formed between the semiconductor epitaxial layer 21 located on the side of the doped region closer to the substrate 10 and the substrate 10. The doped region 22 in the semiconductor epitaxial layer 20 includes a first doped region 221 and a second doped region 222, which are two heavily doped regions with the same conductivity type. The first doped region 221 and the second doped region 222 are isolated by an isolation trench 40. At least one isolation trench 40 extends downward from the first surface 201 located between the first doped region 221 and the second doped region 222 into the substrate 10. It can be seen that the isolation trench 40 penetrates the semiconductor epitaxial layer 20 and extends into the substrate 10. Therefore, based on the depth of the isolation trench 40, different epitaxial layer portions can be isolated.

[0044] The first doped region 221 is used to contact the first electrode 31, and the second doped region 222 is used to contact the second electrode 32. The first electrode 31 and the second electrode 32 are externally connected to different terminals. Therefore, when the bidirectional ESD protection device is in operation, the current in the first direction flows into the first electrode 31, passes sequentially through the first doped region 221, the semiconductor epitaxial layer 21 located between the first doped region 221 and the substrate 10, the substrate 10, the semiconductor epitaxial layer 21 located between the second doped region 222 and the substrate 10, and the second doped region 222, flows to the second electrode 32 and flows out through the second electrode 32. The current in the second direction enters from the second electrode 32, passes sequentially through the second doped region 222, the semiconductor epitaxial layer 21 located between the second doped region 222 and the substrate 10, the substrate 10, the semiconductor epitaxial layer 21 located between the first doped region 221 and the substrate 10, and the first doped region 221, flows to the first electrode 31 and flows out through the first electrode 31. Therefore, the first directional current needs to flow through four PN junctions between the first electrode 31 and the second electrode 32, of which two PN junctions are forward-biased and two are reverse-biased; the second directional current needs to flow through four PN junctions between the second electrode 32 and the first electrode 31, of which two PN junctions are forward-biased and two are reverse-biased. It should be noted that the first directional current and the second directional current do not flow in simultaneously.

[0045] The first electrode 31 and the second electrode 32 are located on the same side of the semiconductor epitaxial layer 20, so that the bidirectional ESD device provided in this embodiment of the present invention forms a lateral NPNP structure. Compared with the vertical NPN structure in the related art, by adjusting the vertical bidirectional ESD device to a lateral bidirectional ESD device, the thickness of the semiconductor epitaxial layer 20 and the depth of the isolation trench 40 can be reduced, thereby avoiding the problem of high withstand voltage being difficult to achieve due to the limitations of epitaxial thickness and trench depth. It can also reduce the fragmentation rate during wafer thinning and reduce losses. By changing the NPN structure in the bidirectional ESD protection device to an NPNP structure, a reverse-biased NP junction can be added in the current path of the first direction current and the current path of the second direction current, thereby improving the withstand voltage of the bidirectional ESD protection device and reducing the capacitance of the bidirectional ESD protection device.

[0046] The technical solution provided by this utility model embodiment reduces the epitaxial thickness and trench depth by adjusting the longitudinally structured bidirectional ESD device to a laterally structured bidirectional ESD device, thereby avoiding the problem of achieving high withstand voltage due to limitations in epitaxial thickness and trench depth. Furthermore, by changing the NPN structure in the bidirectional ESD protection device to an NPNP structure, the withstand voltage of the bidirectional ESD protection device can be further improved, and the capacitance can be reduced. Thus, it achieves the simultaneous reduction of epitaxial thickness and trench depth of the bidirectional ESD device while improving its withstand voltage and reducing its capacitance.

[0047] Based on the above embodiments, optionally, the substrate 10, the first doped region 221, and the second doped region 222 are all N-type; the semiconductor epitaxial layer 20 (the semiconductor epitaxial layer 21 located between the first doped region 221 and the substrate 10 and the semiconductor epitaxial layer 21 located between the second doped region 222 and the substrate 10) is P-type. The substrate 10, the first doped region 221, and the second doped region 222 are doped with N-type ions, and the semiconductor epitaxial layer 20 is doped with P-type ions. The N-type ions can be P (phosphorus) ions or N (nitrogen) ions, and the P-type ions can be Al (aluminum) ions or B (boron) ions.

[0048] In this design, substrate 10 is an N+ type substrate, semiconductor epitaxial layer 20 is a P- type epitaxial layer, and the first doped region 221 and the second doped region 222 are both N+ type doped regions within the P- type epitaxial layer. The semiconductor terminology used herein is commonly used by those skilled in the art. For example, to distinguish between P-type and N-type impurities, for simplicity, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0049] Based on the above embodiments, optionally, the first electrode 31 is electrically connected to the signal port to be protected, and the second electrode 32 is grounded; or, the second electrode 32 is connected to the signal port to be protected, and the first electrode 31 is grounded.

[0050] Specifically, since the conductivity type of the first doped region 221 and the conductivity type of the second doped region 222 are the same, the structures on both sides of the isolation trench 40 are both vertical NPN structures. Therefore, the first electrode 31 can be electrically connected to the signal port to be protected, and the second electrode 32 can be grounded; alternatively, the second electrode 32 can be connected to the signal port to be protected, and the first electrode 31 can be grounded. When the first electrode 31 is electrically connected to the signal port to be protected, the signal port to be protected is connected to a signal line, and the first electrode 31 is connected to the signal line, thus the first electrode 31 is electrically connected to the signal port to be protected via the signal line. When the second electrode 32 is electrically connected to the signal port to be protected, the signal port to be protected is connected to a signal line, and the second electrode 32 is connected to the signal line, thus the second electrode 32 is electrically connected to the signal port to be protected via the signal line.

[0051] When a positive ESD pulse appears on the signal line, the bidirectional ESD protection device conducts between the signal line and ground, discharging current to ground. When a negative ESD pulse appears on the signal line, the bidirectional ESD protection device also conducts between ground and the signal line, completing the discharge. Because it is bidirectional, the bidirectional ESD protection device can provide protection regardless of whether the ESD pulse is positive or negative, and there is no need to distinguish the direction when connecting it.

[0052] Based on the above embodiments, optionally, the angle between the extending direction of the isolation trench 40 and the direction Y perpendicular to the substrate 10 is greater than or equal to 0° and less than or equal to 5°. The direction X is parallel to the plane containing the substrate 10.

[0053] Specifically, the extension direction of the isolation trench 40 can be perpendicular to the Y direction of the substrate 10, in which case the angle between the extension direction of the isolation trench 40 and the Y direction perpendicular to the substrate 10 is equal to 0°; the extension direction of the isolation trench 40 can also deviate from the Y direction perpendicular to the substrate 10, in which case the angle between the extension direction of the isolation trench 40 and the Y direction perpendicular to the substrate 10 is greater than 0°. Setting the angle between the extension direction of the isolation trench 40 and the Y direction perpendicular to the substrate 10 to a range of greater than or equal to 0° and less than or equal to 5° allows the approximately vertical isolation trench 40 to achieve the maximum depth within a minimal footprint. This means that, under the premise of achieving the same electrical isolation depth, the isolation trench 40 occupies the smallest area on the device surface, which is beneficial for device miniaturization.

[0054] Based on the above embodiments, Figure 2 This is a schematic diagram of another bidirectional ESD protection device provided in an embodiment of this utility model, for reference. Figure 2 Optionally, the bidirectional ESD protection device also includes an isolation layer 401 located in the isolation trench 40.

[0055] Specifically, the isolation layer 401 at least covers the walls of the isolation trench 40, and the isolation layer 401 may also completely fill the isolation trench 40. The material of the isolation layer 401 includes, but is not limited to, SiO2. A SiO2 capping layer can be formed on the walls of the isolation trench 40 through a thermal oxidation process; then, a SiO2 filling layer is filled into the isolation trench 40 to form the isolation layer 401. By forming the isolation layer 401 in the isolation trench 40, the electrical isolation between the first doped region 221 and the second doped region 222 can be improved, and the filling material (especially silicon dioxide) can provide mechanical support for the trench sidewalls after curing, enhancing the mechanical strength of the bidirectional ESD protection device. In other embodiments of this invention, a SiO2 capping layer can be formed on the walls of the isolation trench 40 through a thermal oxidation process; then, a polycrystalline silicon filling layer is filled into the isolation trench 40 to form the isolation layer 401. Polycrystalline silicon material can effectively fill trenches with high aspect ratios without creating voids.

[0056] Optionally, the depth of the isolation trench 40 ranges from 5 μm to 30 μm; the thickness of the semiconductor epitaxial layer 20 ranges from 5 μm to 35 μm; and the thickness of the substrate 10 ranges from 90 μm to 200 μm.

[0057] Optionally, the resistivity of substrate 10 can range from [specific value]. The resistivity range of the semiconductor epitaxial layer 20 is as follows: .

[0058] Based on the above embodiments, refer to Figures 1-2Optionally, the bidirectional ESD protection device also includes a dielectric layer 50, which is located on the first surface 201 of the semiconductor epitaxial layer 20.

[0059] The dielectric layer 50 includes a first opening and a second opening; wherein the first opening exposes a first doped region 221 and the second opening exposes a second doped region 222; the first electrode 31 contacts the first doped region 221 through the first opening and the second electrode 32 contacts the first doped region 221 through the second opening.

[0060] Specifically, the dielectric layer 50 can be silicon dioxide, silicon nitride, or a composite layer thereof. The dielectric layer 50 covers the entire first surface 201 of the semiconductor epitaxial layer 20 and the isolation layer 401 in the isolation trench 40. A first opening and a second opening are etched in the dielectric layer 50. The first opening completely exposes a surface portion of the underlying first doped region 221, and the second opening completely exposes a surface portion of the underlying second doped region 222. A first electrode 31 fills the first opening and forms an ohmic contact with the exposed surface of the first doped region 221. A second electrode 32 fills the second opening and forms an ohmic contact with the exposed surface of the second doped region 222. The dielectric layer 50 covers the isolation layer in the isolation trench 40.

[0061] Based on the above embodiments, Figure 3 This is a schematic diagram of another bidirectional ESD protection device provided in an embodiment of this utility model, for reference. Figure 3 Optionally, at least one isolation trench 40 includes: a first isolation trench 41 located on opposite sides of the first doped region 221 and a second isolation trench 42 located on opposite sides of the second doped region 222.

[0062] Specifically, the bidirectional ESD protection device includes multiple isolation trenches 40. A first doped region 221 and a second doped region 222 are distributed between corresponding isolation trenches 40, and the first doped region 221 and the second doped region 222 are distributed between different isolation trenches 40. The first doped region 221 is disposed between two first isolation trenches 41, each first isolation trench 41 extending downward from the first surface 201 into the substrate 10, and each first isolation trench 41 contains an isolation layer 401. The second doped region 222 is disposed between two second isolation trenches 42, each second isolation trench 42 extending downward from the first surface 201 into the substrate 10, and each second isolation trench 42 contains an isolation layer 401. By providing first isolation trenches 41 on opposite sides of the first doped region 221, the width of the first doped region 221 can be defined by the two first isolation trenches 41. Similarly, by providing second isolation trenches 42 on opposite sides of the second doped region 222, the width of the first doped region 221 can be defined by the two second isolation trenches 42. In this case, two isolation trenches 40 (a first isolation trench 41 and a second isolation trench 42) are provided between the first doped region 221 and the second doped region 222, which can further improve the electrical isolation between the first doped region 221 and the second doped region 222.

[0063] Based on the above embodiments, Figure 4 This is a schematic diagram of another bidirectional ESD protection device provided in this embodiment of the present invention, for reference. Figure 4 Optional, bidirectional ESD protection devices also include:

[0064] The passivation layer 60 is located on the side of the first electrode 31 away from the semiconductor epitaxial layer 20, on the side of the second electrode 32 away from the semiconductor epitaxial layer 20, and between the first electrode 31 and the second electrode 32.

[0065] Specifically, a passivation layer 60 is disposed on the side of the first electrode 31 away from the semiconductor epitaxial layer 20, the side of the second electrode 32 away from the semiconductor epitaxial layer 20, and between the first electrode 31 and the second electrode 32. The passivation layer 60 includes external vias for the first and second electrodes. The first external via exposes a portion of the surface of the first electrode 31 beneath it, and the second external via exposes a portion of the surface of the second electrode 32 beneath it. This passivation layer 60 can, for example, enhance the device's ability to block ion contamination, thereby providing protection. Specifically, the passivation layer 60 can reduce various charges in the oxide layer, enhance the blocking ability, and protect the circuit and internal interconnects from mechanical and chemical damage. Furthermore, any material layer that can perform a similar function can be an optional embodiment of this invention. Further, the passivation layer 60 can be a silicon nitride layer, a stack of silicon dioxide and silicon nitride layers, or any other single-layer or multi-layer material layer.

[0066] This utility model embodiment also provides a method for preparing a bidirectional ESD protection device, including:

[0067] Substrate 10 is provided; the thickness of substrate 10 ranges from 400 μm to 700 μm, and the resistivity ranges from [missing value]. ;

[0068] A semiconductor epitaxial layer 20 is formed on one side of the substrate 10; the thickness of the semiconductor epitaxial layer 20 ranges from 5 μm to 35 μm, and the resistivity ranges from [missing value]. ;

[0069] A pre-implantation oxide layer is formed on the side of the semiconductor epitaxial layer 20 away from the substrate 10; the formation temperature range of the pre-implantation oxide layer is... The formation time can be 25 minutes, and the thickness of the oxide layer before injection can be 0.05 μm;

[0070] P element is implanted on the side of the semiconductor epitaxial layer 20 away from the substrate 10 and then annealed to form a doped region 22; wherein the implantation dose of P element is in the range of 1E15cm. -3 ~1E16cm -3 The energy range is 80 KeV, and the annealing temperature range is [missing information]. The annealing time can be 30 minutes;

[0071] A sacrificial oxide layer is formed on the surface of the doped region 22 away from the substrate 10; TEOS can be deposited by LPCVD at a temperature of 720℃ / 5H with a thickness of 0.8um.

[0072] The first surface 201 of the semiconductor epitaxial layer 20 is etched to form an isolation trench 40, and an isolation layer 401 is formed in the isolation trench 40; wherein, the depth of the isolation trench 40 is 5um to 30um, and the angle between the isolation trench 40 and the wafer surface is 85° to 90°.

[0073] A metal layer is formed on the first surface 201 of the semiconductor epitaxial layer 20; wherein the thickness of the metal layer can be 4.5 μm, the temperature range of metal sputtering or evaporation is 230℃-380℃, and the power range is 8kW~15kW.

[0074] The metal layer is etched to form the first electrode 31 and the second electrode 32; the metal layer can be etched by a wet method using a mixture of phosphoric acid, nitric acid and acetic acid to form the first electrode 31 and the second electrode 32; the etching time range is 500s-600s, and the temperature range is 45℃-60℃.

[0075] A passivation layer 60 is formed on the side of the first electrode 31 and the second electrode 32 away from the substrate 10; the passivation layer 60 can be formed by depositing SiO2 and SiN by PECVD process, and the thickness of the passivation layer 60 can be 0.9 μm.

[0076] The substrate 10 is thinned from the back side (the surface of the substrate 10 away from the semiconductor epitaxial layer 20); the thickness of the thinned substrate 10 ranges from 90um to 200um.

[0077] This utility model embodiment also provides an electronic device, including the bidirectional ESD protection device described in any embodiment of this utility model.

[0078] The electronic devices may be, but are not limited to: portable communication devices such as mobile phones, tablets, and smartwatches, with bidirectional ESD protection devices used to protect their USB-C interfaces, display interfaces, side buttons, headphone jacks, etc.; computers and servers: bidirectional ESD protection devices used to protect Ethernet ports, HDMI / DisplayPort interfaces, memory module interfaces, etc.; automotive electronic products: bidirectional ESD protection devices used to protect vehicle networks (such as CAN bus), infotainment system interfaces, sensor interfaces, etc.; industrial control systems: bidirectional ESD protection devices used to protect fieldbus interfaces, I / O modules, etc.

[0079] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A bidirectional ESD protection device, characterized in that, include: Substrate; A semiconductor epitaxial layer is located on one side of the substrate; the semiconductor epitaxial layer includes a first surface and a second surface disposed opposite to each other, the first surface being the surface of the semiconductor epitaxial layer away from the substrate; the semiconductor epitaxial layer includes a first doped region and a second doped region of the same conductivity type, both located on the first surface; wherein the first doped region has a different conductivity type than the semiconductor epitaxial layer; the substrate has a different conductivity type than the semiconductor epitaxial layer; At least one isolation trench, the at least one isolation trench extending downward from a first surface located between the first doped region and the second doped region into the substrate; The first electrode is in contact with the first doped region; The second electrode is in contact with the second doped region.

2. The bidirectional ESD protection device according to claim 1, characterized in that, The first electrode is electrically connected to the signal port to be protected, and the second electrode is grounded; or, the second electrode is connected to the signal port to be protected, and the first electrode is grounded. The substrate, the first doped region, and the second doped region are all N-type; the semiconductor epitaxial layer is P-type.

3. The bidirectional ESD protection device according to claim 1, characterized in that, The angle between the extension direction of the isolation trench and the direction perpendicular to the substrate is greater than or equal to 0° and less than or equal to 5°.

4. The bidirectional ESD protection device according to claim 1, characterized in that, It also includes an isolation layer located in the isolation trench.

5. The bidirectional ESD protection device according to claim 1, characterized in that, It also includes a dielectric layer located on the first surface of the semiconductor epitaxial layer; The dielectric layer includes a first opening and a second opening; wherein the first opening exposes the first doped region, and the second opening exposes the second doped region; the first electrode contacts the first doped region through the first opening, and the second electrode contacts the first doped region through the second opening.

6. The bidirectional ESD protection device according to claim 1, characterized in that, The at least one isolation trench includes: a first isolation trench located on opposite sides of the first doped region and a second isolation trench located on opposite sides of the second doped region.

7. The bidirectional ESD protection device according to claim 1, characterized in that, The depth of the isolation trench ranges from 5µm to 30µm; The thickness of the semiconductor epitaxial layer ranges from 5µm to 35µm; The thickness of the substrate ranges from 90µm to 200µm.

8. The bidirectional ESD protection device according to claim 7, characterized in that, The resistivity of the substrate is in the range of ; The resistivity range of the semiconductor epitaxial layer is: .

9. The bidirectional ESD protection device according to claim 1, characterized in that, Also includes: A passivation layer is located on the side of the first electrode away from the semiconductor epitaxial layer, on the side of the second electrode away from the semiconductor epitaxial layer, and between the first electrode and the second electrode.

10. An electronic device, characterized in that, Includes the bidirectional ESD protection device as described in any one of claims 1 to 9.

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