Battery sheet, photovoltaic module and photovoltaic system

Abstract

The utility model discloses a kind of battery piece photovoltaic module and photovoltaic system, it is related to photovoltaic cell technical field;Battery piece includes oppositely arranged front and back surface;Front is provided with emitter layer on substrate;Front and back surface are provided with n grid line area and n-1 interval area, n≥2;Any two adjacent grid line area is provided with an interval area;The conductive hole penetrates the front and the back surface;The conductive hole and the groove partially overlap or are completely separated;When the conductive hole and the groove partially overlap, the conductive hole partially extends into the groove;When the conductive hole and the groove are completely separated, the minimum edge spacing between the conductive hole and the groove is 0-100 µm.The utility model realizes the internal partial interconnection of battery piece without cutting battery piece, effectively reduces the cost of half piece or multiple photovoltaic module and improves the power of photovoltaic module.

Description

Technical Field

[0001] This utility model relates to the field of photovoltaic cell technology, and in particular to a cell, a photovoltaic module and a photovoltaic system. Background Technology

[0002] The application of half-cell or multi-cell cell and module technology can improve module output power, reduce internal circuit losses, increase packaging efficiency, and lower module operating temperature, thereby reducing the risk of hot spots. Simultaneously, half-cell or multi-cell modules offer better resistance to shading than conventional modules. Half-cell or multi-cell technology can reduce shading area, improve optical utilization, and reduce electrical losses, further enhancing module power.

[0003] In existing technologies, a laser scribing machine is mainly used to cut a whole photovoltaic cell into half cells or multiple cells (three-cell or four-cell cells). Then, a passivation machine is used to passivate the damaged sides of the cut half or multiple cells. After passivation, the cells are then wired and stacked to form a photovoltaic module with half cells or a photovoltaic module with multiple cells through the module process.

[0004] Cutting a whole cell into half or multiple slices requires additional laser scribing equipment, and also results in cell fragmentation and loss, increasing costs. Passivating the damaged sides of the cut half or multiple slices requires ALD passivation or other physical methods to prepare alumina passivation films, which increases the need for side passivation equipment and its supporting equipment, and also results in cell fragmentation and loss, further increasing costs and making the industrialization of this technology difficult. Summary of the Invention

[0005] This invention provides a solar cell and its fabrication method, a photovoltaic module, and a photovoltaic system. The solar cell structure provided by this invention achieves half-cell or multi-cell effects without cutting the solar cell. Compared with traditional solar cell cutting processes for achieving half-cell or multi-cell effects, this invention effectively reduces the fabrication cost of the solar cell and photovoltaic module, while also increasing the power output of the photovoltaic module.

[0006] The first aspect of this utility model provides a battery cell, the battery cell including a front side and a back side disposed opposite to each other; the front side is provided with an emitter layer on a substrate; both the front side and the back side are provided with n grid line regions and n-1 interval regions, where n≥2; an interval region is provided between any two adjacent grid line regions; the orthographic projection of the center line of the interval region on the front side onto the back side coincides with the center line of the interval region on the back side. Each of the grid lines is provided with a main grid line and a secondary grid line that are perpendicular to each other. The main grid line on the front side extends in the same direction as the main grid line on the back side, and the secondary grid line on the front side extends in the same direction as the secondary grid line on the back side. A slot extending along the subgate line is provided in the spacing area of ​​each front side, and the bottom of the slot penetrates the emitter layer to form an isolation area; A conductive hole is provided in the interval area of ​​each of the front sides, and the conductive hole extends through the front side and the back side; The conductive hole may overlap with or completely separate from the groove; when the conductive hole overlaps with the groove, the conductive hole extends into the groove; when the conductive hole completely separates from the groove, the minimum edge distance between the conductive hole and the groove is 0-100µm.

[0007] The second aspect of this utility model provides a photovoltaic module comprising the solar cells provided in the first aspect of this utility model.

[0008] Optionally, the photovoltaic module also includes a solder strip, one end of which is connected to the main grid line on the front side of the cell, and the other end of which is connected to the main grid line on the back side of the adjacent cell.

[0009] The third aspect of this utility model provides a photovoltaic system comprising the photovoltaic module provided in the second aspect of this utility model.

[0010] This invention achieves internal interconnection of solar cells by creating isolation grooves that penetrate the emitter layer on the front side of the solar cell, and then connecting the grid areas separated by the isolation grooves using conductive holes and subsequent solder ribbons. This allows for the fabrication of half-cell or multi-cell photovoltaic modules without the need for cell cutting, effectively reducing the cost of such modules while increasing their power output. Attached Figure Description

[0011] The above and / or additional aspects and advantages of this utility model will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 A front view of an embodiment of the battery cell of this utility model is shown; Figure 2 It shows Figure 1 A schematic diagram of the back side of the battery cell in the illustrated embodiment; Figure 3 It shows Figure 1 A partial cross-sectional view of the battery cell in the embodiment shown; Figure 4 A front view of another embodiment of the battery cell of this utility model is shown; Figure 5 It shows Figure 4 A schematic diagram of the back side of the battery cell in the illustrated embodiment; Figure 6 It shows Figure 4 A partial cross-sectional view of the battery cell in the embodiment shown; Figure 7 A front view diagram of yet another embodiment of the battery cell of this utility model is shown; Figure 8 It shows Figure 7 A schematic diagram of the back side of the battery cell in the illustrated embodiment; Figure 9 A front view diagram of yet another embodiment of the battery cell of this utility model is shown; Figure 10 It shows Figure 9 Enlarged view of region C in the middle; Figure 11 It shows Figure 9 Enlarged view of region D in the middle; Figure 12 It shows Figure 9 Enlarged view of region E in the middle; Figure 13 It shows Figure 9 A schematic diagram of the back side of the battery cell in the illustrated embodiment; Figure 14 It shows Figure 13 Enlarged view of region F in the middle; Figure 15 It shows Figure 13 Enlarged view of region G in the middle; Figure 16 It shows Figure 13 Enlarged view of region H in the middle; Figure 17 A partial front view of an embodiment of the photovoltaic module of this utility model is shown; Figure 18 It shows Figure 17 A partial rear view of the photovoltaic module in the illustrated embodiment; Figure 19 It shows Figure 17 A partial side view of the photovoltaic module in the illustrated embodiment; Figure 20 A front view of an embodiment of the battery cell of this utility model is shown; Figure 21 It shows Figure 20 A schematic diagram of the back side of the battery cell in the illustrated embodiment; Figure 22 It shows Figure 20 A partial cross-sectional view of the battery cell in the embodiment shown.

[0012] Figure label: 1-Battery cell; 2-Soldering strip; 10 - Front side of the solar cell; 100 - Substrate; 101 - Front side grid line area; 1011 - Front side main grid line; 10111 - First grid line; 1012 - Front side sub-grid line; 1013 - Front side harpoon line; 1014 - Front side pad; 102 - Front side spacer area; 1021 - Groove; 1022 - Conductive via; 103 - Front side film layer; 20 - Back side of the solar cell; 201 - Grid line area on the back side; 2011 - Main grid line on the back side; 20111 - Second grid line; 2012 - Sub-grid line on the back side; 2013 - Harpoon line on the back side; 2014 - Pad on the back side; 202 - Spacer area on the back side; 203 - Film layer on the back side. Detailed Implementation

[0013] The embodiments of this utility model are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this utility model, and should not be construed as limiting this utility model.

[0014] The following disclosure provides numerous different embodiments or examples for implementing various structures of the present invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, examples of various specific processes and materials are provided in this invention; however, those skilled in the art will recognize the applicability of other processes and / or the use of other materials.

[0015] The first aspect of this utility model provides a battery cell that can achieve a half-cell or multi-cell battery structure without cutting the battery cell; such as Figure 1-3 , Figure 20-22 As shown, the battery cell 1 provided by this utility model includes a front side 10 and a back side 20 disposed opposite to each other; the front side 10 has an emitter layer disposed on a substrate 100.

[0016] Currently, photovoltaic cells can be classified into P-type and N-type cells based on the conductivity type of the substrate. P-type cells use P-type silicon wafers as substrates, such as P-type monocrystalline silicon wafers or P-type polycrystalline silicon wafers. P-type cells are mainly PERC cells, where the emitter layer is an n+ emitter layer, a doped layer formed by doping with group 5 elements, used to collect photogenerated electrons. For example, it can be a phosphorus-doped layer, i.e., a phosphorus emitter layer, and the emitter layer is located on the front side of the substrate. N-type cells include TOPCon cells, HJT cells, and IBC cells. N-type cells use N-type silicon wafers as substrates, such as N-type monocrystalline silicon wafers or N-type polycrystalline silicon wafers. N-type cells are mainly TOPCon cells, where the emitter layer is a p+ emitter layer, a doped layer formed by doping with group 3 elements, used to collect photogenerated holes. For example, it can be a boron-doped layer, i.e., a boron emitter layer.

[0017] In one specific embodiment, the solar cell is a PERC solar cell, with an anti-reflection layer, an n+ emitter layer and a front electrode on the front side; and a passivation layer, a partial back contact layer and a back electrode on the back side.

[0018] In one specific embodiment, the solar cell is a TOPCon solar cell, and a tunneling layer is provided on the back of the solar cell. The tunneling layer includes at least one tunneling oxide layer and at least one doped polycrystalline silicon layer. For example, it can be formed by combining one tunneling oxide layer and one doped polycrystalline silicon layer, or by combining one tunneling oxide layer and two doped polycrystalline silicon layers, or by stacking four layers: one tunneling oxide layer, one doped polycrystalline silicon layer, one tunneling oxide layer, and one doped polycrystalline silicon layer. This invention does not limit the number of tunneling oxide layers and the stacking order of doped polycrystalline silicon layers in the tunneling layer.

[0019] In a more specific embodiment, the solar cell is a TOPCon solar cell, with a p+ emitter layer, an aluminum oxide passivation layer, an anti-reflection layer and a front electrode disposed on the front side; and a tunneling layer, an anti-reflection layer and a back electrode disposed on the back side.

[0020] Both the front side 10 and the back side 20 of the battery cell 1 are provided with n grid line areas and n-1 interval areas, where n≥2; for example, they can be 2, 3, 4, 5, or 6. An interval area is provided between any two adjacent grid line areas; the interval areas separate adjacent grid lines. The orthographic projection of the center line of the front interval area 102 onto the back side coincides with the center line of the back interval area 202; ensuring that the front interval area 102 and the back interval area 202 are in the same or nearly the same position. Figure 1As shown, two grid lines 101 and one spacer area 102 are provided on the front side 10 of the solar cell 1; two grid lines 201 and one spacer area 202 are provided on the back side 20 of the solar cell 1; the positions of the front spacer area 102 and the back spacer area 202 are almost the same in spatial position on the solar cell, and the orthographic projection of the center line of the front spacer area 102 onto the back side coincides with the center line of the back spacer area 102. For example... Figure 7 As shown, four grid lines 101 and three spacing areas 102 are provided on the front side 10 of the solar cell 1; four grid lines 201 and three spacing areas 202 are provided on the back side 20 of the solar cell 1; the positions of the three front spacing areas 102 and the three back spacing areas 202 are almost the same in the spatial position of the solar cell; the orthographic projection of the back side of each front spacing area coincides with one of the back spacing areas.

[0021] Each grid area is provided with mutually perpendicular main grid lines and sub-grid lines. The main grid line 1011 on the front side extends in the same direction as the main grid line 2011 on the back side 20, and the sub-grid line 1012 on the front side extends in the same direction as the sub-grid line 2012 on the back side. Through the current transmission of the sub-grid lines and the current collection of the main grid lines, the power generation of the subsequent photovoltaic modules is realized.

[0022] On the front side of the solar cell, a groove 1021 is provided along the direction of the sub-busbar 1012 within each front side spacing region 102, and the bottom of the groove 1021 penetrates the emitter layer to form an isolation region; such as Figure 1-2 As shown, a groove 1021 is provided in the front spacing area 102, but there is no groove 1021 in the back spacing area 202; the groove 1021 does not penetrate the front 10 and the back 20; as Figure 3 As shown, slot 1021 penetrates the emitter layer, forming an isolation region.

[0023] It is worth noting that since the trench only needs to penetrate the emitter layer, and the trench can be fabricated after the emitter layer is fabricated but before other film layers are fabricated, other film layers will form within the trench after its fabrication. For example: Figure 3 As shown, for Topcon solar cells, the front side 10 of solar cell 1 on the front side of substrate 100 includes an emitter layer, a passivation layer, a front antireflection layer and a front gate line arranged sequentially on the front side. At this time, the trench 1021 can penetrate all the film layers 103, that is, the front emitter layer, the passivation layer and the front antireflection layer; it can also penetrate only the emitter layer, and a passivation layer and an antireflection layer will be formed on the inner wall of the trench; it can also penetrate the emitter layer, form a passivation layer on the inner wall of the trench and clean off the antireflection layer.

[0024] A conductive hole 1022 is provided in each front-side interval 102, and the conductive hole 1022 penetrates the front-side 10 and the back-side 20; for example Figure 1-2As shown, a conductive hole 1022 is provided in the front spacing area 102, while there is no conductive hole 1022 in the back spacing area 202; the conductive hole 1022 penetrates both the front 10 and the back 20; as Figure 3 As shown, the conductive hole 1022 penetrates the front film layer 103 and the back film layer 203, which include the emitter layer. For example, for a Topcon solar cell, the front side of the cell has an emitter layer, a passivation layer, a front anti-reflection layer, and front grid lines sequentially disposed on the substrate; the back side of the cell has a tunneling layer, a back anti-reflection layer, and a back electrode sequentially disposed. Since the conductive hole 1022 needs to penetrate the front side 103 and the back side 203, and the conductive hole 1022 is located in the gap area where there are no grid lines, the conductive hole 1022 needs to penetrate the front emitter layer, passivation layer, and front anti-reflection layer, and penetrate the back tunneling layer and back anti-reflection layer before the conductive hole 1022 is fabricated. This invention does not limit the other films on the front side besides the emitter layer; the front side of the solar cell can contain any film layer other than the emitter layer. The back film layer is not limited; this is just an example for understanding.

[0025] It is understandable that, since the conductive vias 1022 are subsequently connected to the main grid lines of adjacent grid line areas on the front side 10 and the back side 20 via solder ribbons, the number of main grid lines 1011 on the front side of any grid line area is equal to the number of main grid lines 2011 on the back side of its adjacent grid line area, and the number of main grid lines 1011 is also equal to the number of conductive vias 1022. In other words, the number of main grid lines on the front side, the main grid lines on the back side, and the conductive vias in this invention must be equal.

[0026] The conductive hole may overlap or completely separate from the groove; when the conductive hole overlaps with the groove, the conductive hole extends into the groove; when the conductive hole completely separates from the groove, the minimum edge distance between the conductive hole and the groove is 0-100µm.

[0027] like Figure 1-3 As shown, the conductive hole and the groove partially overlap, that is, part of the conductive hole is inside the groove; in a specific embodiment, the center of the conductive hole may coincide with the central axis of the groove; in a specific embodiment, the center of the conductive hole may also have a certain distance from the central axis of the groove, the distance being greater than 0µm.

[0028] like Figure 20-22As shown, the conductive hole and the groove are completely separated, meaning the conductive hole is outside the groove. In an optional configuration, the conductive hole and the groove are completely separated, and the minimum edge spacing d between the conductive hole and the groove is 0-100µm; that is, the minimum distance d between the edge of the conductive hole near the groove and the edge of the groove near the conductive hole is 0-100 µm; for example, it can be 0µm, 0.1µm, 0.2µm, 0.5µm, 0.8µm, 1µm, 1.2µm, 1.5µm, 2µm, 2.5µm, 3µm, etc. µm, 4µm, 5µm, 6µm, 7µm, 8µm, 9µm, 10µm, 12µm, 15µm, 18µm, 20µm, 25µm, 30µm, 35µm, 40µm, 45µm, 50µm, 55µm, 60µm, 65µm, 70µm, 75µm, 80µm, 85µm, 90µm, 95µm, or 100µm; Excessive spacing increases the current transmission path between the conductive via and the gate area, increases series resistance, and reduces component power. It is worth noting that even when the minimum distance is 0µm, although the conductive via and the slot are close together, this invention is considered a completely separated case.

[0029] It is understood that in this utility model, the battery cells are divided into segments without cutting by means of the groove in the spacer area and the conductive hole. For the whole battery cell, when there is one spacer area, two segments are formed; when there are two spacer areas, three segments are formed.

[0030] This invention, without cutting or slicing, isolates the PN junctions of two adjacent gate regions 101 by the groove 1021 on the front side 10 after penetrating the emitter layer. Within these two adjacent gate regions, a main gate line 1011 on the front side of one gate region is connected to a conductive via 1022, and a main gate line 2011 on the back side of the other gate region is connected to the conductive via 1022. Since the groove 1021 isolates the adjacent gate regions 101, the internal resistance is reduced. Current collection between the two adjacent gate regions is achieved through the conductive via 1022. Therefore, half-cell or multi-cell photovoltaic modules can be fabricated without cutting the substrate 100. This invention effectively reduces the cost of half-cell or multi-cell photovoltaic modules and increases the power output of photovoltaic modules.

[0031] Optionally, such as Figure 4-16As shown, in the front region, the conductive via 1022 is connected to the main grid line 1011 of the grid line area 101 adjacent to the front 10 to form a first grid line 10111. In the back region, the conductive via 1022 is connected to the main grid line 2011 of the grid line area 201 adjacent to the back 20 to form a second grid line 20111. The orthographic projections of the first grid line 10111 and the second grid line 20111 on the front 10 are located on both sides of the spacing area 102. By setting the first grid line 10111 and the second grid line 20111, the reliability of the battery interconnection can be increased, the power loss caused by possible poor soldering of subsequent solder strips can be reduced, and the power generation capacity of the module can be further increased.

[0032] In one alternative approach, such as Figure 6-13 As shown, the structures at both ends of the main gate line are harpoon lines 1013; at least some of the sub-gate lines pass through the harpoon lines; In an alternative embodiment, pads are also provided on the main gate lines. For example, a front pad 1014 is designed on the front main gate line 1011, and a back pad 2014 is provided on the back main gate line 2011. This can further reduce contact resistance and enhance connection reliability.

[0033] It is worth noting that the fork wire and solder pad are conventional structures in photovoltaic cells in this field, and will not be described in detail here.

[0034] In one specific embodiment, the two ends of the main gate line are structured as harpoon lines 1013; at least a portion of the sub-gate lines pass through the harpoon lines 1013; one end of the first gate line is connected to the harpoon line, and the other end extends to and connects to the conductive hole; one end of the second gate line is connected to the harpoon line, and the other end extends to and connects to the conductive hole.

[0035] Specifically, such as Figure 9-12 As shown, the main grid line 1011 on the front side of the battery cell 1 has a harpoon wire 1013 structure at both ends, and a portion of the sub-grid line 1012 passes through the harpoon wire 1013 structure; at this time, the first grid line 10111 on the front side 10 of the battery cell 1, that is, the main grid line 1011 connected to the conductive hole 1022, and the main grid line 1011 connected to the harpoon wire 1013, pass through the harpoon wire 1013 and are connected to the conductive hole 1022. Figure 13-16As shown, the main grid line 2011 on the back side 20 of the battery cell 1 has a harpoon wire 2013 structure at both ends, and a portion of the sub-grid line 2012 passes through the harpoon wire 2013 structure. At this time, the second grid line 20111 on the back side 20 of the battery cell 1, that is, the main grid line 2011 connected to the conductive hole 1022, and the main grid line 2011 connected to the harpoon wire 2013, passes through the harpoon wire 2013 and is connected to the conductive hole 1022. The harpoon wire is a commonly used end structure of the main grid line in battery cells. In this utility model, the standard harpoon wire structure is used as the bus end and mechanical support point of the main grid. The main grid line (i.e., the first grid line and the second grid line) extending from the harpoon wire is connected to the conductive hole, realizing the electrical path connected to the conductive hole. Therefore, without changing the basic functions of the main grid body and the harpoon line, the first grid line and the second grid line are extended as part of the main grid line together with the harpoon line, ensuring low-loss current transmission from the sub-grid line to the main grid line, then to the harpoon line, then to the first grid line and the second grid line, and finally to the conductive hole, realizing the fabrication of photovoltaic modules without cutting the lower half and / or multiple slabs.

[0036] In some optional configurations, the width of the slot 1021 is 40-100µm; for example, it can be 40µm, 45µm, 50µm, 55µm, 60µm, 65µm, 70µm, 75µm, 80µm, 85µm, 90µm, 95µm, or 100µm. A slot width that is too narrow may result in incomplete isolation, while a width that is too wide will reduce the effective light-receiving area. This width range minimizes the occupation of the effective power generation area of ​​the solar cell while ensuring effective electrical isolation between adjacent grid areas (preventing leakage and crosstalk), thus balancing isolation effectiveness and power generation efficiency.

[0037] In some alternative methods, such as Figure 3 , 6 As shown in Figure 22, the bottom of the groove 1021 is cut into the substrate 100 of the solar cell 1, forming a cut-in portion with a depth of H, where H satisfies: 0.005mm ≤ H ≤ 0.015mm. Cutting the bottom of the groove 1021 into the silicon substrate 100 can completely remove any conductive paths that may exist on the surface (such as the emitter layer diffusion edge), enhance the reliability of the isolation region, ensure complete electrical isolation between adjacent gate line regions, and avoid potential leakage paths. If the depth is too shallow, the isolation may be incomplete; if it is too deep, it may increase the difficulty of the process and the risk of mechanical damage.

[0038] In some alternative configurations, a passivation layer is provided on the inner wall of the groove 1021. Providing a passivation layer on the inner wall of the groove can effectively passivate dangling bonds generated on the silicon surface during the grooving process, significantly reducing the surface recombination rate in the groove wall region and decreasing carrier loss in this region, thereby better achieving electrical isolation between adjacent gate line regions. Preferably, the passivation layer is an aluminum oxide layer; aluminum oxide passivation layers are commonly used in the fabrication of solar cells, which simplifies and facilitates the passivation process, promoting the fabrication of the solar cell structure of this invention and its large-scale production and application.

[0039] More preferably, the thickness of the passivation layer is 5-50 nm; for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. This thickness range can provide sufficiently high passivation quality. If it is too thin, the passivation effect may be insufficient, while if it is too thick, it will increase costs and processing time, and may cause problems such as stress.

[0040] In some alternative configurations, the diameter of the conductive via 1022 is 80-200µm; for example, it can be 80µm, 85µm, 90µm, 95µm, 100µm, 105µm, 110µm, 115µm, 120µm, 125µm, 130µm, 135µm, 140µm, 145µm, 150µm, 155µm, 160µm, 165µm, 170µm, 175µm, 180µm, 185µm, 190µm, 195µm, or 200µm. When the conductive hole and the groove partially overlap, the diameter of the conductive hole needs to be larger than the width of the groove. If the width of the groove is larger than the diameter of the conductive hole, conductive material may concentrate at the edge of the groove, causing voids inside the groove and at the junction of the conductive hole and the groove. Simultaneously, current may preferentially accumulate at the edge of the groove, affecting the filling effect of the conductive particles within the conductive hole and ultimately reducing conductivity. Furthermore, regardless of whether the conductive hole and the groove overlap, the diameter of the conductive hole must be controlled within a reasonable range. If the diameter of the conductive hole is too small, it will not only increase resistance and cause filling difficulties (such as insufficient slurry penetration), but may also affect conductivity due to insufficient conductive cross-sectional area. If the diameter is too large, it will increase the shading area of ​​the effective region of the solar cell and weaken its mechanical properties.

[0041] In some alternative embodiments, the conductive hole 1022 includes a through hole and a conductive material filled in the through hole; by filling the through hole with conductive material, a connection channel is formed through the cell, ensuring that the main grid line current in the front grid line area can be conducted to the main grid line in the adjacent grid line area on the back surface with high efficiency and low loss, thereby realizing internal current convergence.

[0042] Preferably, the conductive material comprises at least one conductive particle of silver, copper, or aluminum metal; silver, copper, and aluminum have high electrical conductivity, ensuring low series resistance of the conductive hole.

[0043] More preferably, the conductive material inside the conductive hole 1022 is silver conductive particles; silver has the highest conductivity, which can minimize the resistance loss of the conductive hole itself and optimize the current transmission efficiency.

[0044] In some alternative approaches, a passivation layer is provided on the inner wall of the via; depositing a passivation layer on the inner wall of the via can passivate the damage and dangling bonds generated on the silicon sidewalls by the drilling process, significantly reduce the surface recombination rate in the via wall region, reduce the loss of charge carriers in the transport path, and thus improve the electrical performance of the battery.

[0045] In one alternative embodiment, an emitter layer and a passivation layer are disposed on the inner wall of the via. Preferably, the emitter layer is a p+ emitter layer or an n+ emitter layer.

[0046] Preferably, the passivation layer is an aluminum oxide layer; the aluminum oxide passivation layer is a common passivation layer in the battery cell manufacturing process, which makes the passivation process simpler and more convenient, which is beneficial to the preparation of the battery cell structure of this utility model, as well as the large-scale production and application of the battery cell of this utility model.

[0047] More preferably, the thickness of the passivation layer is 5-50 nm; for example, it can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, or 50 nm. This thickness range can provide sufficiently high passivation quality. If it is too thin, the passivation effect may be insufficient, while if it is too thick, it will increase cost and processing time, and may cause stress problems.

[0048] The method for preparing the battery cell of this utility model includes the following steps: A substrate is selected, and through-holes are fabricated on the front side of the substrate; the through-holes are located within the spacing region of the solar cells; the through-holes penetrate both the front and back sides of the substrate. In this step, the substrate is a P-type silicon wafer or an N-type silicon wafer; through-holes are fabricated in the spacing region of the solar cells; the through-holes penetrate the front side and the back side of the substrate 100; Specifically, according to the preset gate area layout, the processing area is marked at the center line position of the front side spacing area, and a laser is used to prepare through holes, which penetrate the front side and the back side of the substrate 100. Through-holes can be fabricated using nanosecond or picosecond lasers; nanosecond lasers have wavelengths of 830-1064 nm and pulse widths of 1-100 ns; for example, pulse widths can be 1 ns, 2 ns, 3 ns, 4 ns, 5 ns, 6 ns, 7 ns, 8 ns, 9 ns, 10 ns, 11 ns, 12 ns, 13 ns, 14 ns, 15 ns, 16 ns, 17 ns, 18 ns, 19 ns, 20 ns, 25 ns, 30 ns, 35 ns, 40 ns, 45 ns, 50 ns, 60 ns, 70 ns, 80 ns, 90 ns, or 100 ns; the average power is 60-120 kJ / m². W; for example, it can be 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, 100W, 110W or 120W; the spot diameter is 130-300µm; for example, it can be 130µm, 135µm, 140µm, 145µm, 150µm, 155µm, 160µm, 165µm, 170µm, 175µm, 180µm, 185µm, 190µm, 195µm, 200µm, 210µm, 220µm, 230µm, 240µm, 250µm, 260µm, 270µm, 280µm, 290µm or 300µm. The wavelength of the picosecond laser is 532-1064nm; the pulse width is 5-50ps; for example, it can be 5ps, 6ps, 7ps, 8ps, 9ps, 10ps, 11ps, 12ps, 13ps, 14ps, 15ps, 16ps, 17ps, 18ps, 19ps, 20ps, 25ps, 30ps, 35ps, 40ps, 45ps or 50ps; the average power is 60-120W; for example, it can be 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, 100W, 110W or 120W; the spot diameter is 130-300µm. For example, it can be 130µm, 135µm, 140µm, 145µm, 150µm, 155µm, 160µm, 165µm, 170µm, 175µm, 180µm, 185µm, 190µm, 195µm, 200µm, 210µm, 220µm, 230µm, 240µm, 250µm, 260µm, 270µm, 280µm, 290µm, or 300µm.

[0049] Select a substrate, perform surface treatment on the front and / or back sides of the substrate, and prepare an emitter layer on the front side of the substrate; In this step, the P-type or N-type substrate undergoes surface treatment, such as texturing, to create a pyramidal textured surface. The emitter layer is either a p+ or n+ emitter layer. If the emitter layer is p+, it is a doped layer formed by a group III element, such as a boron-doped emitter layer. The boron emitter layer is prepared by forming a diffusion layer with a certain sheet resistance on the substrate surface using boron technology. This is mainly achieved by vaporizing a boron source (e.g., BBr3 or BCl3) in a tube furnace, followed by a series of chemical reactions to deposit the boron on the substrate surface, obtaining appropriate doping concentration, junction depth, and sheet resistance, thereby forming the boron diffusion layer. Boron diffusion is generally carried out in a low-pressure diffusion furnace, using a boron source, O2 as the reactant gas, and N2 as the carrier gas, reacting at a specific flow rate and temperature. If the emitter layer is an n+ emitter layer, it is a doped layer formed by group 5 elements, such as a phosphorus emitter layer formed by phosphorus doping. The phosphorus emitter layer is formed in a tube diffusion furnace by vaporizing a phosphorus source (such as POCl3 or P2O5) at high temperature and undergoing a chemical reaction, which is then deposited on the silicon wafer surface.

[0050] It is understandable that since the via is formed before the emitter layer is prepared, an emitter layer is also formed on the inner wall of the via. If the emitter layer inside the via is not cleaned subsequently, an emitter layer will be formed on the inner wall of the via. This invention does not limit whether an emitter layer exists inside the via.

[0051] It is understandable that for different solar cells, such as PERC solar cells, a front anti-reflection layer needs to be prepared before the emitter layer is fabricated; this invention does not limit whether there are other films between the front side of the substrate and the emitter layer.

[0052] A trench is fabricated on the front side of the substrate; the through-hole is disposed within the trench; the depth of the trench penetrates the emitter layer; In this step, after the emitter layer is prepared, a trench is prepared on the front side of the substrate; the trench is located in the spacing area of ​​the cell; the via is connected to the trench, the via is located in the trench, and the depth of the trench penetrates the emitter layer; the width of the trench is smaller than the diameter of the via.

[0053] The 1021 groove can be fabricated using a laser, such as a picosecond laser, specifically a green picosecond laser. The wavelength of the green picosecond laser is 532 nm. Other wavelengths can also be selected, such as lasers in the range of 532 nm to 1064 nm, with a pulse width of 5-20 ps; for example, 5 ps, 6 ps, 7 ps, 8 ps, 9 ps, 10 ps, ​​11 ps, 12 ps, 13 ps, 14 ps, etc. ps, 15ps, 16ps, 17ps, 18ps, 19ps, or 20ps; average power is 60-120W; for example, it can be 60W, 65W, 70W, 75W, 80W, 85W, 90W, 95W, 100W, 110W, or 120W; spot size is 40-80µm; for example, it can be 40µm, 45µm, 50µm, 55µm, 60µm, 65µm, 70µm, 75µm, or 80µm.

[0054] Specifically, after the emitter layer is fabricated, the processing area is marked at the center line of the front-side spacing region according to the preset gate line layout. A laser is used to create grooves along the sub-gate line direction. The width of the groove is 40-100 μm; the length of the groove can extend from one edge of the sub-gate line to the other; and the depth of the groove needs to penetrate the emitter layer. Preferably, as shown below... Figure 3 and Figure 6 As shown, the depth of the trench can penetrate the emitter layer and cut into the substrate.

[0055] It is understood that for different types of batteries, there may be other films between the substrate and the emitter layer. For example, in PERC cells, there is also a front anti-reflective layer between the substrate and the emitter layer. In this invention, the depth of the groove may or may not penetrate the front anti-reflective layer; this invention does not impose any limitation. Preferably, the depth of the groove is best to penetrate the anti-reflective layer and cut into the substrate.

[0056] To prepare other membrane layers.

[0057] In this step, the PSG layer (phosphosilicate glass layer) or BSG layer (borosilicate glass layer) on the back of the substrate needs to be removed first, usually by using hydrofluoric acid; or, alkaline polishing can be performed, which mainly uses potassium hydroxide aqueous solution to form a base on the surface of the substrate, followed by the preparation of other film layers.

[0058] In a specific embodiment, to fabricate a TOPCon battery, the fabrication of other films includes the fabrication of a back tunneling layer, a front alumina passivation layer, a front antireflection layer, and a back antireflection layer.

[0059] The tunneling layer can be prepared by LPCVD or PECVD. LPCVD involves passing oxygen at high temperature under low pressure, where the oxygen reacts with silicon to produce silicon oxide, forming an oxide layer. Then, silane is passed through at high temperature, where it thermally decomposes into silicon and hydrogen, forming an amorphous silicon layer. Subsequently, phosphorus diffusion is used to transform the amorphous silicon layer into a doped polycrystalline silicon layer, thus forming the tunneling layer.

[0060] The passivation layer is generally an aluminum oxide layer, which is mainly deposited using the ALD method. Trimethylaluminum (TMA) is used as the aluminum source and vaporized water (H2O) or gaseous oxygen (O2) is used as the oxygen (O) source. Two or more chemical vapor precursors are alternately introduced into the reaction chamber and react on the substrate surface to form an aluminum oxide thin film.

[0061] The front and back antireflection layers are generally prepared using PECVD. The preparation of the antireflection layer is a conventional process for preparing solar cell 1, and will not be described in detail here.

[0062] In another specific embodiment, to prepare a PERC cell, the preparation of other films includes the preparation of a back passivation layer and a partial back contact layer.

[0063] The printing process includes: filling the through-holes with paste; and printing the main and sub-grid lines on the front and back sides.

[0064] The printing process includes: filling the through-holes with paste; and printing the main grid lines and sub-grid lines on the front and back sides.

[0065] In this step, after the front and back film layers are prepared, the paste is printed.

[0066] Preferably, before printing, the groove or the groove and the through hole are subjected to wet treatment; since a passivation layer and other films (such as an anti-reflection layer) are formed in the groove and the through hole in the previous step, although the passivation layer and the anti-reflection layer are not conductive and will not affect the isolation performance of the groove, the isolation performance of the groove and the conductivity performance of the conductive hole can be better achieved by removing the anti-reflection layer through wet treatment.

[0067] In one alternative approach, the wet process first employs alkali treatment, followed by rinsing with pure water and then acid treatment; preferably, the alkali solution is NaOH solution and the acid is HF solution.

[0068] In one specific embodiment, the battery cells can first pass through an alkaline bath, where the solution is a NaOH solution with a small amount of additives, including at least one of corrosion inhibitors, surfactants, chelating agents, and defoamers; the solution temperature is 60-80 degrees Celsius, and the processing time is 4-5 minutes. After passing through a water washing bath, the cells then pass through an acid washing bath, where the solution is an HF acid solution formed by pure water and HF. This process prepares the battery cells for printing.

[0069] In one alternative approach, after the wet processing is completed, the trenches and vias can be treated again with a passivation layer to ensure that the PN junction is not located within the trenches and vias, thus preventing leakage. Specifically, a silicon oxide slurry can be coated within the trenches and vias to form a passivation layer of 50-200 nm. For example, a casting coating process can be used, employing precision slot coating equipment, combined with a low-viscosity slurry and a micro-tension controlled casting coating process to achieve the passivation layer coating.

[0070] After the grooves and through-holes are processed, conductive material is filled into the through-holes. In one optional method, a paste can be first used to fill the through-holes, followed by the printing of paste for the back main grid lines, back sub-grid lines, front main grid lines, and front sub-grid lines. Subsequently, a curing process (e.g., laser sintering) is used to solidify the paste within the through-holes into a conductive material, fixing the main and sub-grid lines within the grid line area. In another optional method, the paste can be filled into the through-holes during the fabrication of the back main grid lines, back sub-grid lines, or front main grid lines and front sub-grid lines. This allows for simultaneous completion of conductive hole filling and grid line printing using the same paste, reducing process changeover time. Furthermore, the conductive holes and main grid lines are integrally formed using the same material, eliminating interfacial contact resistance and reducing current transmission losses.

[0071] Another method for preparing the battery cell of this utility model includes the following steps: Select a substrate, perform surface treatment on the front and / or back sides of the substrate, and prepare an emitter layer on the front side of the substrate; In this step, the substrate is a P-type or N-type silicon wafer. The substrate undergoes surface treatment, such as texturing, to create a pyramidal textured surface. The emitter layer is either a p+ or n+ emitter layer. If the emitter layer is p+, it is a doped layer formed by a group III element, such as a boron-doped emitter layer. The boron emitter layer is prepared by forming a diffusion layer with a certain sheet resistance on the substrate surface using boron technology. This is mainly achieved by vaporizing a boron source (e.g., BBr3 or BCl3) in a tube furnace, followed by a series of chemical reactions to deposit the boron on the substrate surface, obtaining appropriate doping concentration, junction depth, and sheet resistance, thus forming the boron diffusion layer. Boron diffusion is generally carried out in a low-pressure diffusion furnace, using a boron source, O2 as the reactant gas, and N2 as the carrier gas, reacting at specific flow rates and temperatures. If the emitter layer is an n+ emitter layer, it is a doped layer formed by group 5 elements, such as a phosphorus emitter layer formed by phosphorus doping. The phosphorus emitter layer is formed in a tube diffusion furnace by vaporizing a phosphorus source (such as POCl3 or P2O5) at high temperature and undergoing a chemical reaction, which is then deposited on the silicon wafer surface.

[0072] Grooves and vias are fabricated on the front side of the substrate; the grooves and vias are positioned within the spacer region of the solar cell; the depth of the grooves penetrates the emitter layer; the vias penetrate the front side and the back side of the substrate 100. In this step, after the emitter layer is fabricated, trenches and vias are fabricated on the front side of the substrate. The trenches 1021 and vias can be fabricated using a laser; for example, a picosecond laser can be used to fabricate the trenches. Alternatively, a nanosecond or picosecond laser can be used to fabricate the vias.

[0073] Specifically, after fabricating the emitter layer, according to the preset gate line layout, the processing area is marked at the center line position of the front-side spacing area. A laser is used to create a groove along the sub-gate line direction, with a groove width of 40-100 μm. The groove length can extend from one edge of the sub-gate line to the other edge, and the groove depth needs to penetrate the emitter layer. Preferably, the groove depth can penetrate the emitter layer and cut into the substrate. After fabricating the groove, vias are fabricated at the intersection of the main gate line extension direction and the groove. The vias are fabricated using a laser and extend through both the front and back sides.

[0074] Specifically, the width of the groove is smaller than the diameter of the through hole.

[0075] It is understandable that since the via is formed after the emitter layer is prepared, there will be no emitter layer on the inner wall of the via at this time.

[0076] To prepare other films; In this step, the PSG layer (phosphosilicate glass layer) or BSG layer (borosilicate glass layer) on the back of the substrate needs to be removed first, usually by using hydrofluoric acid; or, alkaline polishing can be performed, which mainly uses potassium hydroxide aqueous solution to form a base on the surface of the substrate, followed by the preparation of other film layers.

[0077] In a specific embodiment, to fabricate a TOPCon battery, the fabrication of other films includes the fabrication of a back tunneling layer, a front alumina passivation layer, a front antireflection layer, and a back antireflection layer.

[0078] In another specific embodiment, to prepare a PERC cell, the preparation of other films includes the preparation of a back passivation layer and a partial back contact layer.

[0079] The printing process includes: filling the through-holes with paste; and printing the main and sub-grid lines on the front and back sides.

[0080] In this step, after the front and back film layers are prepared, the paste is printed.

[0081] In one alternative approach, the grooves or the grooves and through-holes are wet-treated prior to printing preparation.

[0082] In one alternative approach, the wet process first employs an alkaline treatment, followed by rinsing with pure water and then an acid treatment; preferably, the alkaline solution is a NaOH solution and the acid is an HF solution.

[0083] In one specific embodiment, the battery cells can first pass through an alkaline bath, where the solution is a NaOH solution with a small amount of additives, including at least one of corrosion inhibitors, surfactants, chelating agents, and defoamers; the solution temperature is 60-80 degrees Celsius, and the processing time is 4-5 minutes. After passing through a water washing bath, the cells then pass through an acid washing bath, where the solution is an HF acid solution formed by pure water and HF. This process prepares the battery cells for printing.

[0084] In one alternative approach, after the wet processing is completed, the trenches and vias can be treated again with a passivation layer to ensure that the PN junction is not located within the trenches and vias, thus preventing leakage. Specifically, a silicon oxide slurry can be coated within the trenches and vias to form a passivation layer of 50-200 nm. For example, a casting coating process can be used, employing precision slot coating equipment, combined with a low-viscosity slurry and a micro-tension controlled casting coating process to achieve the passivation layer coating.

[0085] After the grooves and through-holes are processed, conductive material is filled into the through-holes. In one optional method, a paste can be first used to fill the through-holes, followed by the printing of paste for the back main grid lines, back sub-grid lines, front main grid lines, and front sub-grid lines. Subsequently, a curing process (e.g., laser sintering) is used to solidify the paste within the through-holes into a conductive material, fixing the main and sub-grid lines within the grid line area. In another optional method, the paste can be filled into the through-holes during the fabrication of the back main grid lines, back sub-grid lines, or front main grid lines and front sub-grid lines. This allows for simultaneous completion of conductive hole filling and grid line printing using the same paste, reducing process changeover time. Furthermore, the conductive holes and main grid lines are integrally formed using the same material, eliminating interfacial contact resistance and reducing current transmission losses.

[0086] The second aspect of this utility model provides a photovoltaic module comprising a solar cell of the first aspect of this utility model or a solar cell prepared by the method of the first aspect of this utility model.

[0087] In one alternative approach, such as Figure 17-19 As shown, the photovoltaic module is formed by connecting solar cells 1 and solder ribbons 2. One end of the solder ribbon 2 is connected to the front main busbar 1011 of the solar cell 1, and the other end is connected to the back main busbar 2011 of the adjacent solar cell 1. Thus, the front main busbar 1011 and the adjacent back main busbar 2011 are connected by the solder ribbon 2, realizing series connection inside the cell.

[0088] It is understandable that if there is a first grid line on the front main grid line and a second grid line on the back main grid line, the solder ribbon will cover the first grid line and the second grid line. This can reduce the proportion of poor solder joints, reduce the power loss caused by poor solder joints, increase the reliability of cell interconnection, and increase the power generation of the module.

[0089] The third aspect of this utility model provides a photovoltaic system comprising the photovoltaic module provided in the second aspect of this utility model.

[0090] The following describes in detail, with several specific embodiments, the solar cell disclosed in the first aspect and the photovoltaic module of the second aspect. It is to be understood that the following description is merely illustrative and not intended to limit the specific scope of the invention. Example 1

[0091] Referring to Figure 9-16, 72 N-type single-crystal silicon wafers were selected as substrate 100. The resistivity of substrate 100 was 0.5~2.5Ω·cm, the size of substrate 100 was 182.2mm×183.75mm, and the thickness was 130µm. The N-type single-crystal silicon wafers were then subjected to alkaline texturing treatment using NaOH solution. Boron diffusion is performed on the front side 10 of substrate 100 to obtain a boron emitter layer.

[0092] A green picosecond laser with a wavelength of 532 nm, a pulse width of 10 ps, ​​an average power of 60 W, and a spot size of 40 µm was used to create a 40 µm wide slot 1021 on the front side 10 of the substrate 100. An infrared nanosecond laser with a wavelength of 1064 nm, a pulse width of 20 ns, an average power of 100 W, and a spot diameter of 130 µm was used to create a 200 µm diameter via at the intersection of the main grid line 1011 and the slot 1021 on the front side 10 of the substrate 100. After removing the 20BSG layer on the back side and polishing the back side, a tunneling layer was prepared by LPCVD. After cleaning and removing the wrap-around plating, a passivation layer of aluminum oxide on the front side, an anti-reflection layer on the front side, and an anti-reflection layer on the back side were prepared. The wet process is used to treat the cells and holes. The process is as follows: the cells are first passed through an alkaline tank, where the solution is a NaOH solution with a small amount of additives, including at least one of corrosion inhibitors, surfactants, chelating agents, and defoamers. The solution temperature is 73 degrees Celsius, and the treatment time is 4.5 minutes. The cells are then passed through a water washing tank and then through an acid washing tank, where the solution is an HF acid solution formed by pure water and HF. Subsequently, silver paste is used to fill the through-holes and print the paste for the back main grid line, back sub-grid line, front main grid line, and front sub-grid line. The conductive holes, main grid lines, and sub-grid lines are then obtained by Leco laser sintering.

[0093] Specifically, the front side 10 and the back side 20 of the battery cell 1 are provided with two grid lines and one spacing area; the spacing area is located between the two grid lines, and the orthographic projection of the center line of the spacing area 102 on the front side coincides with the center line of the spacing area 202 on the back side. Each grid area is provided with mutually perpendicular main grid lines and sub-grid lines. The extension direction of the main grid line 1011 on the front side is consistent with that of the main grid line 2011 on the back side, and the extension direction of the sub-grid line 1012 on the front side is consistent with that of the sub-grid line 2012 on the back side. The two ends of the main grid lines on the front and back sides are provided with harpoon lines, and at least part of the sub-grid line 1012 passes through the harpoon lines. In the solar cell 1, two grid lines and one spacer area between them form a small solar cell unit. In this small solar cell unit, a groove 1021 extends along the direction of the sub-grid line 1012 within the spacer area 102 on the front side. The length of the groove 1021 extends from one edge of the sub-grid line 1012 to the corresponding edge on the other side. The width of the groove 1021 is 40µm. The bottom of the groove 1021 cuts into the substrate 100 of the solar cell 1, forming a cut-in portion with a depth of H, where H is equal to 0.015mm. A conductive hole 1022 is provided in the groove 1021, and the conductive hole 1022 penetrates the front side 10 and the back side 20. The conductive hole 1022 is connected to the main grid line 1011 of the grid line area 101 on the side adjacent to the front side 10 to form a first grid line 10111. The conductive hole 1022 is connected to the main grid line 2011 of the grid line area 201 on the side adjacent to the back side 20 to form a second grid line 20111. The orthographic projections of the first grid line and the second grid line on the front side 10 are located on both sides of the interval area 102.

[0094] The 72-cell solar cells 1 are arranged in 6 rows and 12 columns (12 cells per row, 6 rows in total) using solder ribbons 2. The solar cells 1 are connected to each other using solder ribbons 2. One end of the solder ribbon 2 is connected to the main grid line 1011 on the front side of the solar cell 1, and the other end is connected to the main grid line 2011 on the back side of the adjacent solar cell 1. In this way, the main grid line 1011 on the front side and the main grid line 2011 on the adjacent back side are connected by solder ribbons 2, realizing series connection inside the cell.

[0095] The power of the photovoltaic module was measured using the Shaanxi Zhongsen GIV-50A solar cell module tester. Example 2

[0096] The difference from Example 1 is that, referring to Figure 7-8 As shown, four grid lines and three spacer areas are provided on the front side 10 of the solar cell 1; each spacer area has a groove and a conductive hole. Example 3

[0097] The difference from Embodiment 1 is that the first grid line 10111 is not provided on the front side of the battery cell, and the second grid line 20111 is not provided on the back side of the battery cell. Example 4

[0098] The difference from Example 1 is that, referring to Figure 20-22 As shown, the conductive hole 1022 is completely separated from the groove 1021; the minimum edge distance d between the conductive hole 1022 and the groove 1021 is 2µm.

[0099] The main gate line 1011 of the gate line area 101 on the side of the conductive hole 1022 adjacent to the front side 10 does not form a first gate line 10111, and the main gate line 2011 of the gate line area 201 on the side of the conductive hole 1022 adjacent to the back side 20 does not form a second gate line 20111.

[0100] Comparative Example 1 The size, film layer and grid line shape of the battery cell of Comparative Example 1 are the same as those of Example 1. The difference from Example 1 is that the battery cell 1 of Comparative Example 1 does not have grooves and through holes in the spacer area; the battery cell of Comparative Example 1 does not include the first grid line and the second grid line.

[0101] Measurements using a solar cell module tester show that, compared to Comparative Example 1, Example 1 saw a power increase of 6W; Example 2 saw a power increase of 15W; Example 3 saw a power increase of 4.5W; and Example 4 saw a power increase of 5W. This demonstrates that the present invention, through the design of slots and conductive holes, achieves internal segmentation of the solar cell 1 without requiring cutting, effectively improving the power output of the photovoltaic module.

[0102] In the description of this utility model, it should be understood that the terms "center," "longitudinal," "transverse," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., indicating the orientation or positional relationship shown in the accompanying drawings, are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, features defined with "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this utility model, unless otherwise stated, "a plurality of" means two or more.

[0103] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0104] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0105] Although embodiments of the present invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A battery cell, characterized in that, The solar cell includes a front side and a back side arranged opposite to each other; the front side has an emitter layer on a substrate; both the front side and the back side have n grid line regions and n-1 spacer regions, where n≥2; a spacer region is provided between any two adjacent grid line regions; the orthographic projection of the center line of the spacer region on the front side onto the back side coincides with the center line of the spacer region on the back side. Each of the grid lines is provided with a main grid line and a secondary grid line that are perpendicular to each other. The main grid line on the front side extends in the same direction as the main grid line on the back side, and the secondary grid line on the front side extends in the same direction as the secondary grid line on the back side. A slot extending along the subgate line is provided in the interval area of ​​each of the front sides, and the bottom of the slot penetrates the emitter layer to form an isolation area; a conductive hole is provided in the interval area of ​​each of the front sides, and the conductive hole penetrates the front side and the back side. The conductive hole may overlap with or completely separate from the groove; when the conductive hole overlaps with the groove, the conductive hole extends into the groove; when the conductive hole completely separates from the groove, the minimum edge distance between the conductive hole and the groove is 0-100µm.

2. The battery cell as described in claim 1, characterized in that, The centerline of the groove coincides with the centerline of the spacer area; and / or, the width of the groove is 40-100µm; and / or, the bottom of the groove cuts into the substrate of the solar cell to form an indentation of depth H, wherein H satisfies: 0.005mm≤H≤0.015mm; and / or, the inner wall of the groove is provided with a passivation layer.

3. The battery cell as described in claim 1, characterized in that, The conductive hole includes a through hole and a conductive material filling the through hole.

4. The battery cell as described in claim 3, characterized in that, The diameter of the conductive hole is 80-200µm; and / or, a passivation layer or an emitter layer and a passivation layer are provided on the inner wall of the through hole.

5. The battery cell as described in claim 2 or 4, characterized in that, The passivation layer is an aluminum oxide layer; and / or, the thickness of the passivation layer is 5-50 nm; and / or, the emitter layer is a p+ emitter layer or an n+ emitter layer.

6. The battery cell as described in claim 1, characterized in that, A first grid line is provided on the front side and a second grid line is provided on the back side. The first grid line and the second grid line are provided on both sides of each of the interval regions. The first grid line is formed by connecting the conductive hole with the main grid line of the grid line area on the side adjacent to the front side, and the second grid line is formed by connecting the conductive hole with the main grid line of the grid line area on the side adjacent to the back side.

7. The battery cell as described in claim 6, characterized in that, The main grid line has harpoon lines at both ends, and at least some of the secondary grid lines pass through the harpoon lines; one end of the first grid line is connected to the harpoon line, and the other end extends to the conductive hole and is connected to the conductive hole; one end of the second grid line is connected to the harpoon line, and the other end extends to the conductive hole and is connected to the conductive hole.

8. A photovoltaic module, characterized in that, Includes the battery cell described in any one of claims 1-7.

9. The photovoltaic module as described in claim 8, characterized in that, It also includes a solder strip, one end of which is connected to the main grid line on the front side of the solar cell, and the other end is connected to the main grid line on the back side of the adjacent solar cell.

10. A photovoltaic system, characterized in that, Includes the photovoltaic module as described in any one of claims 8-9.

Images