Back contact cells and photovoltaic modules

Abstract

The utility model provides a kind of back contact battery and photovoltaic module, it is related to silicon-based solar panel technical field, the back contact battery includes: silicon substrate, the silicon substrate includes oppositely arranged front and back, there is periodic interval arrangement's wave crest and wave trough on the back of the silicon substrate, adjacent wave crest to wave crest or wave trough to wave trough is a unit, the horizontal distance of a unit is 60-600 μm;Electrode is located at the back of the silicon substrate, width range 20-300 μm;The horizontal distance of a unit is greater than one electrode width.Compared with the back contact battery of traditional substrate surface flat, the utility model can improve the PN structure density of silicon substrate surface unit area 1-1.42 times, can effectively improve open-circuit voltage, reduce recombination, and improve fill factor, finally improve battery efficiency 0.03-0.1%.

Description

Technical Field

[0001] This utility model relates to the field of silicon-based solar panel technology, and in particular to a back-contact battery and photovoltaic module. Background Technology

[0002] Traditional silicon-based solar cells use flat silicon wafers. Because both the front and back surfaces of these wafers are flat, it is impossible to stack more PN structures per unit area of ​​the wafer, which leads to the following defects:

[0003] (1) The number of PN junctions per unit area is limited by the two-dimensional planar structure;

[0004] (2) The long carrier transport path leads to recombination loss;

[0005] (3) The improvement of solar cell efficiency has encountered a bottleneck.

[0006] Although existing technologies attempt to increase light absorption through surface texturing or etching, they cannot systematically solve the PN junction density problem. Utility Model Content

[0007] The present invention aims to provide a back-contact battery and photovoltaic module, in order to at least partially solve at least one of the above-mentioned technical problems.

[0008] To solve the above-mentioned technical problems, the first aspect of this utility model provides a back contact battery, comprising:

[0009] A silicon substrate, comprising a front side and a back side disposed opposite to each other, wherein the back side of the silicon substrate has periodically and regularly spaced peaks and troughs, wherein adjacent peaks to peaks or troughs to troughs constitute a unit, and the horizontal distance of a unit is 60-600μm.

[0010] An electrode is disposed on the back side of the silicon substrate, with a width ranging from 20 to 300 μm;

[0011] The horizontal distance of a unit is greater than the width of one of the electrodes.

[0012] According to a preferred embodiment of the present invention, a first region and a second region are provided on the back side of the silicon substrate; the electrode includes a first electrode and a second electrode, the first electrode is disposed in the first region, the second electrode is disposed in the second region, and the width of the first electrode is greater than the width of the second electrode.

[0013] According to a preferred embodiment of the present invention, the width of the first electrode is 30-300 μm, and the width of the second electrode is 20-200 μm.

[0014] According to a preferred embodiment of the present invention, the electrode is disposed on the back side of the silicon substrate by electroplating, and the cross section of the electrode along the thickness direction of the silicon substrate is rectangular or square.

[0015] According to a preferred embodiment of the present invention, the angle between the line connecting adjacent crests and troughs and the horizontal plane is 35°-45°.

[0016] According to a preferred embodiment of the present invention, a non-planar structure is provided between the crests and troughs.

[0017] According to a preferred embodiment of the present invention, the height difference between adjacent wave crests and troughs is 0-20 μm.

[0018] According to a preferred embodiment of the present invention, the peak height is 1-10 μm and the trough depth is 1-10 μm.

[0019] According to a preferred embodiment of the present invention, the peak height is selected as 5μm and the trough depth is selected as 5μm.

[0020] To solve the above-mentioned technical problems, the second aspect of this utility model provides a photovoltaic module, including the back contact battery described in any one of the above-mentioned claims.

[0021] In summary, the back surface of the silicon substrate of this invention features periodically spaced peaks and troughs, with the horizontal distance between adjacent peaks or troughs controlled within 60-600 μm. Simultaneously, electrodes with a width ranging from 20-300 μm are disposed on the back surface of the silicon substrate, and the horizontal distance between adjacent peaks or troughs is greater than the width of one electrode. Compared to a flat back surface, this effectively increases the number of first and second regions on the silicon substrate, thereby increasing the number of PN structures per unit area of ​​the silicon wafer and improving the PN structure density. Furthermore, electrodes of equal width at the top and bottom are formed in the peak areas through electroplating, effectively preventing the electrodes formed by printing processes in the peak areas from sliding down to the top, resulting in electrodes with a smaller top width and a larger bottom width. Additionally, controlling the angle between the line connecting adjacent peaks and troughs and the horizontal plane within 35°-45° effectively avoids defects in the solar panels during subsequent manufacturing processes caused by this periodic peak-trough structure. Compared to the prior art, this invention has at least the following beneficial effects:

[0022] (1) Compared with traditional flat silicon wafers, the PN structure density per unit area of ​​silicon substrate can be increased by 1-1.42 times.

[0023] (2) It can effectively increase open-circuit voltage and reduce composite voltage.

[0024] (3) It can shorten the transmission distance response and improve the fill factor (FF). Compared with traditional flat silicon substrates, the cell efficiency can be improved by 0.03-0.1%. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a back contact battery provided in Embodiment 1 of this utility model;

[0026] Figure 2 This is a schematic diagram of the structure of the silicon substrate provided in Embodiment 1 of this utility model;

[0027] Figure 3 This is a schematic diagram of another silicon substrate provided in Embodiment 1 of this utility model;

[0028] Figure 4a This is a schematic diagram of the electrode structure of the back contact battery provided in Embodiment 1 of this utility model, generated by electroplating process.

[0029] Figure 4b This is a schematic diagram of the electrode structure of the back contact battery provided in Embodiment 1 of this utility model, generated using a printing process.

[0030] Wherein: 100-silicon substrate, 200-first region, 300-second region, 201-P functional layer, 301-N functional layer, 400-passivation layer, 51-first electrode, 52-second electrode, 53-gap region, 1-peak, 2-valley, 3-non-planar structure. Detailed Implementation

[0031] The features and exemplary embodiments of various aspects of this utility model will now be described in detail. To make the objectives, technical solutions, and advantages of this utility model clearer, the following description, in conjunction with the accompanying drawings and embodiments, will provide a further detailed description. It should be understood that the specific embodiments described herein are configured only to explain this utility model and are not configured to limit it. For those skilled in the art, this utility model can be implemented without some of these specific details. The following description of the embodiments is merely intended to provide a better understanding of this utility model by illustrating examples of it.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0033] In this invention, the back-contact battery concentrates all electrodes and doped regions on the back of the battery, leaving the front unobstructed to maximize light absorption. P-type and N-type doped regions are typically arranged alternately to form a PN junction and a back surface field.

[0034] Example 1

[0035] Embodiment 1 of this utility model provides a back contact battery, such as Figure 1 The above includes:

[0036] A silicon substrate 100 includes a front side and a back side disposed opposite to each other, the front side being a light-receiving surface and the back side being a backlighting surface. The silicon substrate 100 can be a monocrystalline silicon wafer, a polycrystalline silicon wafer, or a quasi-monocrystalline silicon wafer, etc. (Reference) Figure 2 In this embodiment, during silicon wafer dicing, the dicing trajectory can be controlled to form periodically spaced peaks 1 and troughs 2 on the back side of the silicon substrate 100, thus forming a wave surface. Preferably, to facilitate dicing and the fabrication of other layers (such as tunneling layers, doped layers, dielectric layers, etc.), periodically spaced peaks 1 and troughs 2 can be formed on the back side of the silicon substrate 100, wherein: regular spacing means that the bottom of peak 1 is connected to the bottom of trough 2, and the peaks 1 and troughs 2 have the same or similar shape and size. For example: Figure 1 In the design, both peak 1 and trough 2 are arc-shaped protrusions, and these protrusions are identical in shape and size. Alternatively, peak 1 and trough 2 can also be triangles of the same shape and size, etc. This invention does not impose specific limitations. Figure 2 Adjacent peaks 1 to peak 1 or troughs 2 to trough 2 constitute a unit. In this embodiment, the horizontal distance L of a unit is controlled between 60-600μm.

[0037] The electrode is disposed on the back side of the silicon substrate 100, and its width is controlled within the range of 20-300μm;

[0038] In this embodiment, the horizontal distance L of a unit is greater than the width of an electrode, so that at least one electrode can be set between adjacent peaks 1 or between valleys 2 and 3.

[0039] In one example, the back surface of the silicon substrate 100 is divided into several first regions 200 and several second regions 300. The first regions 200 and second regions 300 can be alternately arranged and separated by gap regions 53. Different functional layers are set on the first regions 200 and second regions 300 to form regions with different electrical characteristics, supporting the formation of PN junctions and the separation of charge carriers. Specifically, if the first region 200 is a P-doped region, then the second region 300 is an N-doped region; or if the first region 200 is an N-doped region, then the second region 300 is a P-doped region. In this way, since the back surface of the silicon substrate 100 has periodically spaced peaks 1 and troughs 2, compared with a flat back surface, the number of first regions 200 and second regions 300 can be effectively increased, thereby increasing the number of PN junctions per unit area of ​​the silicon substrate 100 and improving the PN junction density. Testing revealed that the silicon substrate 100 of this invention, with its periodically spaced peaks 1 and troughs 2, can fabricate PN junctions on a unit area that are 1-1.42 times larger than those on a flat substrate, thus improving battery efficiency. Furthermore, the peaks 1 and troughs 2 can reflect incident light multiple times, increasing the optical path and enhancing the absorption of long-wavelength light (such as infrared light) by the silicon substrate 100, effectively increasing the turn-on voltage and reducing recombination. Due to the shorter transmission distance, the flyback factor (FF) also increases, ultimately resulting in an efficiency improvement of 0.03-0.1%.

[0040] For example, taking the first region 200 as a P-doped region (also called the P-region) and the second region 300 as an N-doped region (also called the N-region) as an example, a P-functional layer 201 can be disposed in the P-doped region away from the silicon substrate 100. For example, the P-functional layer 201 can include: a first dielectric layer and a P-type doped layer. The first dielectric layer is stacked on the first region 200, and the P-type doped layer is stacked on the first dielectric layer. The first dielectric layer and the P-type doped layer can be in direct contact, or other functional layers can be disposed between them. For example, the first dielectric layer can be a tunneling layer, which can be made of materials such as silicon oxide, aluminum oxide, or titanium oxide, with a thickness of 5-10 μm. The P-type doped layer can be obtained by doping elements such as boron and aluminum into a polycrystalline silicon layer, with a thickness of 10-100 μm. An N-functional layer 301 may be disposed in the N-doped region away from the silicon substrate 100. For example, the N-functional layer 301 may include a second dielectric layer and an N-type doped layer. The second dielectric layer is stacked on the second region 300, and the N-type doped layer is stacked on the second dielectric layer. The second dielectric layer and the N-type doped layer may be in direct contact, or other functional layers may be disposed between them. The second dielectric layer may be a tunneling layer, such as a silicon oxide tunneling layer, which has passivation and tunneling functions. The tunneling layer may be made of materials such as silicon oxide, aluminum oxide, or titanium oxide, and its thickness is 5-10 μm. The N-type doped layer can be obtained by doping elements such as phosphorus and arsenic into a polycrystalline silicon layer, and its thickness is 10-100 μm. Furthermore, a passivation layer 400 with a thickness of 5-50 μm can be disposed on the side of the N-type doped layer and the P-type doped layer away from the silicon substrate 100, wherein: the passivation layer 400 can be one or more of the following: intrinsic amorphous silicon layer, intrinsic polycrystalline silicon layer, intrinsic nanocrystalline silicon layer, intrinsic mixed-crystal silicon layer, silicon oxide layer, aluminum oxide layer, silicon oxynitride layer, silicon nitride layer, and silicon carbonitride layer.

[0041] In addition to the above structure, the back contact battery also includes a first electrode 51 and a second electrode 52. The first electrode 51 is disposed in the first region 200 (P-type doped layer) on the side away from the silicon substrate 100, and is electrically connected to the P-type doped layer through the passivation layer 400. The second electrode 52 is disposed in the second region 300 (N-type doped layer) on the side away from the silicon substrate 100, and is electrically connected to the N-type doped layer through the passivation layer 400. The first electrode 51 and the second electrode 52 can be sintered from burn-through paste or non-burn-through paste. The materials of the first electrode 51 and the second electrode 52 can be one or more of aluminum, silver, gold, nickel, molybdenum, or copper. The width of the first electrode 51 is greater than the width of the second electrode 52. Preferably, the width of the first electrode 51 is 30-300 μm, and the width of the second electrode 51 is 20-200 μm.

[0042] In this embodiment, to avoid the occurrence of defective solar panels in subsequent manufacturing processes due to this periodic peak-and-trough structure, such as... Figure 2 The required angle A between the line connecting adjacent peaks 1 and troughs 2 and the horizontal plane needs to be controlled within 35-45°, and the horizontal distance L of a single cell needs to be controlled within 60-600 μm. Specifically, a horizontal angle A of 35-45° balances light scattering and material stress, avoiding carrier recombination caused by sharp angles. If the horizontal angle A exceeds 45°, it will lead to numerous defects in subsequent cell manufacturing processes. Preferably, in this embodiment, the horizontal angle A is chosen to be 45°.

[0043] To further improve the yield, the height difference H between peak 1 and trough 2 is controlled within 0-20 μm. Specifically, a H range of 0–5 μm is suitable for short-wavelength light scattering (UV-Vis). A H range of 5–20 μm enhances the capture of long-wavelength light (infrared). For example, the peak 1 height H1 is 1-10 μm, and the trough 2 depth H2 is 1-10 μm. Preferably, the peak 1 height is 5 μm, and the trough 2 depth is 5 μm.

[0044] In a preferred embodiment, a non-planar structure 3 may be provided between adjacent peaks 1 and troughs 2. The non-planar structure 3 further increases the surface area of ​​the functional layer, thereby increasing the number of first regions 200 and second regions 300 on the silicon substrate 100. The non-planar structure 3 can be convex outwards from the wave surface or concave inwards from it. The non-planar structure 3 can be selected as follows: Figure 3 The trapezoid in the figure can also be a triangle, a curve, or other shapes; this utility model does not impose any specific limitations.

[0045] In this embodiment, the electrodes (first electrode 51 and second electrode 52) are disposed on the back side of the silicon substrate 100 by electroplating, and the cross section of the electrodes along the thickness direction of the silicon substrate 100 is rectangular or square. Figure 4a This demonstrates that an electrode 4 with a rectangular cross-section is formed in the region where wave crest 1 is located through an electroplating process, which effectively prevents the upper part of the electrode formed by the printing process from sliding down, resulting in... Figure 4b The diagram shows an electrode with a smaller upper width and a larger lower width.

[0046] Example 2

[0047] This utility model provides a photovoltaic module in embodiment two, including the back contact battery described in any one of embodiments one.

[0048] In summary, the back surface of the silicon substrate 100 of this invention has periodically spaced peaks 1 and troughs 2, with the horizontal distance between adjacent peaks 1 and peaks 1 or between troughs 2 controlled within 60-600 μm. Simultaneously, electrodes with a width range of 20-300 μm are provided on the back surface of the silicon substrate 100, and the horizontal distance between adjacent peaks 1 and peaks 1 or between troughs 2 and troughs 2 is greater than the width of one electrode. Compared to a flat back surface, this effectively increases the number of first and second regions on the silicon substrate 100. Furthermore, electrodes 4 with the same upper and lower width are provided in the area where peaks 1 are located through electroplating, effectively preventing the upper part of the electrodes formed by printing in the area where peaks are located from sliding down, resulting in electrodes with a smaller upper width and a larger lower width. At the same time, controlling the angle between the line connecting the apex of adjacent peaks 1 and troughs 2 and the horizontal plane within 35°-45° effectively avoids the occurrence of defective solar panels in subsequent manufacturing processes due to this periodic peak-trough structure. Compared with the prior art, this utility model has at least the following beneficial effects:

[0049] (1) Compared with traditional flat silicon wafers, the PN structure density per unit area of ​​silicon wafer surface can be increased by 1-1.42 times.

[0050] (2) It can effectively increase open-circuit voltage and reduce composite voltage.

[0051] (3) It can shorten the transmission distance response and improve the FF. Compared with traditional flat silicon wafers, the battery efficiency can be improved by 0.03-0.1%.

[0052] It should be clarified that this utility model is not limited to the specific structures and processes described above and shown in the figures. For the sake of brevity, detailed descriptions of known structures are omitted here. In the above embodiments, several specific structures are described and shown as examples. However, the lens cleaning device of this utility model is not limited to the specific structures described and shown. Those skilled in the art can make various changes, modifications, and additions, or change the installation positions between structures, after understanding the spirit of this utility model.

[0053] The above description is merely a specific embodiment of this utility model. Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the structures, modules, and units described above can be referred to the corresponding processes in the foregoing embodiments, and will not be repeated here. It should be understood that the protection scope of this utility model is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this utility model, and these modifications or substitutions should all be covered within the protection scope of this utility model.

Claims

1. A back-contact battery, characterized in that, include: A silicon substrate, comprising a front side and a back side disposed opposite to each other, wherein the back side of the silicon substrate has periodically spaced peaks and troughs, wherein adjacent peaks to peaks or troughs to troughs constitute a unit, and the horizontal distance of a unit is 60-600 μm. An electrode is disposed on the back side of the silicon substrate, with a width ranging from 20 to 300 μm; The horizontal distance of a unit is greater than the width of one of the electrodes.

2. The back contact battery according to claim 1, characterized in that, The back side of the silicon substrate is provided with a first region and a second region; the electrode includes a first electrode and a second electrode, the first electrode is disposed in the first region, the second electrode is disposed in the second region, and the width of the first electrode is greater than the width of the second electrode.

3. The back contact battery according to claim 2, characterized in that, The width of the first electrode is 30-300 μm, and the width of the second electrode is 20-200 μm.

4. The back contact battery according to claim 1, characterized in that, The electrode is deposited on the back side of the silicon substrate by electroplating, and the cross-section of the electrode along the thickness direction of the silicon substrate is rectangular or square.

5. The back contact battery according to claim 1, characterized in that, The angle between the line connecting adjacent crests and troughs and the horizontal plane is 35°-45°.

6. The back contact battery according to claim 1, characterized in that, There is a non-planar structure between the crests and troughs.

7. The back contact battery according to claim 1, characterized in that, The height difference between adjacent peaks and troughs is 0-20 μm.

8. The back contact battery according to claim 1, characterized in that, The peak height is 1-10 μm, and the trough depth is 1-10 μm.

9. The back contact battery according to claim 8, characterized in that, The peak height was selected as 5μm, and the trough depth was selected as 5μm.

10. A photovoltaic module, characterized in that, Includes the back contact battery as described in any one of claims 1-9.

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