Silicon wafer substrate and heterojunction cell

Abstract

The application relates to the technical field of solar cells, in particular to a silicon wafer substrate and a heterojunction cell. The silicon wafer substrate comprises a front surface and a back surface arranged oppositely, and a side surface is arranged around the front surface and the back surface; wherein the back surface comprises an edge surrounding area, and the remaining area of the back surface is a center area; the edge surrounding area is a textured structure, and the center area is a polished surface; and the front surface is a textured structure. The silicon wafer substrate can make the edge area have a smaller plating thickness, insulate and isolate the front and back film, and the center area is responsible for optical reflection and passivation improvement. The silicon wafer substrate has the characteristics of preventing electric leakage, enhancing internal reflection and improving passivation, and realizes the synergistic optimization of electrical performance and optical performance.

Description

Technical Field

[0001] This application relates to the field of solar cell technology, and more particularly to a silicon wafer substrate and a heterojunction cell. Background Technology

[0002] Currently, silicon-based solar cells are highly industrialized, possessing excellent photoelectric conversion efficiency, reliability, and stability. The silicon wafer substrate is the fundamental material constituting the cell. The surface morphology of the silicon wafer is one of the key factors affecting its performance.

[0003] With continuous technological advancements, silicon-based solar cells have undergone multiple technological iterations, resulting in various structures such as aluminum back surface field (Al-BSF) cells, PERC cells, TOPCon cells, HJT cells, XBC cells, and crystalline silicon / perovskite tandem cells. Different types of cells place varying performance requirements on the silicon substrate. For HJT cells, a textured front and polished back silicon substrate structure is typically used. However, after depositing functional thin films such as amorphous silicon, leakage channels can easily form at the edges of the front and back films, affecting cell performance. This issue is one of the key challenges that needs to be addressed in current HJT technology.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Utility Model Content

[0005] This application provides a silicon wafer substrate and a heterojunction solar cell to solve or alleviate one or more of the technical problems mentioned above.

[0006] A first aspect of this application provides a silicon wafer substrate, the silicon wafer substrate including a front side and a back side disposed opposite to each other, and a side side surrounding the front side and the back side; The back side includes an edge surrounding area, and the remaining area of ​​the back side is a central area; the edge surrounding area has a velvety texture, and the central area has a polished surface; the front side has a velvety texture.

[0007] The silicon wafer substrate of this application allows for a smaller thickness of the coating around the edge area, enabling insulation isolation between the front and back films, while the central area is responsible for optical reflection. This silicon wafer substrate combines the characteristics of "preventing leakage" and "enhancing internal reflection", achieving synergistic optimization of electrical and optical performance.

[0008] Optionally, the edge surrounding area is a closed annular frame-shaped area. This closed annular frame-shaped area effectively isolates the connection between the front and back films, preventing leakage.

[0009] Optionally, the edge surrounding area is composed of multiple discontinuous velvet blocks arranged at intervals.

[0010] Optionally, the width of the surrounding edge area is 0.1 mm to 5 mm. This effectively prevents leakage without significantly sacrificing the battery's effective power generation area.

[0011] Optionally, there is a height difference between the surface of the edge surrounding region on the back side and the surface of the central region, with the edge surrounding region protruding from or recessed from the central region. This height difference physically and completely blocks the connection between the back film and the front film (via side 2), fundamentally solving the leakage path problem.

[0012] Optionally, the polished surface of the central region is a mirror-polished surface, and the reflectivity of the polished surface to 550nm wavelength light is not less than 90%. Thus, using a mirror-polished surface further improves the absorption and utilization of light.

[0013] Optionally, the silicon substrate is an N-type monocrystalline silicon wafer; the thickness of the silicon substrate is less than or equal to 200 μm. Therefore, it is suitable for heterojunction solar cells.

[0014] Optionally, the front velvet structure can be a random pyramid velvet, a pitted velvet, a black silicone velvet, and / or an inverted pyramid velvet.

[0015] Optionally, the back surface texture can be a random pyramid texture, a pitted texture, a black silicone texture, and / or an inverted pyramid texture.

[0016] Optionally, the side surface has a velvety structure. This facilitates continuous fabrication of the velvety surface, eliminating the need for staged fabrication.

[0017] A second aspect of this application provides a heterojunction solar cell, including the silicon substrate described in the first aspect of this application. This heterojunction solar cell eliminates edge leakage and improves conversion efficiency. Attached Figure Description

[0018] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the various drawings denote the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings depict only some embodiments disclosed in this application and should not be construed as limiting the scope of this application.

[0019] Figure 1 This is a schematic diagram of the structure of a silicon wafer substrate provided in some embodiments of this application; Figure 2 This is a schematic diagram of the structure of a silicon wafer substrate provided in other embodiments of this application; Figure 3 This is a bottom view schematic diagram of a silicon wafer substrate provided in some embodiments of this application; Explanation of reference numerals in the attached figures: 1-Front; 2-Side; 3-Back; 301-Edge surrounding area; 302-Back of central area. Detailed Implementation

[0020] The embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings. In the drawings, for clarity, the dimensions of layers, regions, and elements, as well as their relative dimensions, may be exaggerated. Throughout, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this application can be combined with each other.

[0021] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this application.

[0022] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0023] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0024] In this application, when numerical intervals (i.e., numerical ranges) are involved, unless otherwise specified, the distribution of selectable numerical values ​​within the numerical interval is considered continuous, and includes the two endpoints of the numerical interval (i.e., the minimum and maximum values), as well as every numerical value between these two endpoints. Unless otherwise specified, when a numerical interval refers only to integers within that numerical interval, it includes the two endpoint integers of the numerical range, as well as every integer between the two endpoints, which is equivalent to directly listing every integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical ranges disclosed in this application should be understood to include any and all subranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, percentage, ratio, etc. The term "numerical interval" can be broadly included to include percentage intervals, ratio intervals, proportion intervals, etc.

[0025] This application provides a silicon wafer substrate and a heterojunction solar cell technology solution. Based on this, it solves the problem that leakage channels can easily form when the front and back films are interconnected at the edge regions. See below for details.

[0026] Exemplary embodiments according to this application will now be described in more detail with reference to the accompanying drawings. It should be understood that these exemplary embodiments may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0027] The first aspect of this application provides a silicon wafer substrate.

[0028] like Figure 1 and Figure 3 As shown, the silicon wafer substrate includes a front side 1 and a back side 3 disposed opposite to each other, with a side side 2 surrounding the front side 1 and the back side 3; The back surface 3 includes an edge surrounding area 301, and the remaining area of ​​the back surface is a central area 302; the edge surrounding area 301 has a velvety surface, and the central area 302 has a polished surface; the front surface 1 has a velvety surface.

[0029] In this embodiment of the silicon substrate, the structure fundamentally severs the conductive film path extending from the front side 1 through the side side 2 to the back side 3 in the HJT cell. The edge surrounding region 301 on the back side is designed with a textured surface, whose rough surface effectively disrupts the continuity of the amorphous silicon or TCO (transparent conductive oxide) film deposited thereon, forming a natural, high-resistance insulating isolation region. The presence of the textured surface of the edge surrounding region 301 greatly suppresses the recombination of charge carriers through the leakage channels at the edge of the cell, significantly reducing the parallel resistance of the cell, thereby improving the open-circuit voltage and fill factor of the cell, and ultimately achieving higher photoelectric conversion efficiency. Meanwhile, the central region 302 on the back side remains a polished surface with extremely high smoothness and reflectivity, which can efficiently reflect long-wavelength light transmitted through the silicon wafer back into the cell for secondary absorption, enhancing the cell's ability to capture light (i.e., the "light trapping effect"), thereby increasing the cell's short-circuit current (Isc). The silicon wafer substrate of this application allows for a smaller thickness of the coating around the edge area, enabling insulation isolation between the front and back films, while the central area is responsible for optical reflection. This silicon wafer substrate combines the characteristics of "preventing leakage" and "enhancing internal reflection", achieving synergistic optimization of electrical and optical performance.

[0030] In this embodiment, the edge surrounding region 301 on the back side of the silicon substrate can be a continuously distributed textured structure region; the edge surrounding region 301 on the back side can also be a discontinuous textured structure region, in which case the textured structure region can be separated by non-textured regions. In an optional embodiment, the edge surrounding region can be formed by multiple discontinuous textured blocks arranged at intervals. Preferably, see below. Figure 3 The edge surrounding area 301 can be a closed annular frame-shaped area; thus, the closed annular frame-shaped area can ensure effective isolation of the connection between the front and back films and prevent leakage.

[0031] Furthermore, the width of the surrounding edge region is 0.1 mm to 5 mm. This effectively prevents leakage without excessively sacrificing the battery's effective power generation area. For example, the width of the surrounding edge region can be 0.1 mm, 0.2 mm, 0.3 mm, 0.5 mm, 1 mm, 2.5 mm, 3.5 mm, 5 mm, etc.

[0032] In an optional embodiment, there is a height difference between the surface of the edge surrounding region 301 of the back side 3 and the surface of the central region 302 in the silicon substrate. This height difference physically and completely blocks the connection between the back film and the front film (via the side 2), fundamentally solving the leakage path problem and providing a more reliable solution than simple surface morphology differences.

[0033] Furthermore, the height difference can be from 0.5μm to 10μm. For example, the height difference can be 0.5μm, 1.5μm, 3.5μm, 5.5μm, 6μm, 7μm, 8μm, 9μm, 10μm, etc.

[0034] In some specific embodiments, see Figure 1 In this silicon substrate, the edge surrounding region 301 protrudes above the central region 302. With the edge higher than the center, the protruding structure acts as a physical barrier, directly preventing the back film from contacting the front film and thus preventing leakage.

[0035] In other specific embodiments, see Figure 2 In this silicon wafer substrate, the edge surrounding region 301 is recessed within the central region 302. At this point, the edge is lower than the center, and trenches can be formed at the edge recess, which can better isolate the active silicon wafer edge, where carrier recombination is active, from the active region at the center, thus improving the open-circuit voltage of the battery.

[0036] In an optional embodiment, the polished surface of the central region 302 in the silicon wafer substrate is a mirror-polished surface, and the reflectivity of the polished surface to 550nm wavelength light is not less than 90%. Therefore, using a mirror-polished surface is beneficial to improving the reflectivity of light, thereby further improving the absorption and utilization of light.

[0037] In an optional embodiment, the silicon substrate is an N-type monocrystalline silicon wafer. This makes it suitable for heterojunction solar cells (HJT cells).

[0038] Optionally, the thickness of the silicon substrate is less than or equal to 200 μm.

[0039] Furthermore, the thickness of the silicon substrate can be from 30μm to 130μm. For example, 30μm, 40μm, 50μm, 60μm, 80μm, 90μm, 100μm, 110μm, 130μm, etc.

[0040] The embodiments of this application do not limit the textured surface structure. Those skilled in the art can choose according to their needs. For example, the front textured surface structure is a random pyramid textured surface, a pitted textured surface, a black silicone textured surface, and / or an inverted pyramid textured surface; the back textured surface structure is a random pyramid textured surface, a pitted textured surface, a black silicone textured surface, and / or an inverted pyramid textured surface.

[0041] In an optional embodiment, the side surface 2 of the silicon substrate has a textured structure. This facilitates continuous fabrication of the textured surface, eliminating the need for staged fabrication.

[0042] This application provides a method for preparing a silicon wafer substrate, comprising the following operations: providing a silicon wafer, then texturing both sides to form a textured structure on the front, back, and side surfaces of the silicon wafer; then depositing silicon oxide or silicon nitride as a mask layer on the front surface 1, while simultaneously forming silicon oxide or silicon nitride coatings on the side surface 2 and the edge surrounding area 301 during the deposition process; polishing the central area 302 not covered by silicon oxide or silicon nitride to form a polished surface; and removing the silicon oxide or silicon nitride to obtain the silicon wafer substrate, as shown in the schematic diagram below. Figure 1 As shown.

[0043] This application provides another method for preparing a silicon wafer substrate, including the following operations: providing a silicon wafer, followed by double-sided polishing to form polished surfaces on the front, back, and side surfaces of the silicon wafer; then depositing silicon oxide or silicon nitride as a mask layer in the central region 302 of the back surface 3; texturing the front surface 1, side surface 2, and edge surrounding region 301 not covered by silicon oxide or silicon nitride to form a textured structure; and removing the silicon oxide or silicon nitride to obtain the silicon wafer substrate, as shown in the schematic diagram below. Figure 2 As shown.

[0044] A second aspect of this application provides a heterojunction solar cell, including the silicon substrate described in the first aspect of this application. This heterojunction solar cell eliminates edge leakage and improves conversion efficiency.

[0045] The following section will present performance tests on the HJT battery manufacturing method and related comparative examples provided in this application.

[0046]

Example 1

[0047] Step 1: Fabrication of a silicon substrate with a backside partitioned structure Silicon wafer cleaning: We provide standard N-type monocrystalline silicon wafers and clean them using the standard RCA cleaning process to remove surface contaminants, metallic impurities, and the natural oxide layer.

[0048] Double-sided texturing: The cleaned silicon wafer is placed in an alkaline texturing solution (such as a mixture of sodium hydroxide and isopropanol) and anisotropically etched at 85°C. A uniform, random pyramidal textured surface structure is formed on the front side 1, back side 3, and side side 2 of the silicon wafer. This textured surface structure effectively reduces surface reflectivity.

[0049] Deposition mask layer: A layer of silicon nitride (SiN) is deposited on the front side of the silicon wafer using plasma-enhanced chemical vapor deposition (PECVD). x The silicon oxide or silicon nitride layer serves as a mask layer. During deposition, due to the wrap-around effect, the side surface 2 and the surrounding area 301 of the back edge are also covered by the wrap-around material. However, the central area 302 of the back surface is not covered or is covered very thinly because it is in the shadow area of ​​the plasma atmosphere.

[0050] Selective polishing: The silicon wafer is placed in an alkaline polishing solution (such as a diluted potassium hydroxide solution). Due to the good masking effect of silicon nitride on alkaline solutions, the front side 1, side side 2, and back edge region 301 are protected. The textured structure of the back center region 302, which is not covered by the mask, is etched and polished by the alkaline solution, ultimately forming a smooth polished surface.

[0051] Mask Removal: The silicon wafer is immersed in hydrofluoric acid (HF) buffer to completely remove the mask layer on the front side 1 and the coating around the sides 2 and edge region 301, exposing and preserving the original textured structure underneath. Thus, the silicon substrate is obtained: the front side 1 is textured, the central region 302 on the back side is polished, and the back edge surrounding region 301 and sides 2 are textured. The width of the back edge surrounding region 301 is 0.2 mm.

[0052] Step 2: Deposition of HJT battery functional thin film Fabrication of amorphous silicon layer by CVD: Place the partitioned substrate described above into HJT's PECVD equipment.

[0053] First, intrinsic amorphous silicon (ia-Si:H) passivation layers are deposited sequentially on both sides of the silicon wafer. This layer perfectly covers both textured and polished surfaces, forming excellent surface passivation.

[0054] Then, a p-type doped microcrystalline silicon layer (μc-Si:H(p)) is deposited on the intrinsic layer of the front side (p-type face), and an n-type doped microcrystalline silicon layer (μc-Si:H(n)) is deposited on the intrinsic layer of the back side (n-type face) to form a heterojunction structure.

[0055] PVD fabrication of TCO layer: Indium tin oxide (ITO) is deposited on the doped silicon layers on both sides of the cell using a magnetron sputtering (PVD) device.

[0056] Step 3: Fabrication of Electrodes Screen printing: Using screen printing technology, fine grid lines and main grid lines are printed and cured on the front TCO layer, and corresponding back electrodes are printed and cured on the back TCO layer.

[0057]

Example 2

[0058] Double-sided polishing: The cleaned silicon wafer is placed in an alkaline polishing solution (such as diluted potassium hydroxide or sodium hydroxide solution) for chemical mechanical polishing or pure chemical polishing, forming a smooth polished surface on the front, back, and sides of the silicon wafer. This polished surface has high reflectivity.

[0059] Deposition mask layer: Using plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD) equipment, a layer of silicon oxide (SiO2) is precisely deposited in the central region on the back side of the silicon wafer. x ) or silicon nitride (SiN) x This is used as a mask layer. By controlling the process (such as using a masking plate), it is ensured that the edge surrounding area and sides are basically not covered.

[0060] Selective texturing: The silicon wafers are placed in an alkaline texturing solution (such as a mixed solution of sodium hydroxide and isopropanol) and anisotropically etched at 85°C.

[0061] The areas surrounding the front, sides, and back edges that are not covered by the mask react with the alkali solution to form a uniform, random pyramidal velvet structure with a width of 0.2 mm.

[0062] The central area of ​​the back side covered by the mask is protected, and the polished surface underneath is preserved from corrosion.

[0063] Mask Removal: Immerse the silicon wafer in hydrofluoric acid (HF) buffer to completely remove the silicon oxide or silicon nitride mask layer in the central area of ​​the back side, exposing and preserving the smooth polished surface underneath. This yields the desired silicon substrate: a textured front side, a polished central area on the back side, and textured edges and sides.

[0064] Step 2: Deposition of HJT battery functional thin film Fabrication of amorphous silicon layer by CVD: Place the partitioned substrate described above into HJT's PECVD equipment.

[0065] First, intrinsic amorphous silicon (ia-Si:H) passivation layers are deposited sequentially on both sides of the silicon wafer. This layer perfectly covers both textured and polished surfaces, forming excellent surface passivation.

[0066] Then, a p-type doped microcrystalline silicon layer (μc-Si:H(p)) is deposited on the intrinsic layer of the front side (p-type face), and an n-type doped microcrystalline silicon layer (μc-Si:H(n)) is deposited on the intrinsic layer of the back side (n-type face) to form a heterojunction structure.

[0067] PVD fabrication of TCO layer: Indium tin oxide (ITO) is deposited on the doped silicon layers on both sides of the cell using a magnetron sputtering (PVD) device.

[0068] Step 3: Fabrication of Electrodes Screen printing: Using screen printing technology, fine grid lines and main grid lines are printed and cured on the front TCO layer, and corresponding back electrodes are printed and cured on the back TCO layer.

[0069] Comparative Example 1 The other steps are the same as in Example 1, except that step one is as follows: Step 1: Preparing the silicon wafer substrate Silicon wafer cleaning: We provide standard N-type monocrystalline silicon wafers and clean them using the standard RCA cleaning process to remove surface contaminants, metallic impurities, and the natural oxide layer.

[0070] Front-side texturing: The cleaned silicon wafer is placed in an alkaline texturing solution (such as a mixture of sodium hydroxide and isopropanol) and anisotropically etched at 85°C. This forms a uniform, random pyramidal textured surface structure on the front side of the silicon wafer. This textured surface structure effectively reduces surface reflectivity.

[0071] Step 2: Deposition of HJT battery functional thin film Fabrication of amorphous silicon layer by CVD: Place the partitioned substrate described above into HJT's PECVD equipment.

[0072] First, intrinsic amorphous silicon (ia-Si:H) passivation layers are deposited sequentially on both sides of the silicon wafer. This layer perfectly covers both textured and polished surfaces, forming excellent surface passivation.

[0073] Then, a p-type doped microcrystalline silicon layer (μc-Si:H(p)) is deposited on the intrinsic layer of the front side (p-type face), and an n-type doped microcrystalline silicon layer (μc-Si:H(n)) is deposited on the intrinsic layer of the back side (n-type face) to form a heterojunction structure.

[0074] PVD fabrication of TCO layer: Indium tin oxide (ITO) is deposited on the doped silicon layers on both sides of the cell using a magnetron sputtering (PVD) device.

[0075] Step 3: Fabrication of Electrodes Screen printing: Using screen printing technology, fine grid lines and main grid lines are printed and cured on the front TCO layer, and corresponding back electrodes are printed and cured on the back TCO layer.

[0076] Test case The HJT batteries of Examples 1-2 and Comparative Example 1 were subjected to IV tests to obtain the fill factor, open circuit voltage, short circuit current density, power conversion efficiency, and parallel resistance (Rsh).

[0077] The fill factor (FF) used in this article refers to the actual maximum available power (P). m or V mp ×J mp The ratio of the theoretical (not practically available) power (Jsc × Voc) to the theoretical (not practically available) power (Jsc × Voc). Therefore, FF can be determined by the following formula: FF = (V mp ×J mp ) / (J sc ×V oc Jmp and Vmp represent the current density and voltage at the maximum power point (Pm), respectively, which is obtained by changing the resistance in the circuit until J×V reaches its maximum value; Jsc and Voc represent the short-circuit current and open-circuit voltage, respectively. The fill factor is a key parameter for evaluating solar cells. Commercial solar cells typically have a fill factor of approximately 60% or higher.

[0078] The open-circuit voltage (Voc) used in this paper is the potential difference between the anode and cathode of the device under conditions of no external load connection.

[0079] The short-circuit current density (Jsc) used in this article is the maximum current density flowing through the output terminal of a photovoltaic cell or module when it is short-circuited (voltage V=0) under STC conditions.

[0080] The power conversion efficiency (PCE) of solar cells used in this article refers to the percentage of power converted from absorbed light into electrical energy. The PCE of a solar cell can be measured under standard test conditions (STC) based on incident light irradiance (E: W / m²). 2 ) and the surface area of ​​solar cells (Ac:m 2 The STC is calculated by dividing by the point of maximum power (Pm). STC typically refers to the value at a temperature of 25°C and an irradiance of 1000 W / m². 2 The spectrum of air quality 1.5 (AM1.5).

[0081] The parallel resistance (Rsh) in this paper is the value obtained by differentiating the IV curve under STC near the point of V = 0.

[0082] Test data are shown in Table 1:

[0083] In Table 1, Jsc is the short-circuit current density; Voc is the open-circuit voltage; FF is the fill factor; PCE is the conversion efficiency; and Rsh is the parallel resistance.

[0084] As can be seen from Table 1 above, compared with Comparative Example 1, Example 1 and Example 2 show a significant improvement in Rsh, and significant improvements in Jsc, Voc, FF, and PCE. This indicates that the embodiments of this application have solved the leakage problem.

[0085] It should be noted that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential," etc., are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this application. The directional terms "inner" and "outer" refer to the inside or outside relative to the outline of the component itself. For example, if a device in the drawings is inverted, a device described as "above" or "on top of" other devices or structures will subsequently be positioned as "below" or "under" other devices or structures. Thus, the exemplary term "above" can include both "above" and "below." The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein are interpreted accordingly.

[0086] It should also be noted that the terms "one embodiment," "another embodiment," and "embodiment" used in this application refer to specific features, structures, or characteristics described in connection with that embodiment, which are included in at least one embodiment described in the general description of this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in connection with any embodiment, the intention is to suggest that implementing such a feature, structure, or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0087] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0088] It should also be noted that the above are merely preferred embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A silicon wafer substrate, characterized in that, The silicon substrate includes a front side and a back side disposed opposite to each other, with a side side surrounding the front side and the back side; The back side includes an edge surrounding area, and the remaining area of ​​the back side is a central area; the edge surrounding area has a velvety texture, and the central area has a polished surface; the front side has a velvety texture.

2. The silicon wafer substrate according to claim 1, characterized in that, The surrounding edge region is a closed annular frame-shaped region.

3. The silicon wafer substrate according to claim 1, characterized in that, The edge surrounding area is composed of multiple discontinuous velvet blocks arranged at intervals.

4. The silicon wafer substrate according to claim 1, characterized in that, The width of the edge surrounding area is 0.1 mm to 5 mm.

5. The silicon wafer substrate according to claim 1, characterized in that, There is a height difference between the surface of the edge surrounding region on the back side and the surface of the central region, and the edge surrounding region protrudes from or is recessed from the central region.

6. The silicon wafer substrate according to claim 1, characterized in that, The polished surface of the central region is a mirror-polished surface, and the reflectivity of the polished surface to 550nm wavelength light is not less than 90%.

7. The silicon wafer substrate according to claim 1, characterized in that, The silicon substrate is an N-type monocrystalline silicon wafer; and / or The thickness of the silicon substrate is less than or equal to 200 μm.

8. The silicon wafer substrate according to claim 1, characterized in that, The front velvet structure is a random pyramid velvet, a pitted velvet, a black silicone velvet, and / or an inverted pyramid velvet; and / or The back surface texture is a random pyramid texture, a pitted texture, a black silicone texture, and / or an inverted pyramid texture.

9. The silicon wafer substrate according to claim 1, characterized in that, The sides have a velvety texture.

10. A heterojunction battery, characterized in that, Includes the silicon wafer substrate as described in any one of claims 1 to 9.

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