A redistribution layer circuit and chip

Abstract

The utility model provides a kind of redistribution layer circuit and chip, it is related to redistribution layer circuit technical field.Target bump and to be connected bump based on each other's physical position relation, each according to preset shape extends corresponding wide line;With the wide line that target bump extends as bottom side, extend along first direction, the plurality of first thin lines that extends and the bottom side is orthogonal;With the wide line that to be connected bump extends as bottom side, extend along first direction, the plurality of second thin lines that extends and the bottom side is orthogonal, the plurality of first thin lines and the plurality of second thin lines between with the minimum spacing of design rule keep each other interlaced.The utility model proposes brand-new redistribution layer circuit, bump does not need to have specific law logic connection.Enhance power supply quality, flexible adaptation different bump period arrangement, do not require bump to have law logic connection, improve redistribution layer implementation efficiency, reduce power noise, optimize overall structure static and dynamic voltage drop.

Description

Technical Field

[0001] This utility model relates to the field of redistribution layer circuit technology, and in particular to a redistribution layer circuit and chip. Background Technology

[0002] In electronics, a chip is a way to miniaturize circuits, typically manufactured on the surface of a semiconductor wafer. With the development of electronic science, the demand for chips is increasing. As chip packaging trends towards miniaturization and lightweighting, the rationality and scientific nature of the packaging structure will affect the quality of the chip.

[0003] Currently, medium and large-sized chips typically use flip-chip (FC) packaging technology to achieve more uniform power supply. Compared to wire bonding technology, the conductive bumps on FC chips are usually arranged in a regular array within the chip's internal region. FC chips typically use a Re-Distribution Layer (RDL) wiring to interconnect the bumps with the chip's internal power network.

[0004] The redistribution layer circuits obtained by the RDL routing method designed in the existing technology do not make full use of space, leaving a large number of blank areas. Furthermore, the RDL circuits are only implemented for structures with specific logical connections arranged in a periodic bump pattern, and cannot be implemented for structures with irregular logical connections in the bump pattern of flip-chip technology chips. Utility Model Content

[0005] In view of the above problems, the present invention is proposed to provide a redistribution layer circuit and chip that overcomes or at least partially solves the above problems.

[0006] In a first aspect, this utility model embodiment provides a redistribution layer circuit, the redistribution layer circuit comprising: a plurality of bumps, a plurality of wide lines and a plurality of thin lines; The plurality of bumps includes: a target bump and at least one bump to be connected; Based on their physical positional relationship, the target bump and the bump to be connected each extend a corresponding wide line according to a preset shape. Using the wide line extending from the target protrusion as the bottom edge, it extends along the first direction, and the extended first thin lines are orthogonal to the bottom edge; Using the wide line extending from the protrusion to be connected as the bottom edge, it extends along the first direction. Multiple second thin lines extend orthogonally to the bottom edge. The multiple first thin lines and the multiple second thin lines are staggered with each other at the minimum spacing of the design rules. The preset shape is as follows: the bottom edge formed by the target bump extending a wide line is parallel to the second direction, the bottom edge formed by the bump to be connected extending a wide line is also parallel to the second direction, and the area of ​​the interactive region formed by the multiple first thin lines and multiple second thin lines between the two wide lines meets the preset requirements. The preset requirements are: the thin lines extended between each target bump and its corresponding bump to be connected intersect to form an interactive region, the sum of the areas of all interactive regions is as large as possible, and the maximum width requirement in the design rules is met.

[0007] Optionally, the target bump is configured to select any one of the multiple periodically arranged bumps as the target bump; The bump to be connected is configured such that, based on the periodic arrangement of the multiple bumps and combined with the physical position of the target bump, the bump with sufficient interconnection space with the target bump among the multiple bumps that are close to the target bump in the target direction is used as the connecting bump, and the target direction is the various directions around the target bump; The sufficient interconnect space refers to the space that allows for wiring connections between the target bump and the bump to be connected, using a line type that reaches or approaches the maximum linewidth of the redistribution layer.

[0008] Optionally, the wide line is configured to determine the extension direction of the corresponding wide line of the target bump and the bump to be connected based on the physical positional relationship between the target bump and the bump to be connected, and to extend the corresponding wide line according to the extension direction of the target bump and the bump to be connected, wherein the corresponding wide line serves as the bottom edge, which is parallel to the second direction, and the length of the bottom edge needs to reach or be close to the width of the maximum line width of the redistribution layer.

[0009] Optionally, the width line configuration is to determine the extension direction of the width line corresponding to each of the target bump and the bump to be connected, based on the direction of the center line connecting the target bump and the bump to be connected; specifically including: If the center line is parallel to the first direction, the width line is configured such that the target bump extends its width line in the direction of the center line, and the bump to be connected also extends its width line in the direction of the center line, while ensuring that the preset shape is met. If the center line is parallel to the second direction, then the wide line is configured such that, among the selectable wiring directions in the redistribution layer, the target bump and the bump to be connected each select a direction that is not the second direction but is close to the second direction as their respective extension direction, provided that the preset shape is met. If the nearest direction is taken as the extension direction, and the extension direction cannot make the wide line provide a bottom edge parallel to the second direction, then the wide line is configured such that, on the premise of ensuring that the preset shape is met, the target bump is bent at a certain angle towards the direction of the bump to be connected as the extension direction corresponding to the target bump, and the bump to be connected is bent at a certain angle towards the direction of the target bump as the extension direction corresponding to the bump to be connected. If the center line is neither parallel to the first direction nor parallel to the second direction, the wide line is configured to find an available extension direction in other unoccupied wiring space in the redistribution layer, and determine whether the preset shape is satisfied after extending in that direction or after the zigzag line is extended at a certain angle. If it is satisfied, that direction is used as the extension direction.

[0010] Optionally, the wide line is further configured such that, after extending the corresponding wide lines according to the respective extension directions of the target bump and the bump to be connected, and there is still remaining space and the remaining space satisfies the target condition, a step structure is made at the bottom edge of the corresponding thin line to be generated, so as to increase the length of the corresponding wide line as the bottom edge. The target condition refers to the fact that the area of ​​the interactive area already meets the preset requirements before the step structure is added.

[0011] Optionally, the plurality of first thin lines and the plurality of second thin lines are configured such that, based on the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines, the interactive areas formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines are either fused or not fused.

[0012] Optionally, the plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are all the same power line, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines is fused and connected. The plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are not the same power line and are one power and one ground, the interaction area formed by the plurality of first thin lines and the plurality of second thin lines intersecting each other is not fused and connected. In this case, the interaction area formed by the plurality of first thin lines and the plurality of second thin lines intersecting each other serves as a capacitor area between two power lines. The plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are different lines that are both electrical or both ground, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines is not fused and connected. In this case, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines serves as the boundary of the voltage domain corresponding to the two power lines.

[0013] Optionally, after merging or not merging the interactive areas formed by the intersecting of multiple first thin lines and multiple second thin lines, the thin lines are further configured such that, between the remaining protrusions other than the target protrusion and the protrusion to be connected, or between each protrusion extending a wide line, or between each protrusion extending a wide line to another protrusion, there are areas where corresponding thin lines can extend, and corresponding wide lines already exist. In this case, using the corresponding wide line as the bottom edge, multiple corresponding thin lines extend in the first direction, intersecting to form interactive areas; or... If there is a region where corresponding thin lines can be extended but there are no corresponding wide lines, then a wide line is extended at the corresponding position, which is used as the bottom edge, and multiple corresponding thin lines are extended in the first direction to intersect and form an interactive region.

[0014] Optionally, the plurality of first thin lines and the plurality of second thin lines are configured such that, during the fusion connection, the regions between the plurality of first thin lines and the plurality of second thin lines, as well as the regions between each thin line and the wide line, are filled with the metal lines of the redistribution layer; and, during filling, if a wide line serves as the bottom edge and its corresponding length is greater than the maximum line width in the redistribution layer design rules, then the plurality of first thin lines and the plurality of second thin lines are divided into several groups on an even basis, wherein the width of all thin lines and their filling metal lines in each group is not greater than the width of the maximum line width in the redistribution layer design rules, and gaps are reserved between each group.

[0015] Optionally, the plurality of said thin lines include: elongated rectangular metal lines or zigzag metal lines; The multiple thin lines must satisfy the characteristics of having a large area and small spacing after they intersect each other.

[0016] Optionally, the first direction has an arbitrary angle with the main wiring direction of the next layer of metal adjacent to the redistribution layer.

[0017] Optionally, the first direction is orthogonal to the main wiring direction of the next metal layer immediately adjacent to the redistribution layer.

[0018] In a second aspect, embodiments of the present invention provide a chip, the chip comprising: a redistribution layer circuit as described in any of the first aspects.

[0019] This invention presents a novel redistribution layer circuit for chips with periodically arranged bumps in flip-chip packaging. It creatively proposes a new redistribution layer circuit that only requires the bumps to be periodically arranged, without requiring the bumps to have a specific logical connection pattern. Taking any one bump as the target bump, a wide line is extended based on the physical positional relationship between the target bump and the bumps to be connected, combined with the requirements of a preset shape. This wide line serves as the bottom edge parallel to a second direction.

[0020] Then, using each wide line as its base, multiple thin lines extend in orthogonal directions, naturally parallel to the first direction. These thin lines intersect each other with the minimum spacing specified in the design rules, forming interactive areas. The above method is used to obtain the corresponding interactive area for each bump. For each interactive area, its area is maximized to ensure the sum of the areas of all interactive areas is as large as possible, satisfying the maximum width requirement in the design rules. This fully utilizes space, avoids leaving large blank areas, enhances power supply quality, and flexibly adapts to different bump period arrangements. It does not require a regular logical connection between bumps, thus possessing high practicality. Attached Figure Description

[0021] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which: Figure 1 This is a schematic diagram of a traditional, exemplary orthogonal arrangement of bumps. Figure 2 This is a schematic diagram of another traditional, exemplary orthogonal arrangement of bumps; Figure 3 This is a schematic diagram of the first common orthogonal arrangement structure of the protrusions in the embodiments of this utility model; Figure 4 This is a schematic diagram of a second common orthogonal arrangement structure of protrusions in an embodiment of this utility model; Figure 5 This is a schematic diagram of the first common staggered arrangement structure of the protrusions in the embodiments of this utility model; Figure 6 This is a schematic diagram of a second common staggered arrangement structure of protrusions in an embodiment of this utility model; Figure 7 This corresponds to the embodiments of this utility model. Figure 4 A structural diagram of the target bump and the bump to be connected; Figure 8 This corresponds to the embodiments of this utility model. Figure 6 A structural diagram of the target bump and the bump to be connected; Figure 9 This corresponds to the embodiments of this utility model. Figure 3A schematic diagram of the structure extending from the wide lines; Figure 10 This corresponds to the embodiments of this utility model. Figure 6 A schematic diagram of the structure extending from the wide lines; Figure 11 This corresponds to the embodiments of this utility model. Figure 9 Schematic diagram of the structure with wide and thin lines; Figure 12 This corresponds to the embodiments of this utility model. Figure 10 Schematic diagram of the structure with wide and thin lines; Figure 13 This is a structural schematic diagram of an embodiment of the present invention when the fine wire is a zigzag-shaped metal wire; Figure 14 This corresponds to the embodiments of this utility model. Figure 9 , Figure 11 A schematic diagram of the structure after the orthogonal arrangement of protrusions extends into wide and thin lines; Figure 15 This corresponds to the embodiments of this utility model. Figure 10 , Figure 12 A schematic diagram of the structure after the staggered arrangement of protrusions extends into wide and thin lines; Figure 16 This corresponds to the embodiments of this utility model. Figure 14 The structural diagram shows orthogonally arranged protrusions extending into wide and thin lines, with the thin lines forming a fusion. Figure 17 This corresponds to the embodiments of this utility model. Figure 15 The structural diagram shows the interlaced protrusions extending into wide and thin lines, with the thin lines forming a fusion. Figure 18 This is a schematic diagram of an exemplary grouping and fusion connection structure in an embodiment of this utility model; Figure 19 This is an exemplary structural diagram of ungrouped fusion connection in an embodiment of this utility model. Detailed Implementation

[0022] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0023] The inventors discovered that most traditional RDL routing methods do not make full use of space, leaving a large amount of blank area. They can only provide power to the devices on the chip without improving noise reduction or other effects. A few methods improve the aforementioned problems, but they are only for structures with bump periodic arrangement and specific logical connections, such as logical connections where bumps are arranged in a specific orthogonal pattern and power (Powe) and ground (Gourd) are interleaved in a specific way.

[0024] Reference Figure 1 The diagram illustrates an exemplary orthogonal arrangement of bump structures, where B11~B1n and B31~B3n represent electrical circuits, and B21~B2n and Bm1~Bmn represent ground circuits. In this bump structure, electrical and ground circuits are spaced apart and orthogonally arranged. Furthermore, B11, B13, B31, and B33 correspond to power line VDD1; B12, B32, B1n, and B3n correspond to power line VDD2; B21, B23, Bm1, and Bm3 correspond to power line VSS1; and B22, Bm2, B2n, and Bmn correspond to power line VSS2. Thus, the bumps are arranged orthogonally, and electrical and ground circuits are logically connected in an alternating pattern. Current traditional RDL wiring methods have implemented wiring designs for this type of structure, providing power while improving noise levels.

[0025] However, traditional RDL routing methods cannot route periodically arranged, irregular logic connection structures. Periodic arrangement essentially refers to the periodic arrangement of physical locations, where the period refers to the cycle obtained by repeating a single bump as the smallest repeating unit. For example: Figure 2 The diagram shows another exemplary orthogonal arrangement of bumps. Although the bumps are also arranged periodically, B11 and B12 correspond to power lines VDD1, and B13~B1n-2 ( Figure 2 (Not shown in the image) Corresponding power lines VDD2 and B1n-1 ( Figure 2 (Not shown in the image), B1n corresponds to power line VDD1, B31 and B32 correspond to power line VDD1, B33~B3n correspond to power line VDD2, B21 corresponds to power line VSS1, B22~B2n correspond to power line VSS2, Bm1~Bm3 correspond to power line VSS1, Bm4 ( Figure 2 (Not shown in the diagram) ~Bmn corresponds to power line VSS2. Power and ground are not connected in any logical or predictable manner; traditional RDL wiring methods cannot handle this structure.

[0026] To address the aforementioned problems, the inventors, through extensive design, research, and testing, creatively proposed this utility model of a redistribution layer circuit and chip, effectively solving the aforementioned issues. The technical solution of this utility model will be explained and described in detail below.

[0027] Currently, there are various design rules in the industry for the routing of redistribution layer lines, such as the maximum line width and spacing of various types of lines. Based on these existing design rules, a first direction is first determined, which is the extension direction of the thin lines.

[0028] Theoretically, the first direction for routing the fine lines can be any direction. However, since the redistribution layer mainly realizes the interconnection between the bumps and the power network inside the chip, and considering the chip's own layout structure, the better approach to determining the first direction is to consider the main routing direction of the next layer of metal immediately adjacent to the redistribution layer. It can have any angle with the main routing direction of the next layer of metal immediately adjacent to the redistribution layer, but the optimal choice is to be orthogonal to the main routing direction of the next layer of metal immediately adjacent to the redistribution layer (generally referring to the next layer of metal immediately adjacent to the redistribution layer that will be connected to the redistribution layer through the connecting hole).

[0029] This is to achieve the best drilling effect between the redistribution layer and the next metal layer. Based on the current chip layout, if this orthogonal direction is taken as the first direction, it will generally not only allow all the fine lines to form a larger interactive area after the wiring is completed, but also make the overall wiring structure of the redistribution layer simpler and neater, with better drilling effect, which is beneficial for chip power supply or redistribution layer to transmit current to on-chip devices.

[0030] Naturally, it is understandable that if there are other methods, the determined first direction can achieve better results than the above, and those skilled in the art can determine the first direction based on the actual situation.

[0031] Once the first direction is determined, the second direction can be determined based on it. The second direction is orthogonal to the first direction. The determination of the second direction is primarily to define the extension direction of the wide lines. Since the thin lines extend from the wide lines as their bases, and the wide lines extend from the various protrusions (i.e., from inside the protrusions to outside), once the second direction is determined, corresponding wide lines can be extended from each protrusion according to this second direction, making the wide lines the bases of the thin lines, thus extending the thin lines. Based on the above, the redistribution layer circuit proposed in this utility model includes: multiple bumps, multiple wide lines, and multiple thin lines; the multiple bumps include: target bumps and at least one bump to be connected. After determining the first direction and the second direction, the wide lines of the target bump and the bump to be connected can be extended based on the physical positional relationship between them. Of course, the extension must be performed according to a preset shape; otherwise, the subsequently extended thin lines will not meet the design rules of the redistribution layer. The preset shape means that the bottom edge formed by the extension of the wide line from the target bump is parallel to the second direction, and the bottom edge formed by the extension of the wide line from the bump to be connected is also parallel to the second direction. The area of ​​the interactive region formed by the multiple first thin lines and multiple second thin lines between the two wide lines meets the preset requirement. This preset requirement means that the thin lines extended between each target bump and its corresponding bump to be connected intersect to form an interactive region, and the sum of the areas of all interactive regions is as large as possible, while also meeting the maximum width requirement in the design rules.

[0032] Understandably, if there is only one bump to be connected, the target bump and the bump to be connected each extend a wide line. If there are multiple bumps to be connected, then the target bump and each bump to be connected must extend their respective corresponding wide lines.

[0033] After the wide line is extended, it can be used as the bottom edge of the target bump and extended along the first direction. The extended first thin lines are orthogonal to the bottom edge. The wide line of the bump to be connected is used as the bottom edge and extended along the first direction. The extended second thin lines are orthogonal to the bottom edge. The multiple first thin lines and multiple second thin lines are intersected with each other with the minimum spacing of the design rules.

[0034] In one embodiment of this utility model, it is crucial to determine the target bump and the bump to be connected among multiple bumps. The target bump is configured such that any one bump is selected from the multiple bumps as the target bump. The bump to be connected is configured such that, based on the periodic arrangement of the multiple bumps and combined with the physical position of the target bump, the bump with sufficient interconnection space with the target bump among the multiple bumps that are close to the target bump in the target direction is selected as the connecting bump. The target direction refers to all directions around the target bump.

[0035] Understandably, while the logical connections of bumps can be arbitrary and irregular, their physical positions are periodically arranged. Therefore, any bump can be selected as the target bump. Combining this with the periodic arrangement of bumps, the physical positions of multiple bumps close to the target bump can be determined around it. Generally, the target bump will have adjacent bumps in multiple directions. In extreme cases, such as when the target bump is at its outermost corner, it will still have adjacent bumps in at least one direction. These adjacent bumps can all be considered as bumps to be determined.

[0036] After determining the physical location of the bump to be determined, at least one bump to be connected can be identified from among the multiple bumps to be determined. Specifically, this includes: First, based on the physical positions of multiple undetermined bumps and the physical position of the target bump, it is determined whether each undetermined bump is the closest bump in the target direction. The target direction is any direction surrounding the target bump. Looking at the redistribution layer from a top-down perspective, each target bump can have multiple directions around it. For example, a typical scenario would be eight directions: top, bottom, left, right, upper left, lower left, upper right, and lower right. These eight directions are considered the target directions. Combining the physical positions of the target bump with the undetermined bumps in these eight directions, at least one undetermined bump can be identified in each direction, resulting in a total of eight undetermined bumps in each direction. Naturally, it's understandable that if the target bump has an undetermined bump in only one direction and none in the other directions, then there would be only one undetermined bump in each direction.

[0037] Next, if any bump to be determined is the closest bump in the target direction, then it is determined whether there is sufficient interconnection space between the bump to be determined and the target bump. If any bump to be determined is the closest bump in the target direction and there is sufficient interconnection space between the bump to be determined and the target bump, then the bump to be determined is the bump to be connected; otherwise, the bump to be determined is not the bump to be connected. That is: if there is one bump to be determined in each direction of the target bump, but only the bump to be determined in the direction to the left of the target bump has sufficient interconnection space with the target bump, then the bump to be determined in the direction to the left of the target bump is determined as the bump to be connected, and the bumps to be determined in the other directions cannot be used as bumps to be connected.

[0038] In this context, "sufficient interconnect space" refers to the space available to complete the routing connection between the target bump and the bump to be connected using a line type that reaches or approaches the maximum linewidth of the redistribution layer. If the bump to be determined to the left of the target bump is the closest bump to the target bump to the left, but the routing space between them is too small to complete the routing connection using a line type that reaches or approaches the maximum linewidth of the redistribution layer, then it is considered that there is insufficient interconnect space between them, and the bump to be determined to the left of the target bump cannot be used as a bump to be connected.

[0039] To better understand the process of determining the bumps to be connected, we will use four common periodic bump arrangements as examples. (Refer to...) Figure 3 The diagram shown illustrates the first common orthogonal arrangement of protrusions. (Refer to...) Figure 4 The diagram shown illustrates the second common orthogonal arrangement of protrusions. (Refer to...) Figure 5 The diagram shown illustrates the first common type of staggered arrangement of protrusions. (Refer to...) Figure 6 The diagram shows a second common type of staggered arrangement of bumps. Figure 3-6 In the accompanying diagrams, P represents electricity and G represents ground. Figure 3 In the structure, rows P and G are aligned and arranged orthogonally. Figure 4 The middle section features alternating P and G rows, but the two rows are aligned, presenting an orthogonal arrangement. Figure 5 One line contains P and another contains G, but the two lines are not aligned and are arranged in an alternating pattern, like a honeycomb. Figure 6 The P and G symbols are arranged alternately, with the two rows not aligned, creating an interlaced layout, like a honeycomb.

[0040] For orthogonal arrangements, refer to Figure 7 The corresponding shown Figure 4 A schematic diagram of the target bump and the bump to be connected in the structure. Figure 7 The second P from left to right in the third row represents a target bump. There are a total of 8 bumps to be determined in all directions around it. The four bumps indicated by the solid black arrows and selected by the dashed box are the bumps to be connected. That is, the four bumps to the left of the target bump (P), to the right of the target bump (P), to the top of the target bump (G), and to the bottom of the target bump (G) are the bumps to be connected. The four bumps indicated by the dashed black arrows are the closest bumps in their corresponding directions, but because there is not enough interconnect space, they are not considered as bumps to be connected.

[0041] For staggered arrangements, refer to Figure 8 The corresponding shown Figure 6 A schematic diagram of the target bump and the bump to be connected in the structure. Figure 8The second G from left to right in the third row represents a target bump. There are a total of 8 bumps to be determined in all directions around it. The six bumps indicated by the solid black arrows and selected by the dashed box are the bumps to be connected. That is, the six bumps to the left of the target bump (P), to the right (P), to the top left (P), to the bottom left (G), to the top right (G), and to the bottom right (P) are the bumps to be connected. The bump indicated by the dashed black arrow, although it is the closest bump in its corresponding direction, is not considered as a bump to be connected because there is not enough interconnect space.

[0042] In one embodiment of this utility model, after determining the target bump and the bump to be connected in the aforementioned manner, the width line is configured based on the physical positional relationship between the target bump and the bump to be connected. This involves determining the extension direction of the width line corresponding to each of the target bump and the bump to be connected, and extending the corresponding width line according to their respective extension directions. The corresponding width line serves as the bottom edge, which is parallel to the second direction. The length of this bottom edge must reach or approach the width of the maximum linewidth of the redistribution layer. Specifically: Specifically, the width line configuration is as follows: based on the direction of the center line connecting the target bump and the bump to be connected, the extension direction of the corresponding width line for each bump is determined. That is, first, the direction of the center line connecting the target bump and the bump to be connected is determined according to their physical positional relationship. Then, if the center line is parallel to the first direction, the width line configuration is such that the target bump extends its width line in the direction of the center line, and the bump to be connected also extends its width line in the direction of the center line, both extending in the same direction while ensuring that the preset shape is met.

[0043] If the center line is parallel to the second direction, the wide line is configured such that, in the redistribution layer, among the selectable wiring directions, the target bump and the bump to be connected each select a direction that is not the second direction but is close to the second direction as the extension direction, and both extend in the direction of each other.

[0044] If the nearest direction is taken as the extension direction, and the extension direction cannot make the wide line provide a bottom edge parallel to the second direction, then the wide line is configured such that, on the premise of ensuring that the preset shape is met, the target bump is bent at a certain angle towards the direction of the bump to be connected as the extension direction corresponding to the target bump, and the bump to be connected is bent at a certain angle towards the direction of the target bump as the extension direction corresponding to the bump to be connected.

[0045] In the last case: if the center line is neither parallel to the first direction nor parallel to the second direction, the wide line is configured to find an available extension direction in other unoccupied wiring space in the redistribution layer, and determine whether the preset shape is satisfied after extending in that direction or after the zigzag line is extended at a certain angle. If it is satisfied, that direction is used as the extension direction.

[0046] Combination Figure 9 , Figure 10 This allows for a more intuitive understanding. (Refer to...) Figure 9 The corresponding shown Figure 3 A schematic diagram of the structure extending from the wide lines, see reference. Figure 10 The corresponding shown Figure 6 A schematic diagram of the structure extending from the wide lines. Figure 9 , Figure 10 All subsequent diagrams will use the horizontal direction as the first direction and the vertical direction as the second direction for illustration, and will not be repeated here.

[0047] Figure 9 For any bump, it has width lines S1 and S2, where the width line S1 is the center line parallel to the first direction. The extension direction of the width line corresponding to the bump is the direction of the center line, and it is the bottom edge parallel to the second direction. The length L1 of the bottom edge reaches or is close to the width of the maximum line width of the redistribution layer.

[0048] For the wide line S2, it is composed of S21 and S22. Since the center line is parallel to the second direction, among the available wiring directions in the redistribution layer, the nearest direction that is not the second direction but close to the second direction is selected as the extension direction, provided that the preset shape is met. That is, the wide line S22 is extended. Since the wide line S22 does not provide a bottom edge parallel to the second direction, the target bump is bent at a certain angle towards the direction of the bump to be connected, which is the extension direction corresponding to the target bump. The bump to be connected is bent at a certain angle towards the direction of the target bump, which is the extension direction corresponding to the bump to be connected, which is the wide line S21.

[0049] In addition, there is another scenario: the wide lines are configured such that, after extending their respective wide lines according to the extension directions of the target bump and the bump to be connected, and there is still remaining space that meets the target condition, a step structure is created at the bottom edge of the corresponding thin lines to be generated, thereby increasing the length of the corresponding wide lines as bottom edges. Here, the target condition refers to the fact that the area of ​​the interaction region already meets the preset requirements before adding the step structure. Figure 9 Since there is no remaining space after the wide lines S1 and S2 extend out, no stepped structure is made. Figure 10 An example of a stepped structure is shown in the figure.

[0050] Reference Figure 10As shown, for any bump, there are wide lines S1 and S2. The wide line S1 is composed of S11 and S12. Since the center line is parallel to the first direction, the extension direction of the wide line S11 corresponding to the bump is the direction of the center line. There is still remaining space, so a step structure S12 is added, which is used as the bottom edge parallel to the second direction. The length L1 of the bottom edge reaches or exceeds the width of the maximum line width of the redistribution layer.

[0051] For the wide line S2, since the center line is not parallel to the second direction, among the available routing directions in the redistribution layer, the nearest direction is selected as the extension direction to ensure that the preset shape is met, that is, to extend the wide line S2. The wide line S2 can provide a bottom edge parallel to the second direction. Therefore, it is not necessary for the target bump to bend at a certain angle towards the direction of the bump to be connected as the extension direction corresponding to the target bump, nor is it necessary for the bump to be connected to bend at a certain angle towards the direction of the target bump as the extension direction corresponding to the bump to be connected. Instead, it can be extended directly, that is, the wide line S2 is obtained.

[0052] A wide line extending from the target bump serves as the bottom edge, extending towards the bump to be connected. Multiple first thin lines extend from this bottom edge, orthogonal to it. Similarly, a wide line extending from the bump to be connected serves as the bottom edge, extending towards the target bump. Multiple second thin lines extend from this bottom edge, orthogonal to it. The first and second thin lines are staggered with a minimum spacing specified by design rules. This method achieves wiring between the target bump and at least one bump to be connected.

[0053] After extending the wide line through the aforementioned steps, since the wide line serves as the bottom edge and is parallel to the second direction, while the first and second directions are orthogonal, the multiple thin lines extending from the wide line as the bottom edge naturally also orthogonal to the wide line. That is: multiple first thin lines extend from the wide line extending from the target bump as the bottom edge towards the bump to be connected, and multiple second thin lines extend from the wide line extending from the bump to be connected as the bottom edge towards the target bump. Furthermore, the multiple first thin lines and the multiple second thin lines intersect each other with the minimum spacing specified in the design rules; and the area of ​​the interactive region formed by these intersects meets the preset requirements.

[0054] Reference Figure 11 The corresponding shown Figure 9 Schematic diagrams of the wide and thin lines of the structure, refer to... Figure 12 The corresponding shown Figure 10 Schematic diagram of the structure with wide lines and thin lines. Figure 11 , Figure 10 In Chinese, S represents a wide line and F represents a thin line. Figure 11 , 12The following figures illustrate the thin line using a long rectangular shape as an example. Preferred shapes for the thin line include long rectangular metal lines or zigzag metal lines. The thin line only needs to satisfy the characteristic of having a large area and small spacing after multiple thin lines intersect; it is not limited to being a long rectangle. For example... Figure 13 The broken-line metal wire shown has a broken-line shape, with the thin line F extending between the two wide lines S. The overall extension direction is the first direction, and after they intersect each other, they also have the characteristics of large area and small spacing.

[0055] In one embodiment of this utility model, the plurality of first thin lines and the plurality of second thin lines are configured such that, after each target bump and the bump to be connected extends its corresponding thin line, based on the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines, the interactive areas formed by the interlacing of the plurality of first thin lines and the plurality of second thin lines are either fused or not fused. Specifically: The multiple first thin lines and multiple second thin lines are configured such that, where the power lines corresponding to the multiple first thin lines and multiple second thin lines are all the same power line, the interactive areas formed by the intersecting multiple first thin lines and multiple second thin lines are fused together. That is, if the power lines corresponding to the bumps of the first thin lines and the second thin lines are the same power line, for example, both connected to VDD1 or both connected to VSS2, then the power lines corresponding to the two bumps are considered to be the same power line, and the interactive areas formed by the intersecting multiple first thin lines and multiple second thin lines are fused together. This makes the connection between adjacent bumps with the same power line more robust.

[0056] If the power lines corresponding to multiple first and second thin lines are not the same power line and are connected to ground respectively, the interactive area formed by the interlacing of multiple first and second thin lines is not merged. In this case, the interactive area formed by the interlacing of multiple first and second thin lines serves as a capacitive region between the two power lines. That is, if the power lines corresponding to the bumps of the first and second thin lines are connected to ground respectively, for example, the target bump is connected to VDD1 and the bump to be connected is connected to VSS2, etc., in this case, it is considered that the power lines corresponding to the two bumps are not the same power line, and therefore the multiple first and second thin lines are not merged. In this way, the interactive area formed by the interlacing of multiple first and second thin lines serves as a capacitive region between two power lines connected to ground. This capacitive region can modify the impedance curve of the PDN (Power Distribution Network, which refers to the power distribution network part including VRM, PCB, IC package and chip), filter the high-frequency current in the power network on the filter, thereby reducing power supply noise.

[0057] If multiple first and second thin lines correspond to power lines that are different lines of the same power or the same ground, then the interactive region formed by the intersecting first and second thin lines is not merged. This interactive region serves as the boundary between the voltage domains corresponding to the two power lines. In other words, if the power lines corresponding to the bumps of the first and second thin lines are of different power or ground, for example, if the target bump is connected to VDD1 and the bump to be connected is connected to VDD2, or the target bump is connected to VSS2 and the bump to be connected is connected to VSS1, then the power lines corresponding to the two bumps are considered to be of different power or ground, and therefore, the multiple first and second thin lines are not merged. This interactive region, where multiple first and second thin lines intersect, serves as the boundary between the voltage domains corresponding to two power lines of different power or ground. This boundary prevents short circuits between bumps, eliminating the need for designers to manually handle voltage domain boundaries and improving the implementation efficiency of the redistribution layer.

[0058] In one embodiment of this utility model, after either merging or not merging the interactive areas formed by the intersecting of multiple first thin lines and multiple second thin lines, the thin lines are further configured such that, between the remaining protrusions (excluding the target protrusion and the protrusion to be connected), or between each protrusion extending a wide line, or between each protrusion extending a wide line to another protrusion, there are areas where corresponding thin lines can be extended, and corresponding wide lines already exist. In this case, the corresponding wide line is used as the bottom edge, and multiple corresponding thin lines are extended in the first direction to intersect and form an interactive area. Alternatively, although there are areas where corresponding thin lines can be extended, there are no corresponding wide lines. In this case, a wide line needs to be extended at the corresponding position, used as the bottom edge, and multiple corresponding thin lines are extended in the first direction to intersect and form an interactive area. This method maximizes the area of ​​the interactive area, ensuring that the sum of the areas of all interactive areas is as large as possible and meets the maximum width requirement in the design rules.

[0059] Reference Figure 14 The corresponding shown Figure 9 , Figure 11 A schematic diagram of the structure after the orthogonal arrangement of protrusions extends into wide and thin lines, see reference. Figure 15 The corresponding shown Figure 10 , Figure 12 A schematic diagram of the structure after the staggered arrangement of protrusions extends into wide and thin lines. Figure 14 The dashed box represents the area around the target bump (excluding the bump to be connected), where there is a region with the target bump where corresponding thin lines can extend, and the interactive area where the thin lines extend. Figure 15 There are no areas around the target bump, excluding the bump to be connected, where corresponding thin lines can extend from the target bump. (Combined) Figure 14, 15 It can be seen that the redistribution layer circuit structure implemented by the method proposed in this utility model can lead out a bump trace to a location close to an adjacent bump. This is equivalent to a relatively wide distribution of the redistribution layer wiring connecting any bump. This helps to reduce the length of the current flowing through the lower metal path when the bump supplies power to the on-chip unit, thereby optimizing the static voltage drop of the overall structure.

[0060] Reference Figure 16 The corresponding shown Figure 14 The structural diagram shows orthogonally arranged protrusions extending into wide and thin lines, with the thin lines merging them. (Refer to the diagram.) Figure 17 The corresponding shown Figure 15 The structural diagram shows the interlaced protrusions extending into wide and thin lines, with the thin lines forming a fusion. Figure 16 , 17 The dashed boxes represent the areas where the target bump and the bump to be connected extend corresponding thin lines for merging. The interior of these areas is also filled with dotted shadows to represent the metal lines of the redistribution layer. The thin lines that are not merged have gaps between them, represented by blank spaces.

[0061] In one embodiment of this utility model, the plurality of first thin lines and the plurality of second thin lines are further configured such that, during fusion connection, the areas between the plurality of first thin lines and the plurality of second thin lines, as well as the areas between each thin line and the wide line, need to be filled with the metal lines of the redistribution layer. During filling, if a wide line serves as the bottom edge and its corresponding length is greater than the maximum line width in the redistribution layer design rules, then the plurality of first thin lines and the plurality of second thin lines are divided into several groups on an even basis. The combined width of all thin lines and their filling metal lines in each group is not greater than the maximum line width in the redistribution layer design rules, and gaps are maintained between each group.

[0062] Reference Figure 18 The diagram shows an exemplary structure for merging and connecting groups, with reference to... Figure 19 The diagram shows an exemplary structure for ungrouped fusion connections. Figure 18 In this design, multiple first and second thin lines are evenly divided into two groups, with a gap A between the two groups. The gaps between the thin lines in the upper group are filled with metal wires from the redistribution layer, and the gaps between the thin lines in the lower group are also filled with metal wires from the redistribution layer. The combined width of all thin lines and their filling metal wires in each group does not exceed the maximum line width specified in the redistribution layer design rules. Figure 19 Without grouping, all the thin lines are directly filled with the metal lines of the redistribution layer, making the total width of the area greater than the maximum line width in the redistribution layer design rules. This will cause a design violation and should be avoided.

[0063] Based on the redistribution layer circuitry described above, this utility model embodiment also proposes a chip, the chip comprising: the redistribution layer circuitry as described in any of the preceding claims.

[0064] Through the above examples, this utility model creatively proposes a novel redistribution layer circuit for periodically arranged bumps in flip-chip packaging technology. This circuit only requires the bumps to be periodically arranged, without requiring the bumps to have a specific logical connection. Taking any one bump as the target bump, a wide line is extended based on the physical positional relationship between the target bump and the bump to be connected, combined with the requirements of a preset shape. This wide line serves as the bottom edge parallel to the second direction.

[0065] Then, using each wide line as its base, multiple thin lines extend in orthogonal directions, naturally parallel to the first direction. These thin lines intersect each other with the minimum spacing specified in the design rules, forming interactive areas. The above method is used to obtain the corresponding interactive area for each bump. For each interactive area, its area is maximized to ensure the sum of the areas of all interactive areas is as large as possible, satisfying the maximum width requirement in the design rules. This fully utilizes space, avoids leaving large blank areas, enhances power supply quality, and flexibly adapts to different bump period arrangements, without requiring a regular logical connection between the bumps.

[0066] By extending wide and thin lines onto any bump using the method proposed in this invention to form a circuit structure, the redistribution layer wiring process of breaking down the whole into parts is realized, ensuring that the power lines of the redistribution layer are automatically consistent with the power lines of the bump. For intersecting thin lines corresponding to power lines of different voltages or grounds, the boundaries are automatically defined, preventing short circuits and other problems. Designers do not need to manually handle voltage domain boundaries, thus improving the efficiency of the redistribution layer implementation.

[0067] For interlaced thin lines corresponding to the same power line, they are merged and connected to achieve a robust interconnect structure similar to wide lines, which is beneficial for power transmission. For interlaced thin lines corresponding to power and ground lines, an in-layer capacitance region is formed. This capacitance region can modify the PDN impedance curve and reduce the high-frequency current in the power network on the filter, thereby reducing power supply noise.

[0068] In addition, a bump trace can be led out to a location close to an adjacent bump, which means that the wiring distribution of the redistribution layer connecting any bump is relatively wide. This helps to reduce the length of the current flowing through the lower metal layer when the bump supplies power to the on-chip unit, thereby optimizing the static voltage drop of the overall structure and making it highly practical.

[0069] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.

[0070] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.

[0071] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.

Claims

1. A redistribution layer circuit, characterized in that, The redistribution layer circuitry includes: multiple bumps, multiple wide lines, and multiple thin lines; The plurality of bumps includes: a target bump and at least one bump to be connected; Based on their physical positional relationship, the target bump and the bump to be connected each extend a corresponding wide line according to a preset shape. Using the wide line extending from the target protrusion as the bottom edge, it extends along the first direction, and the extended first thin lines are orthogonal to the bottom edge; Using the wide line extending from the protrusion to be connected as the bottom edge, it extends along the first direction. Multiple second thin lines extend orthogonally to the bottom edge. The multiple first thin lines and the multiple second thin lines are staggered with each other at the minimum spacing of the design rules. The preset shape is as follows: the bottom edge formed by the target bump extending a wide line is parallel to the second direction, the bottom edge formed by the bump to be connected extending a wide line is also parallel to the second direction, and the area of ​​the interactive region formed by the multiple first thin lines and multiple second thin lines between the two wide lines meets the preset requirements. The preset requirements are: the thin lines extended between each target bump and its corresponding bump to be connected intersect to form an interactive region, the sum of the areas of all interactive regions is as large as possible, and the maximum width requirement in the design rules is met.

2. The redistribution layer circuit according to claim 1, characterized in that, The target bump is configured such that one bump is selected from a plurality of periodically arranged bumps as the target bump; The bump to be connected is configured such that, based on the periodic arrangement of the multiple bumps and combined with the physical position of the target bump, the bump with sufficient interconnection space with the target bump among the multiple bumps that are close to the target bump in the target direction is used as the connecting bump, and the target direction is the various directions around the target bump; The sufficient interconnect space refers to the space that allows for wiring connections between the target bump and the bump to be connected, using a line type that reaches or approaches the maximum linewidth of the redistribution layer.

3. The redistribution layer circuit according to claim 1, characterized in that, The wide line configuration is as follows: based on the physical positional relationship between the target bump and the bump to be connected, the extension direction of the corresponding wide line of the target bump and the bump to be connected is determined, and the corresponding wide line is extended according to the extension direction of the target bump and the bump to be connected. The corresponding wide line serves as the bottom edge, which is parallel to the second direction, and the length of the bottom edge needs to reach or be close to the width of the maximum line width of the redistribution layer.

4. The redistribution layer circuit according to claim 3, characterized in that, The width line configuration is based on the direction of the center line connecting the target bump and the bump to be connected, determining the extension direction of the width line corresponding to each of the target bump and the bump to be connected; specifically including: If the center line is parallel to the first direction, the width line is configured such that the target bump extends its width line in the direction of the center line, and the bump to be connected also extends its width line in the direction of the center line, while ensuring that the preset shape is met. If the center line is parallel to the second direction, then the wide line is configured such that, among the selectable wiring directions in the redistribution layer, the target bump and the bump to be connected each select a direction that is not the second direction but is close to the second direction as their respective extension direction, provided that the preset shape is met. If the nearest direction is taken as the extension direction, and the extension direction cannot make the wide line provide a bottom edge parallel to the second direction, then the wide line is configured such that, on the premise of ensuring that the preset shape is met, the target bump is bent at a certain angle towards the direction of the bump to be connected as the extension direction corresponding to the target bump, and the bump to be connected is bent at a certain angle towards the direction of the target bump as the extension direction corresponding to the bump to be connected. If the center line is neither parallel to the first direction nor parallel to the second direction, the wide line is configured to find an available extension direction in other unoccupied wiring space in the redistribution layer, and determine whether the preset shape is satisfied after extending in that direction or after the zigzag line is extended at a certain angle. If it is satisfied, that direction is used as the extension direction.

5. The redistribution layer circuit according to claim 3, characterized in that, The wide line is further configured such that, after extending the corresponding wide lines according to the respective extension directions of the target bump and the bump to be connected, and there is still remaining space and the remaining space satisfies the target condition, a step structure is made at the bottom edge of the corresponding thin line to be generated, so as to increase the length of the corresponding wide line as the bottom edge. The target condition refers to the fact that the area of ​​the interactive area already meets the preset requirements before the step structure is added.

6. The redistribution layer circuit according to claim 1, characterized in that, The multiple first thin wires and multiple second thin wires are configured such that, based on the power lines corresponding to the multiple first thin wires and multiple second thin wires, the interactive areas formed by the interlacing of the multiple first thin wires and multiple second thin wires are either fused or not fused.

7. The redistribution layer circuit according to claim 6, characterized in that, The plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are all the same power line, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines is fused and connected. The plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are not the same power line and are one power and one ground, the interaction area formed by the plurality of first thin lines and the plurality of second thin lines intersecting each other is not fused and connected. In this case, the interaction area formed by the plurality of first thin lines and the plurality of second thin lines intersecting each other serves as a capacitor area between two power lines. The plurality of first thin lines and the plurality of second thin lines are configured such that, when the power lines corresponding to the plurality of first thin lines and the plurality of second thin lines are different lines that are both electrical or both ground, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines is not fused and connected. In this case, the interaction area formed by the mutual intersection of the plurality of first thin lines and the plurality of second thin lines serves as the boundary of the voltage domain corresponding to the two power lines.

8. The redistribution layer circuit according to claim 7, characterized in that, After either merging or not merging the interactive areas formed by the intersecting of multiple first thin lines and multiple second thin lines, the thin lines are further configured such that, between the remaining protrusions other than the target protrusion and the protrusion to be connected, or between each protrusion extending a wide line, or between each protrusion extending a wide line to another protrusion, there are areas where corresponding thin lines can extend, and corresponding wide lines already exist. Then, using the corresponding wide line as the bottom edge, multiple corresponding thin lines extend in the first direction, intersecting to form interactive areas; or... If there is a region where corresponding thin lines can be extended but there are no corresponding wide lines, then a wide line is extended at the corresponding position, which is used as the bottom edge, and multiple corresponding thin lines are extended in the first direction to intersect and form an interactive region.

9. The redistribution layer circuit according to claim 7, characterized in that, The plurality of first thin lines and the plurality of second thin lines are configured such that, during the fusion connection, the regions between the plurality of first thin lines and the plurality of second thin lines, as well as the regions between each thin line and the wide line, are filled with the metal lines of the redistribution layer; and, during filling, if a wide line serves as the bottom edge and its corresponding length is greater than the maximum line width in the redistribution layer design rules, then the plurality of first thin lines and the plurality of second thin lines are divided into several groups on an even basis, wherein the width of all thin lines and their filling metal lines in each group is not greater than the width of the maximum line width in the redistribution layer design rules, and gaps are reserved between each group.

10. The redistribution layer circuit according to claim 1, characterized in that, The plurality of the thin lines include: long rectangular metal lines or zigzag metal lines; The multiple thin lines must satisfy the characteristics of having a large area and small spacing after they intersect each other.

11. The redistribution layer circuit according to claim 1, characterized in that, The first direction has an arbitrary angle with the main wiring direction of the next layer of metal adjacent to the redistribution layer.

12. The redistribution layer circuit according to claim 1, characterized in that, The first direction is orthogonal to the main wiring direction of the next layer of metal adjacent to the redistribution layer.

13. A chip, characterized in that, The chip includes: a redistribution layer circuit as described in any one of claims 1-12.

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