Semiconductor package and processor module

Abstract

The utility model provides a kind of semiconductor packaging and processor module.Semiconductor packaging includes semiconductor die and thermal interface film on semiconductor die.The thermal interface film includes at least first layer and second layer.The first layer includes vertically oriented graphite and the second layer includes horizontally oriented graphite.

Description

Technical Field

[0001] This utility model relates to a package, and more particularly to a semiconductor package and processor module. Background Technology

[0002] Various computer applications require the use of large amounts of computer processors. Examples of such applications include high-performance computing (HPC), cloud computing, data centers, and artificial intelligence. Cooling the computer processors is essential during operation. Utility Model Content

[0003] This invention provides a semiconductor package including a semiconductor die and a thermal interface film on the semiconductor die. The thermal interface film includes at least a first layer and a second layer. The first layer includes vertically oriented graphite and the second layer includes horizontally oriented graphite.

[0004] A processor module according to this invention includes a semiconductor die, a thermal interface film on the semiconductor die, and a heat sink on the thermal interface film. The thermal interface film is a single layer comprising graphite oriented in a first volume and graphite oriented in a second volume, wherein the first volume is different from the second volume.

[0005] Based on the above, the use of a thermal interface film in the embodiments of this invention can more quickly distribute the heat generated by the semiconductor die to a larger surface area, thereby improving heat conduction efficiency. Therefore, the heat distribution in the semiconductor package is more uniform. This also reduces heat accumulation on the semiconductor die, thereby increasing the lifespan of the semiconductor chip.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a cross-sectional view of one embodiment of a processor module according to some embodiments of the present invention. The module includes a semiconductor package and a heat sink. A thermal interface film is used to more effectively transfer heat from the semiconductor package to the heat sink;

[0008] Figure 2A This is a cross-sectional view of a thermal interface film according to some embodiments of the present invention. This embodiment has three layers, with a horizontally oriented graphite layer located between the other two layers;

[0009] Figure 2B This is a first planar view showing the thermal interface film relative to the semiconductor die and two memory chips;

[0010] Figure 2CThis is a second planar view showing the thermal interface film relative to the semiconductor die and additional memory chip;

[0011] Figure 3A It is a cross-sectional view showing layers of vertically oriented graphite;

[0012] Figure 3B It is a cross-sectional view showing layers of horizontally oriented graphite;

[0013] Figure 4A This is a cross-sectional view of another embodiment of the thermal interface film. In this three-layer embodiment, the first layer with vertically oriented graphite is thicker than the third layer with vertically oriented graphite;

[0014] Figure 4B This is a cross-sectional view of another embodiment of the thermal interface film. In this three-layer embodiment, the third layer with vertically oriented graphite is thicker than the first layer with vertically oriented graphite;

[0015] Figure 5A This is a cross-sectional view of another embodiment of the thermal interface film. In this embodiment, horizontally oriented graphite exists only in a portion of the layer above the semiconductor grains;

[0016] Figure 5B It is a planar view showing the thermal interface thin film relative to the semiconductor die and two memory chips;

[0017] Figure 6A This is a cross-sectional view of another embodiment of a thermal interface thin film. In this embodiment, horizontally oriented graphite is present in the peripheral region of the layer above one or more edge regions of the semiconductor grain;

[0018] Figure 6B It is a planar view showing the thermal interface thin film relative to the semiconductor die and two memory chips;

[0019] Figure 7A This is a cross-sectional view of another embodiment of the thermal interface film according to some embodiments of the present invention. This embodiment has two layers, with a horizontally oriented graphite layer located below a vertically oriented graphite layer;

[0020] Figure 7B This is a cross-sectional view of another embodiment of a two-layer thermal interface film, wherein a horizontally oriented graphite layer is located above a vertically oriented graphite layer.

[0021] Figure 8A This is a cross-sectional view of another embodiment of the thermal interface film. In this embodiment, the film is a monolayer comprising vertically oriented graphite and horizontally oriented graphite;

[0022] Figure 8B It is a planar view showing the thermal interface thin film relative to the semiconductor die and two memory chips;

[0023] Figure 9 This is a cross-sectional view of another embodiment of the processor module according to some embodiments of the present invention. In this embodiment, the thermal interface film directly contacts the semiconductor die and the heat sink;

[0024] Figure 10 This is a cross-sectional view of another embodiment of the processor module according to some embodiments of the present invention. In this embodiment, the semiconductor package includes a semiconductor die and a cap. A first thermal interface film is located between the semiconductor die and the cap. A second thermal interface film is located between the cap and a heat sink;

[0025] Figure 11 This is a flowchart illustrating a method for fabricating a thermal interface film according to some embodiments;

[0026] Figure 12 This is a flowchart illustrating a method for manufacturing a processor module according to some embodiments;

[0027] Figure 13 This is a schematic diagram of a group of servers in a data center and a diagram of the connection of a real-time monitoring system used to monitor the health status of processor modules in the data center. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples to implement different features of the provided object. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, the present invention may reuse reference numerals and / or letters in various instances. Such reuse is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, this document may use spatially relative terms such as “below,” “under,” “lower,” “above,” and “upper” to describe the relationship or characteristics of one component or feature to another, as shown in the figures. In addition to the orientations depicted in the figures, spatially relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise) and the spatially relative descriptors used herein may be interpreted accordingly.

[0030] The numerical values ​​in this specification and claims should be understood to include values ​​that remain the same when reduced to the same number of significant figures, as well as values ​​that differ from those determined by experimental errors less than those of conventional measurement techniques of the type described in this invention. All scopes of this invention include the endpoints of the numerical values.

[0031] The term "about" can be used to include any numerical value that can vary without altering its fundamental function. When used with a range, "about" also reveals a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also reveals a range "from 2 to 4". The term "about" can refer to a numerical value ±10%.

[0032] This invention relates to structures composed of different layers. When the terms "on," "upon," or "over" are used to refer to two different layers (including a substrate), they simply mean that one layer is on, on, or over another layer. These terms do not require that the two layers be in direct contact with each other and allow other layers to be located between them. For example, all layers of the structure can be considered to be "on" the substrate, even if they are not all in direct contact with the substrate. The term "direct" can be used to indicate that two layers are in direct contact with each other, with no layer between them. Furthermore, when referring to performing process steps on or on a substrate, this should be interpreted as performing such steps on any layers that may be present on the substrate, depending on the context.

[0033] The term "semiconductor die" used in this invention refers to a substrate having one or more integrated circuits, and is also commonly referred to as a chip or microchip.

[0034] As used in this invention, the term "semiconductor package" refers to a combination of one or more semiconductor dies and one or more interconnect layers that allow an integrated circuit to communicate with one or more other packages. Examples of interconnect layers may include redistribution layers (RDLs) or interposers having bonding pads or C4 bumps or pillars.

[0035] This invention relates to a processor module with improved heat transfer efficiency to increase heat dissipation. Semiconductor dies can be packaged in many different ways, such as package-on-package (PoP), where two semiconductor packages are stacked on top of each other, or chip-on-wafer-on-substrate (CoWoS), where the semiconductor die is attached to a wafer (e.g., an interposer), and then the wafer is attached to a substrate (e.g., a printed circuit board). These can also be referred to as three-dimensional integrated circuit (3DIC) devices.

[0036] Heat dissipation during operation remains a concern. Prolonged exposure to excessively high temperatures can reduce the reliability and lifespan of semiconductor chips. To address this, a thermal interface material (TIM) is applied to the semiconductor chip to improve thermal coupling with the heat sink. The heat sink can be secured in place relative to the chip using a fastening system, such as clamps or screws. In some TIM processes, the chip is exposed within the package, and the TIM is applied between the chip and the heat sink. In other TIM processes, the package includes a cover (which acts as a heat diffuser to dissipate heat over a larger surface area), and the TIM is applied between the cover and the heat sink. However, TIMs and covers are often ineffective at dissipating heat, which is primarily generated by the semiconductor chip (compared to other components such as memory). For example, SUS304 (a stainless steel alloy commonly used in covers) has a thermal conductivity of only about 14-17 W / m·K. As a result, heat remains above the semiconductor chip, reducing its lifespan. In this invention, a thermal interface film is used, which acts as a good heat diffuser to diffuse and dissipate heat energy more evenly, thereby extending the lifespan of semiconductor chips.

[0037] Figure 1 This is a cross-sectional view of one embodiment of the processor module 100 of this utility model. First, a semiconductor package 110 is shown. Here, the package includes a semiconductor die 120 in the form of a system-on-a-chip (SoC). On the SoC, many electronic components are combined on a common substrate. The SoC contains a semiconductor die, shown here located between two memory chips 130. Compared to the memory chips 130, the SoC 120 generates a relatively large amount of heat. The SoC may include, for example, a central processing unit (CPU) or a graphics processing unit (GPU). The memory chips may be, for example, high-bandwidth memory (HBM). Other electronic components may also be present. Typically, any number of dies / chips may be present in the package 110 and the processor module 100. The sides of the SoC 120 may be surrounded by molding compound or encapsulation material 140.

[0038] The SoC 120 is bonded to the top surface of the wafer 102 via a first inline layer 142, which includes, for example, electrical contacts such as pads, balls, pins, bumps, pillars, or other similar structures. The wafer 102 may be an interposer substrate formed from a semiconductor substrate such as silicon. Sometimes, active devices (such as transistors) and passive devices (such as resistors or capacitors) are formed on the wafer surface. The wafer may also include through-hole vias.

[0039] Wafer 102 is then bonded to the top surface of substrate 104 to obtain semiconductor package 110, shown here as chip-on-wafer-on-substrate (CoWoS). This can also be accomplished by a second inline layer 144 containing electrical contacts such as pads, balls, pins, bumps, pillars, or other similar structures. Substrate 104 can be, for example, a printed circuit board (PCB) or the like. Substrate 104 may also again include other active or passive devices. An underfill material 146 is shown here between SoC 120 and wafer 102, and between wafer 102 and substrate 104. An inline layer (not shown) may also be included on the back side of the substrate, which will be used to connect the semiconductor package to the motherboard.

[0040] Continuing, a thermal interface film 200 is placed on top of the semiconductor package 110 to improve thermal coupling. This film may be referred to herein as a first or inner TIM layer. In some embodiments, the thickness of the first TIM layer may range from 50 micrometers (μm) to about 3 millimeters (mm), although other ranges are also within the scope of this invention. The thermal interface film will be discussed in more detail later.

[0041] Adhesive 148 is also applied to substrate 104 and around SoC 120. Adhesive 148 may be, for example, epoxy resin, or silicone resin, glue, or other adhesive suitable for semiconductor devices.

[0042] A cover 150 is attached to the substrate 104 and covers the semiconductor die 120. The cover 150 both physically protects the semiconductor die 120 and acts as a heat sink to dissipate heat generated by the SoC over its larger surface area. The cover 150 is typically made of a material with high thermal conductivity, such as aluminum, steel, stainless steel, copper, and other similar materials. The cover 150 is secured to the wafer using an adhesive 148. The adhesive 148 may require heat to be applied at an appropriate temperature for a suitable time to cure. The cover 150 may also be considered part of the semiconductor package 110.

[0043] A second thermal interface material layer 152 is placed on the cover 150, thermally coupling the cover 150 to the heat sink 154. Suitable thermal interface materials may include polymers, which may contain thermally conductive fillers. Some non-limiting examples of thermally conductive fillers may include alumina, boron nitride, aluminum nitride, aluminum, copper, silver, and indium. The thermal interface material may be a thin film or sheet, including, for example, carbon nanotubes (CNTs) or graphite. The thermal interface material may be in the form of a solid pad, paste, gel, grease, or phase change material. The thermal interface material may be continuously applied to the cover.

[0044] The heat sink 154 is placed on top of the second thermal interface material layer. The heat sink 154 may be made of materials such as aluminum or copper. The heat sink 154 may include heat dissipation fins to increase the surface area. The heat sink 154 may be secured to the semiconductor package by appropriate means, such as clamps or screws.

[0045] The combination of semiconductor package 110 and heat sink 154 is referred to herein as processor module 100. It should be noted that this invention also extends to bare die packages excluding the cover and therefore having only one TIM layer instead of two TIM layers; such combinations are also considered processor modules within the scope of this invention.

[0046] Although not illustrated, each processor module may also include an internal cache, memory, input / output controllers, a bus for transferring data, and other similar components. Channels may include a system bus, network connectivity, wired and wireless systems. Each processor module may include one or more cores. Each processor module executes instructions according to the required software / program.

[0047] Now refer to Figure 2A The side cross-sectional view illustrates the thermal interface film 200 of this embodiment, which is a sandwich structure consisting of three layers: a first layer 210, a second layer 220, and a third layer 230. The second layer 220 is located between the first layer 210 and the third layer 230 and is in direct contact with the first layer 210 and the third layer 230. Each layer contains graphite.

[0048] In the first layer 210 and the third layer 230, graphite is vertically oriented, as shown in reference numeral 202. Horizontally oriented graphite is present in these two layers only in a very small amount relative to the vertically oriented graphite (at most 5% by weight of the graphite in the layer). In the second layer 220, graphite is horizontally oriented, as shown in reference numeral 204. Vertically oriented graphite is present in the second layer only in a very small amount relative to the horizontally oriented graphite (at most 5% by weight of the graphite in the layer). More generally, graphite 202 in the first layer 210 and the third layer 230 is oriented in a first plane or volume, and graphite 204 in the second layer 220 is oriented in a second plane or volume different from the first plane or volume.

[0049] In this regard, graphite exhibits high thermal conductivity in the in-plane direction but poor thermal conductivity in the out-of-plane direction. The in-plane thermal conductivity of graphite starts from ~400 W / m·K and can be even higher. The term "vertical orientation" indicates that the direction of high thermal conductivity is along the Z-axis away from the semiconductor die towards the heat sink 154. In other words, the in-plane orientation of graphite is from the semiconductor die towards the heat sink, or from the out-of-plane direction of the thermal interface film itself. The term "horizontal orientation" indicates that the direction of high thermal conductivity is along the Y-axis (and X-axis) from the semiconductor die towards the package side. The in-plane orientation of graphite is in the plane of the thermal interface film. Therefore, vertically oriented graphite layers rapidly transfer heat from the semiconductor die to the cover and heat sink, while horizontally oriented graphite layers rapidly diffuse heat from the semiconductor die to a larger surface area (e.g., the surface area on a memory chip, where the operating temperature is significantly lower).

[0050] Graphite in thermal interface thin films typically exists in the form of flakes or flakes, at least 100 nanometers in height, and possesses properties different from stacked graphene. It is important to note that individual graphite flakes are considered as a whole. For example, each graphite flake is not required to extend completely across the entire length / width / height of a given layer. This is illustrated here using short or long lines. Overall, heat can be transferred more rapidly along the in-plane direction of the graphite.

[0051] Continuing, each layer of the thermal interface film may also individually contain an adhesive resin or polymer resin 206, with graphite dispersed therein. Suitable polymer resins typically have high melting points to accommodate the high operating temperatures of the semiconductor grains. Some non-limiting examples of suitable polymer resins may include silicone resins, polyetherimide (PEI), polyetheretherketone (PEEK), polytetrafluoroethylene (PTFE), polybenzimidazole (PBI), polyimide (PI), polyphenylene sulfide (PPS), polyethersulfone (PES), certain polyethylenes such as HDPE, polypropylene, polyethylene terephthalate (PET), polybutylene terephthalate (PBT), and epoxy resins. However, the presence of a polymer resin is not necessarily required. For example, pyrolytic graphite sheets can be used as layers containing vertically oriented graphite.

[0052] Continue to refer to Figure 2A The first layer 210 has a first height H1. The second layer 220 has a second height H2. The third layer 230 has a third height H3. In a particular embodiment, the second height H2 is less than the first height H1. In other particular embodiments, the second height H2 is less than the third height H3. In other words, the ratio of the second height H2 to the first height H1 and the ratio of the second height H2 to the third height H3 are between zero and one. As shown here, the first height H1 and the third height H3 are approximately equal.

[0053] In some embodiments, the first height H1 and the third height H3 may independently range from about 40 micrometers (μm) to about 200 micrometers. In some embodiments, H2 may vary from about 5 micrometers (μm) to about 100 micrometers. Combinations of these heights are taken into account, and other ranges and values ​​are also within the scope of this invention.

[0054] Figure 2B It is along Figure 2A Plan view of the BB line. The length 112 and width 114 of semiconductor package 110 are shown. Semiconductor die 120 and two memory chips 130 are also shown. Semiconductor die 120 has a length 122 and width 124. Similarly, each memory chip 130 has a length 132 and width 134. The semiconductor package can be considered as having a length greater than its width.

[0055] In a particular embodiment, the length 122 of the semiconductor die is approximately 20 millimeters (mm) to approximately 70 millimeters. In a particular embodiment, the width 124 of the semiconductor die is approximately 5 millimeters (mm) to approximately 50 millimeters. Combinations of these values ​​are taken into account, and other ranges and values ​​are also within the scope of this invention.

[0056] In a particular embodiment, the length 132 of each memory chip is approximately 5 mm to approximately 30 mm. In a particular embodiment, the width 134 of each memory chip is approximately 5 mm to approximately 30 mm. Combinations of these values ​​are taken into account, and other ranges and values ​​are also within the scope of this invention. It is worth noting that the length 112 and width 114 of the semiconductor package are greater than the individual length and width of the semiconductor die or memory chip.

[0057] Continue to refer to Figure 2B The horizontally oriented graphite 204 is illustrated here as oriented only along the Y-axis. Typically, it is desirable for graphite to cover both high-heat and low-heat regions (heat measured relative to each other). For example, here, graphite covers the high-heat semiconductor die 120 and two low-heat memory chips 130. The second layer 220 of the thermal interface film is shown here as having a size approximately equal to that of the semiconductor package.

[0058] However, Figure 2C The plan view illustrates one embodiment in which horizontally oriented graphite 204 is depicted oriented along both the Y and X axes. This embodiment may be useful, for example, when a semiconductor package has additional surface area along both the Y and X axes. For example, in this illustration, an additional memory chip 130 is present around the semiconductor die 120.

[0059] Now refer to Figure 3AThe plane of graphite can have an angle θ1 measured relative to the vertical axis 102. If the angle θ1 is between 0° and 15°, the graphite can be considered vertically oriented. Similarly, refer to... Figure 3B The plane of graphite may have an angle θ2 measured relative to the horizontal axis 104. If the angle θ2 is between 0° and 30°, the graphite may be considered horizontally oriented. More generally, the angle formed between the first plane or volume and the second plane or volume is at least 45°.

[0060] Figure 4A and Figure 4B Two additional embodiments of a three-layer thermal interface film 200 having the previously described layers 210, 220, and 230 are described. First, refer to... Figure 4A As shown here, the first height H1 is greater than the third height H3. This may be useful if the lid surface has a high surface roughness. See next... Figure 4B As shown here, the third height H3 is greater than the first height H1. This can be useful if the surface of the semiconductor die and / or memory chip has a high surface roughness.

[0061] Figure 5A and Figure 5B Another embodiment of the thermal interface film is described. In this embodiment, the horizontally oriented graphite 204 in the second layer 220 is not dispersed throughout the entire layer, but rather exists in specific portions of the layer. Figure 5A In the semiconductor die 120, the semiconductor package 110 has a length of 122, and the semiconductor package 110 has a length of 112. Horizontally oriented graphite is located within a length 226, which is greater than the length of the semiconductor die 122 but less than the length of the semiconductor package 112. Two empty regions 228 are indicated. In a particular embodiment, the amount of graphite in the empty regions (by mass) is at least 10 times less than the amount of graphite in other portions of the layer. Figure 5B yes Figure 5A Plan view of the BB line. As can be seen more clearly here, this embodiment still allows heat to diffuse from the entire semiconductor die 120 to the surface area above the memory chip 130.

[0062] exist Figure 6A and Figure 6B In the illustrated embodiment, the horizontally oriented graphite in the second layer 220 is again not dispersed throughout the entire layer. Similarly, Figure 6B yes Figure 6AA plan view of the BB line. As shown here, the semiconductor die 120 can be considered to have at least one edge region 126. Two such edge regions 126 are shown here. The second layer 220 has one or more peripheral regions 222 and a central region 224. Horizontally oriented graphite 204 is present in the peripheral regions 222 but not in the central region 224, i.e., the central region is an empty region. In the cross-sectional view, the peripheral regions 222 of the second layer overlap with the edge regions 126 of the semiconductor die. In a particular embodiment, the edge regions 126 are approximately 1% to 99% of the semiconductor die surface area, or approximately 1% to 90%, or approximately 1% to 80%. In other words, the area not covered by the horizontally oriented graphite is generally relatively small. In this embodiment, heat generated in the edge regions of the semiconductor die is diffused to the surface area above the memory chip. Then, heat generated near the center of the semiconductor die is passively diffused to the edge regions of the semiconductor die. It is worth noting that, although Figures 5A-6B The description illustrates that only the second layer has empty areas, but the first and third layers can also have similar empty areas if desired. These embodiments allow for the use of less graphite while still achieving acceptable heat dissipation.

[0063] Generally, the thermal interface film 200 includes at least a first layer 210 (containing vertically oriented graphite) and a second layer 220 (containing horizontally oriented graphite). Figure 7A and Figure 7B Two embodiments of a two-layer thermal interface film are described. First, refer to... Figure 7A As shown here, the first layer 210 sits on top of the second layer 220. The second layer 220 will contact the semiconductor die. Similarly, this embodiment may be more useful if the cap and / or heat sink have a high surface roughness. Now refer to... Figure 7B Here, the first layer 210 is located below the second layer 220. The first layer 210 will contact the semiconductor die. This embodiment may be useful if the surface of the semiconductor die and / or memory chip has a high surface roughness.

[0064] Now refer to Figure 8A and Figure 8B In this embodiment, the thermal interface film 200 is a single layer 240, which simultaneously contains vertically oriented graphite 202 and horizontally oriented graphite 204. Figure 8B yes Figure 8A Plan view of the BB line. Here, vertically oriented graphite 202 is represented by circles, while horizontally oriented graphite 204 is represented by lines extending along the Y and X axes.

[0065] Figure 9This is a cross-sectional view of another embodiment of the processor module 100 of this utility model. This embodiment includes a semiconductor die 120 and a memory chip 130, a wafer 102 and a substrate 104 to obtain a semiconductor package 110. In this embodiment, there is no cover (also referred to as a bare die). Instead, a thermal interface film 200 directly contacts the semiconductor die 120 and the heat sink 154.

[0066] Figure 10 This is a cross-sectional view of another embodiment of the processor module 100 of this utility model. This embodiment is similar to... Figure 1 The embodiment shown. In this embodiment, the second thermal interface material layer 152 is also a thermal interface film as described above.

[0067] Figure 11 This is a flowchart illustrating a method 300 for fabricating a thermal interface thin film according to some embodiments, and will be referred to... Figure 2A To explain. In step 305, a vertically oriented graphite layer is formed, which can be used as... Figure 2A Layers 210 and 230 in the thin film. Figure 11 In step 310, a horizontally oriented graphite layer is formed, which can be used as... Figure 2A Layer 220 in the film. These two steps can be performed using conventional methods. For example, graphite can be dispersed in a polymer solution or melt. The graphite-impregnated polymer solution or melt can then be extruded, and the graphite can be oriented as needed by applying a magnetic field or other orientation methods. Figure 11 In step 315, at least one vertically oriented graphite layer and at least one horizontally oriented graphite layer are then stacked together to form a thermal interface film 200. Pressure may be applied to bond the layers together due to electrostatic forces and / or material properties. In an optional step 320, the composite film may be cured to keep the layers bonded together.

[0068] Figure 12 This is a flowchart illustrating a method 400 for applying a heat sink to a semiconductor package according to some embodiments. The method steps will be discussed below in relation to forming a single processor module.

[0069] First of all, Figure 12 In step 405, a semiconductor package 110 is received. Here, the semiconductor package includes a semiconductor die 120, a wafer 102, and a substrate 104. Again, a cover 150 is present, but not required.

[0070] Alternatively, a semiconductor package can be formed. In step 410, the semiconductor die 120 is attached to the wafer 102. In step 415, the wafer 102 is attached to the substrate 104. These steps will produce a bare die package.

[0071] In step 420, a thermal interface film 200 is applied to the grains. The thermal interface film 200 may be held in place relative to the grains due to electrostatic forces and / or material properties. If a cap is required, in optional step 425, an adhesive 148 is placed around the substrate. The order of applying the thermal interface film and the adhesive can be reversed. Then, in optional step 430, a cap 150 is attached to the substrate using the adhesive. The cap also contacts the thermal interface film 200. This will produce a result such as Figure 1 The semiconductor package 110 shown is indicated as step 432. It should be noted that the thermal interface film typically has higher thermal conductivity than the cover of the semiconductor package, which helps to dissipate heat more quickly.

[0072] Continue, and then, in Figure 12 In optional step 435, the semiconductor package 110 can be installed into the slot on the motherboard. Next, in Figure 12 In optional step 440, a second thermal interface material layer 152 is applied to the semiconductor package to form a second thermal interface material layer 152. This layer may be formed on the cover (e.g., on...). Figure 1 (in the middle) or formed on the semiconductor die (e.g.) Figure 9 (The bare grains). The second thermal interface material layer can be another thermal interface film, or some other thermal interface material.

[0073] exist Figure 12 In step 445, the heat sink is then secured to the semiconductor package. For example, a clamp or fastening system (such as screws) can be used to secure the heat sink to the second thermal interface material layer.

[0074] Reference Figure 13 Data center 170 (indicated by dashed lines) comprises a group of servers 172, labeled here as server 1 to server n. Each server functions as a computing node within the data center. Each server 172 contains multiple processor modules 100, labeled here for illustrative purposes as GPU-1 to GPU-n or CPU-1 to CPU-n. The servers and their processor modules are networked together and configured to send data to user interface 176. This forms a high-performance computing (HPC) environment. The various servers can work in parallel to process data and perform computations more quickly.

[0075] Typically, servers are interconnected through one or more tiers of network switches and routers. Other components not shown here include power supplies, switches, routers, hubs, gateways, firewalls, intrusion detection / prevention devices, computer terminals, printers, memory / storage devices, modems, access points, fire detection and suppression systems, cabling, input / output devices, fans, etc.

[0076] This invention utilizes a processor module with a thermal interface film, offering several advantages. The use of a thermal interface film allows for more rapid distribution of heat generated by the semiconductor chip across a larger surface area, thereby improving heat transfer efficiency. Consequently, the heat distribution within the semiconductor package is more uniform. This also reduces heat buildup on the semiconductor die, thus extending the lifespan of the semiconductor chip. Traditional heat transfer materials, including gels, are prone to pump-out phenomena, where the thermal gel / paste gradually migrates outward from the semiconductor chip due to temperature fluctuations during semiconductor package bending or uneven stress. Reduced application of thermal adhesive / paste at desired locations leads to increased temperature and decreased heat transfer efficiency. The use of a thermal interface film avoids this problem.

[0077] Some embodiments of this invention therefore relate to a method of applying a heat sink to a semiconductor package. A thermal interface film is applied to the semiconductor package. A heat sink is then applied to the thermal interface film. Note that there may be other layers, such as a cover, between the thermal interface film and the heat sink. The thermal interface film comprises at least a first layer and a second layer, the first layer comprising vertically oriented graphite and the second layer comprising horizontally oriented graphite.

[0078] Other embodiments disclosed herein relate to semiconductor packaging, including: a semiconductor die; a thermal interface film on the semiconductor die; and a heat sink on the thermal interface film. The thermal interface film includes at least a first layer and a second layer, the first layer comprising vertically oriented graphite and the second layer comprising horizontally oriented graphite.

[0079] Semiconductor packages are also described in various embodiments herein, including: a semiconductor die; a thermal interface film on the semiconductor die; and a heat sink on the thermal interface film. The thermal interface film is a monolayer comprising vertically oriented graphite and horizontally oriented graphite.

[0080] Some embodiments of this invention also relate to a method of applying a heat sink to a semiconductor package. A thermal interface film is applied to the semiconductor package. Then, a heat sink is applied to the thermal interface film. Note that there may be other layers, such as a cover, between the thermal interface film and the heat sink. The thermal interface film is a single layer comprising vertically oriented graphite and horizontally oriented graphite.

[0081] Other embodiments disclosed herein relate to methods for fabricating thermal interface films. A vertically oriented graphite layer is formed. A horizontally oriented graphite layer is formed. At least one vertically oriented graphite layer and at least one horizontally oriented graphite layer are then stacked together to form a thermal interface film. Optionally, the composite film may be cured to maintain the layers bonded together.

[0082] Other embodiments disclosed herein relate to methods for fabricating a monolayer thermal interface film containing both vertically oriented and horizontally oriented graphite. Graphite is dispersed in a polymer solution or melt. The graphite-containing polymer solution or melt can then be extruded, and a magnetic field is applied to simultaneously orient the graphite horizontally and vertically.

[0083] This document also discloses devices comprising semiconductor packages having the thermal interface film described above. Examples of such devices may include mobile phones, cameras, computers, televisions, vehicles such as airplanes or automobiles, or other consumer electronic devices such as washing machines, dryers, toasters, microwave ovens, etc.

[0084] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor package, characterized in that, include: Semiconductor grains; as well as The thermal interface film on the semiconductor grain; The thermal interface film comprises at least a first layer and a second layer, wherein the first layer comprises vertically oriented graphite and the second layer comprises horizontally oriented graphite.

2. The semiconductor package according to claim 1, characterized in that, The thermal interface film further includes a third layer comprising vertically oriented graphite, and the second layer is located between the first layer and the third layer.

3. The semiconductor package according to claim 2, characterized in that, The thickness of the first layer is equal to or greater than the thickness of the third layer.

4. The semiconductor package according to claim 2, characterized in that, The thickness of the first layer is less than the thickness of the third layer.

5. The semiconductor package according to claim 1, characterized in that, The horizontally oriented graphite in the second layer is located within a length range greater than the length of the semiconductor grain and less than the length of the semiconductor package; or The horizontally oriented graphite in the second layer is located in the peripheral region of the second layer, and the peripheral region overlaps with the edge region of the semiconductor grain.

6. The semiconductor package according to claim 1, characterized in that, Also includes: A cover, wherein the thermal interface film is located between the semiconductor die and the cover, and the thermal interface material is present between the heat sink and the cover.

7. The semiconductor package according to claim 1, characterized in that, The heat sink is in direct contact with the thermal interface film.

8. A processor module, characterized in that, include: Semiconductor grains; The thermal interface film on the semiconductor grain; as well as The heat sink on the thermal interface film; The thermal interface film is a single layer comprising graphite oriented in a first volume and graphite oriented in a second volume, the first volume being different from the second volume.

9. The processor module according to claim 8, characterized in that, The angle formed between the first volume and the second volume is at least 45°.

10. The processor module according to claim 8, characterized in that, The graphite in the first volume is vertically oriented and the graphite in the second volume is horizontally oriented.

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