Single tube package structure of inner insulation series

Abstract

The application relates to a single-tube packaging structure of an inner insulation series and relates to the packaging technical field of semiconductor devices, and aims to solve the problem of large parasitic inductance caused by the packaging structure of a discrete layout. The single-tube packaging structure of the inner insulation series comprises an insulation sheet, a first metal coating, a second metal coating, a third metal coating and a fourth metal coating are arranged on one side of the insulation sheet at intervals, the first metal coating, the second metal coating, the third metal coating and the fourth metal coating are sequentially fixedly connected with a first pin, a second pin, a third pin and a fourth pin. The third metal coating is provided with a semiconductor transistor, and the third metal coating is in contact connection with a drain electrode of the semiconductor transistor. A gate electrode of the semiconductor transistor is in flying wire connection with the first metal coating, and a source electrode is in flying wire connection with the second metal coating. The fourth metal coating is provided with a diode, the fourth metal coating is in contact connection with a negative electrode of the diode, and a positive electrode of the diode is connected with the third metal coating through a flying wire.

Description

Technical Field

[0001] This application relates to the field of semiconductor device packaging technology, and more particularly to a single-tube packaging structure with internal insulation. Background Technology

[0002] In the field of power electronics, with the increasing demand for high efficiency, high power density, and high-frequency switching performance, silicon carbide (SiC) MOSFETs (semiconductor field-effect transistors, hereinafter referred to as semiconductor transistors) are finding wider and wider applications due to their excellent high-temperature, high-voltage, and high-frequency operating capabilities, as well as low switching losses. Common PFC (Power Factor Correction) circuits often employ a combination of TO247 packaged MOSFETs and diodes.

[0003] However, the discrete packaging structure results in high parasitic inductance, especially during high-frequency switching, which can lead to significant switching losses and electromagnetic interference (EMI). Utility Model Content

[0004] This application provides a single-tube package structure with internal insulation to solve the problem of large parasitic inductance caused by discrete package structures.

[0005] This application provides an internally insulated single-tube package structure, including an insulating sheet. A first metal cladding layer, a second metal cladding layer, a third metal cladding layer, and a fourth metal cladding layer are spaced apart on one side of the insulating sheet. These four metal cladding layers are sequentially fixedly connected to a first pin, a second pin, a third pin, and a fourth pin. A semiconductor transistor is disposed on the third metal cladding layer, and the third metal cladding layer is in contact with the drain of the semiconductor transistor. The gate of the semiconductor transistor is connected to the first metal cladding layer via a flying wire, and the source of the semiconductor transistor is connected to the second metal cladding layer via a flying wire. A diode is disposed on the fourth metal cladding layer, and the fourth metal cladding layer is in contact with the cathode of the diode. The anode of the diode is connected to the third metal cladding layer via a flying wire.

[0006] In some embodiments, along a first direction, the first pin, second pin, third pin, and fourth pin are connected to the same end of the insulating sheet. A third and fourth metal cladding layer are spaced apart along a second direction, with an angle between the first and second directions.

[0007] In some embodiments, along a first direction, the first metal cladding layer and the second metal cladding layer are spaced apart from the semiconductor transistor.

[0008] In some embodiments, the insulating sheet is further provided with a fifth metal cladding layer spaced apart, the fifth metal cladding layer being fixedly connected to the fifth pin, and the fifth metal cladding layer being connected to the Kelvin flying wire of the semiconductor transistor.

[0009] In some implementations, the spacing between the first pin, the fifth pin, and other pins along the second direction is greater than or equal to 1 mm.

[0010] In some implementations, the spacing between the second, third, and fourth pins along the second direction is a first dimension, and the spacing between adjacent first and fifth pins along the second direction is a second dimension, wherein the second dimension is greater than the first dimension.

[0011] In some embodiments, a sixth metal cladding layer is further provided on one side of the insulating sheet. The sixth metal cladding layer is disposed at opposite ends of the insulating sheet along a first direction and at the same side as the third metal cladding layer along a third direction. The sixth metal cladding layer is spaced apart from the third and fourth metal cladding layers along the first direction, and the sixth metal cladding layer has multiple stress holes along the third direction. The first direction, the second direction, and the third direction form an angle with each other.

[0012] In some embodiments, there are two sixth metal cladding layers, which are spaced apart along the second direction.

[0013] In some embodiments, the main components of the insulating sheet are aluminum oxide, aluminum nitride, or silicon nitride.

[0014] In some embodiments, the first metal cladding, the second metal cladding, the third metal cladding, the fourth metal cladding, and the sixth metal cladding are connected to the insulating sheet by active metal brazing or direct metal bonding.

[0015] In some embodiments, the first metal cladding, the second metal cladding, the third metal cladding, the fourth metal cladding, and the sixth metal cladding are copper-based claddings.

[0016] In some embodiments, a seventh metal cladding is provided on the other side of the insulating sheet, and the seventh metal cladding and the first metal cladding are disposed on opposite sides of the insulating sheet along a third direction.

[0017] In some embodiments, the single-tube encapsulation structure of the internal insulation series further includes an encapsulation layer covering an insulating sheet, a first metal cladding, a second metal cladding, a third metal cladding, a fourth metal cladding, and a seventh metal cladding. The technical solutions provided in this application have the following advantages compared with the prior art: In the single-tube package structure of the internally insulated series provided in the embodiments of this application, the first pin, the second pin, the third pin and the fourth pin are connected to the insulating sheet in sequence through the first metal cladding, the second metal cladding, the third metal cladding and the fourth metal cladding, so as to increase the conductor cross-sectional area of ​​the pin through the metal cladding structure, which is beneficial to reduce parasitic inductance.

[0018] Specifically, the connection between the pins and the semiconductor transistor can be achieved by using flying wires between the metal cladding and the semiconductor transistor. For the first metal cladding 21 and the second metal cladding 22, the larger conductor contact area allows for a wider range of choices in the arrangement of the flying wire contacts, facilitating flexible adjustments to the routing layout, preventing interference between adjacent pins, and reducing parasitic inductance. For the third metal cladding 23 and the fourth metal cladding 24, the larger cross-sectional area of ​​the metal cladding reduces impedance and thus lowers parasitic inductance through a larger current-carrying area. This reduces losses and electromagnetic interference in the semiconductor transistor during high-frequency switching. In other words, through optimized design of the metal claddings, flying wire connections, and pin layout, a compact and efficient internal layout of the power device is achieved, effectively solving the problems of high parasitic inductance, poor heat dissipation, and complex mounting processes inherent in traditional packaging methods. Attached Figure Description The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0021] Figure 1 An internal top view of a single-tube package structure with internal insulation provided for an embodiment of this application; Figure 2 for Figure 1 A three-dimensional structural schematic diagram of a single-tube package structure with internal insulation is shown. Figure 3 for Figure 1 A partial structural diagram of one side of the insulating sheet shown in the figure; Figure 4 A circuit topology diagram of a single-tube package structure with internal insulation provided in an embodiment of this application; Figure 5 A schematic diagram of a single-tube package structure with internal insulation provided in this application being applied to a boost circuit; Figure 6for Figure 1 An internal bottom view of a single-tube package structure with internal insulation, as shown. Figure 7 Figure 2 The diagram shows an overall structural schematic of a single-tube package structure with internal insulation.

[0022] Explanation of reference numerals in the attached figures: 10. Insulating sheet; 21. First metal cladding layer; 22. Second metal cladding layer; 23. Third metal cladding layer; 24. Fourth metal cladding layer; 25. Fifth metal cladding layer; 26. Sixth metal cladding layer; 27. Seventh metal cladding layer; 28. Stress hole; 31. First pin; 32. Second pin; 33. Third pin; 34. Fourth pin; 35. Fifth pin; 40. Semiconductor transistor; 50. Diode; 60. Encapsulation layer; X, First direction; Y, Second direction; Z, Third direction. Detailed Implementation

[0023] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0024] The following disclosure provides numerous different embodiments or examples for implementing various structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0025] For ease of description, spatial relative terms may be used in the text to describe the relative position or movement of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "front," "back," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure undergoes a positional flip, orientation change, or change of motion, these directional indications will change accordingly. For instance, an element described as "below other elements or features" or "below other elements or features" will subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptors used in the text will be interpreted accordingly.

[0026] Please see Figures 1 to 7 This application provides a single-tube package structure with internal insulation to solve the problem of large parasitic inductance caused by discrete package structures.

[0027] like Figure 1 and Figure 2 As shown, the single-tube package structure of the internally insulated series includes an insulating sheet 10. A first metal cladding layer 21, a second metal cladding layer 22, a third metal cladding layer 23, and a fourth metal cladding layer 24 are spaced apart on one side of the insulating sheet 10. The first metal cladding layer 21, the second metal cladding layer 22, the third metal cladding layer 23, and the fourth metal cladding layer 24 are sequentially fixedly connected to a first pin 31, a second pin 32, a third pin 33, and a fourth pin 34. A semiconductor transistor 40 is disposed on the third metal cladding layer 23, and the third metal cladding layer 23 is in contact with the drain of the semiconductor transistor 40. The gate of the semiconductor transistor 40 is connected to the first metal cladding layer 21 via a flying wire, and the source of the semiconductor transistor 40 is connected to the second metal cladding layer 22 via a flying wire. A diode 50 is disposed on the fourth metal cladding layer 24, and the fourth metal cladding layer 24 is in contact with the cathode of the diode 50. The anode of the diode 50 is connected to the third metal cladding layer 23 via a flying wire.

[0028] The insulating sheet 10 can be a substrate with high electrical insulation properties, serving to support and position the metal cladding while also providing electrical isolation between regions with different potentials. For example, the insulating sheet 10 can be made of ceramic materials or polymers, and its surface can be treated to form a stable bonding interface with the metal cladding.

[0029] For example, the main components of the insulating sheet 10 are aluminum oxide, aluminum nitride, or silicon nitride. Among them, ceramic materials such as aluminum oxide (Al2O3), aluminum nitride (AlN), and silicon nitride (Si3N4) have excellent insulation properties. Taking the thickness of the insulating sheet 10 as an example, which is between 0.25-1.0 mm, the corresponding breakdown voltage can reach 5-20 kV, which is sufficient to isolate the potential difference between the chip and the heat sink.

[0030] Furthermore, in high-power and high-frequency applications, aluminum nitride insulation sheets 10 can be used, balancing efficient heat dissipation (thermal conductivity up to 230-320 W / (m·K)) with high-frequency insulation suitability. In extreme environments (such as thermal shock resistance, aerospace, or energy storage inverters), silicon nitride insulation sheets 10 can be selected, sacrificing some thermal conductivity for better mechanical reliability, while still meeting insulation requirements. In low-to-medium power and cost-sensitive applications (such as ordinary IGBT (Insulated Gate Bipolar Transistor) modules or industrial power supplies), alumina insulation sheets 10 can be used, offering high cost-effectiveness and meeting basic heat dissipation and insulation performance requirements.

[0031] One side of the insulating sheet 10 is provided with a first metal cladding layer 21, a second metal cladding layer 22, a third metal cladding layer 23, and a fourth metal cladding layer 24 spaced apart. This arrangement ensures electrical isolation between the metal cladding layers, avoids the formation of signal interference paths, and thus reduces parasitic inductance problems during high-frequency switching. The first metal cladding layer 21, the second metal cladding layer 22, the third metal cladding layer 23, and the fourth metal cladding layer 24 are sequentially fixedly connected to the first pin 31, the second pin 32, the third pin 33, and the fourth pin 34. This direct fixed connection eliminates the need for external insulating material, reduces the thermal resistance conduction path, and allows heat to be transferred more efficiently from the chip to the pins, thereby improving heat dissipation performance.

[0032] The semiconductor transistor 40 can be a silicon carbide MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) or other types of power switching devices. Its drain is connected to the third metal cladding 23 so that the third pin 33 serves as the current input terminal. The source of the semiconductor transistor 40 is connected to the second metal cladding 22 via multiple flying wires so that the second pin 32 serves as the current output terminal. The arrangement of multiple flying wires 9 (such as four 12mil aluminum or copper wires) is beneficial for handling larger current loads. The gate of the semiconductor transistor 40 is connected to the first metal cladding 21 via flying wires so that the first pin 31 serves as the signal voltage input terminal, used to control the conduction or disconnection between the second pin 32 and the third pin 33.

[0033] Based on this, a diode 50 is provided on the fourth metal cladding layer 24, and the negative terminal of the diode 50 is connected to the fourth pin 34 through the fourth metal cladding layer 24. The positive terminal of the diode 50 is connected to the third metal cladding layer 23 through one or more flying wires. For example, the flying wires can be three 12mil aluminum or copper wires to facilitate a larger current load.

[0034] The third metal cladding layer 23 houses the semiconductor transistor 40, and is connected to the drain of the semiconductor transistor 40 via direct contact. This direct contact structure reduces interface resistance, allowing heat generated during chip operation to dissipate quickly through the metal cladding layer, avoiding heat accumulation caused by traditional solder mounting. The gate of the semiconductor transistor 40 is connected to the first metal cladding layer 21 via a flying wire. This flying wire connection keeps the gate signal path short and direct, suppressing voltage oscillations caused by gate loop inductance and reducing switching losses and electromagnetic interference. Simultaneously, the source of the semiconductor transistor 40 is connected to the second metal cladding layer 22 via a flying wire. This flying wire connection optimizes the geometry of the current loop, reduces the impact of source inductance on switching speed, and improves high-frequency operating stability.

[0035] The fourth metal cladding layer 24 is provided with a diode 50. The positive terminal of the diode 50 is connected to the third metal cladding layer 23 through a flying wire. The integrated flying wire connection shortens the interconnection length between the diode 50 and the switching chip, avoids the problem of long wires in discrete layout, further reduces parasitic inductance and improves overall electrical reliability.

[0036] The diode 50 has the functions of forward conduction, freewheeling, and voltage boosting. For example... Figure 3 and Figure 4 As shown, the input signal voltage can be controlled via the first pin 31, thereby controlling the conduction and disconnection of the semiconductor transistor 40. When the semiconductor transistor 40 is on, the input voltage U1 is applied across the inductor L, and the inductor L stores energy. At this time, the diode 50 is reverse-biased and the capacitor C discharges R to the load to maintain the output voltage. When the semiconductor transistor 40 is off, the induced electromotive force of the inductor L is superimposed on U1, the diode 50 is forward-biased, and the energy stored in the inductor L, together with the input voltage U1, charges the capacitor C and supplies power to the load R, so that the output voltage U2 is higher than the input voltage.

[0037] Based on this, in the aforementioned single-tube package structure of the internally insulated series, the first pin 31, the second pin 32, the third pin 33, and the fourth pin 34 are sequentially connected to the insulating sheet via the first metal cladding 21, the second metal cladding 22, the third metal cladding 23, and the fourth metal cladding 24. This increases the conductor cross-sectional area of ​​the pins through the metal cladding structure, which helps reduce parasitic inductance. Specifically, the connection between the pins and the semiconductor transistor 40 can be achieved by using flying wires between the metal cladding and the semiconductor transistor 40. For the first and second metal claddings 21 and 22, the larger conductor contact area allows for a wider range of choices in the arrangement of the flying wire contacts, facilitating flexible adjustments to the wiring layout and preventing mutual interference between adjacent pins, thus reducing parasitic inductance. For the third and fourth metal claddings 23 and 24, the larger cross-sectional area of ​​the metal claddings reduces impedance through a larger current-carrying area, thereby reducing parasitic inductance. This reduces losses and electromagnetic interference in the semiconductor transistor 40 during high-frequency switching. By optimizing the design of each metal coating, flying wire connection, and pin layout, the internal layout of the power device is made more compact and efficient, effectively solving the problems of high parasitic inductance, poor heat dissipation, and complex installation process in traditional packaging methods.

[0038] In some embodiments, such as Figure 1 and Figure 2 As shown, along the first direction X, the first pin 31, the second pin 32, the third pin 33, and the fourth pin 34 are connected to the same end of the insulating sheet 10. The third metal cladding layer 23 and the fourth metal cladding layer 24 are distributed at intervals along the second direction Y, and there is an angle between the first direction X and the second direction Y.

[0039] The first direction, X, refers to the main extension direction of the pin arrangement. It can be a straight line or a curve with a certain curvature, aiming to optimize the spatial layout of the pin cluster. The second direction, Y, is the direction that intersects with the first direction, X. It can be implemented perpendicularly or obliquely, aiming to provide reasonable distribution space for the metal overlay. The angle design, by introducing a non-parallel spatial orientation relationship, can effectively improve the space utilization within the package structure and ensure the smoothness of the bonding wire path.

[0040] For example, the first direction X and the second direction Y can be arranged parallel to the insulating sheet 10, such as the first direction X being the length direction of the insulating sheet 10 and the second direction Y being the width direction of the insulating sheet 10. Correspondingly, the third direction Z can be the thickness direction of the insulating sheet 10. That is, the first direction X, the second direction Y, and the third direction Z can be straight lines and arranged perpendicular to each other.

[0041] By concentrating the four pins along the first direction X at the same end of the insulating sheet 10, the actual connection distance of the bonding wires is significantly shortened, avoiding the physical conflict of the bonding wires crossing each other in the traditional distributed layout, thereby suppressing the generation of parasitic inductance. At the same time, the arrangement of the third metal cladding layer 23 and the fourth metal cladding layer 24 at intervals along the second direction Y clearly defines the spatial isolation between them, providing independent mounting areas for the semiconductor transistor 40 and the diode 50, and reducing electrical coupling interference during high-frequency operation.

[0042] like Figure 2 and Figure 3 As shown, along the first direction X, the first metal cladding layer 21 and the second metal cladding layer 22 are spaced apart from the semiconductor transistor 40.

[0043] By setting a physical spacing between the first metal cladding layer 21, the second metal cladding layer 22, and the semiconductor transistor 40 along the first direction X, the problem of excessive parasitic inductance during high-frequency switching is effectively solved. The spacing along the first direction X creates a controllable distance between the gate connection path and the source connection path and the chip body for electrical isolation. Since the first direction X is a critical direction for pin clustering, maintaining spacing in this direction minimizes the current loop area, thereby suppressing additional parasitic inductance caused by electric and magnetic field coupling. This not only reduces the generation of electromagnetic noise but also balances structural directionality and electrical isolation requirements, ensuring the stability of the gate drive signal and source circuit during high-frequency operation and avoiding performance degradation caused by local heat accumulation or potential interference.

[0044] like Figure 1 and Figure 3 As shown, the insulating sheet 10 is also provided with a fifth metal cladding layer 25 spaced apart. The fifth metal cladding layer 25 is fixedly connected to the fifth pin 35, and the fifth metal cladding layer 25 is connected to the Kelvin flying wire of the semiconductor transistor 40.

[0045] The first metal cladding 21, the second metal cladding 22, the third metal cladding 23, the fourth metal cladding 24, and the fifth metal cladding 25 can be implemented using copper foil, aluminum foil, or other metallic materials with good electrical conductivity. For example, the thickness of the insulating sheet 10 along the third direction Z can be 0.25-1.0 mm. The metal cladding can be oxygen-free copper with a thickness of 0.1-0.6 mm.

[0046] By using the fifth metal cladding layer 25 and the fifth pin 35, physical isolation from other metal cladding layers can be maintained through a specific spacing design. This aims to prevent electromagnetic coupling interference from high-frequency currents in the power circuit to the sensing path, thereby reducing the impact of parasitic inductance on voltage detection and improving detection accuracy. The fifth pin 35 serves as a dedicated sensing port, which can be reliably fixed to the fifth metal cladding layer 25 through soldering, crimping, or threaded connections, ensuring a low-impedance signal transmission path.

[0047] The fifth metal cladding layer 25 is connected to the Kelvin terminal of the semiconductor transistor 40 via a flying wire. This short-path design effectively reduces the parasitic inductance introduced by traditional long wires, enabling real-time and accurate capture of source voltage changes. Simultaneously, the fifth pin 35, as an independent sensing port, can transmit the acquired source voltage signal to an external controller with high fidelity, providing precise feedback signals for switching control. Furthermore, the spacing design between the fifth metal cladding layer 25 and other metal cladding layers further suppresses the electromagnetic coupling effect generated by high-frequency currents in the power circuit, ensuring that the Kelvin connection operates in a stable electrical environment.

[0048] For example, at the end of the insulating sheet 10 used to fix the connection pins, the connection points of the first metal cladding 21, the fifth metal cladding 25, the second metal cladding 22, the third metal cladding 23, and the fourth metal cladding 24 are sequentially distributed along the second direction Y (e.g., from left to right). Since the second pin 32 is the current output terminal, the area of ​​the second metal cladding 22 can be larger than the areas of the first metal cladding 21 and the fifth metal cladding. Taking the five pins located at the lower end of the insulating sheet 10 as an example, the first metal cladding 21, the fifth metal cladding 25, and the second metal cladding 22 are distributed alternately from left to right. The main body of the third metal cladding 23 is spaced above the above three metal claddings, the pin ends of the third metal cladding 23 are located to the right of the second metal cladding 22, and the fourth metal cladding 24 can be a strip structure arranged along the first direction X and located to the left of the third metal cladding 23. This achieves an electrically isolated design and distribution.

[0049] Specifically, the spacing between the first pin 31, the fifth pin 35, and other pins along the second direction Y is greater than or equal to 1 mm. Since the first pin 31 and the fifth pin 35 are used to transmit signal voltage or current and have a small load, setting a small gap (greater than 1 mm) between them and other pins can reduce the overall structural size along the second direction Y while achieving electrical isolation, which is beneficial for product miniaturization design.

[0050] The spacing along the second direction Y between the second pin 32, the third pin 33, and the fourth pin 34 is the first dimension. The spacing along the second direction Y between the adjacent first pin 31 and the fifth pin 35 is the second dimension. The second dimension is larger than the first dimension; for example, the second dimension can be set to 2-3 mm. If the second dimension is too large, the insulating sheet 10 will have a large width along the second direction Y. If the second dimension is too small, the electrical clearance between the second pin 32, the third pin 33, and the fourth pin 34 will be insufficient. This optimizes the utilization of the package space and provides better electrical performance for the single-tube package structure of the internal insulation series.

[0051] It should be noted that since pins 31 and 35 are primarily low-voltage pins, while pins 32, 33, and 34 are high-voltage pins, the second dimension is set larger than the first dimension. Furthermore, the spacing between each pin should exceed the standard electrical clearance requirements to ensure good electrical isolation between the pins. Minimizing pin spacing further facilitates miniaturization of the product.

[0052] In some embodiments, such as Figure 2 and Figure 3 As shown, a sixth metal cladding layer 26 is also provided on one side of the insulating sheet 10. The sixth metal cladding layer 26 is spaced apart from the third metal cladding layer 23 and the fourth metal cladding layer 24 along the first direction X. The sixth metal cladding layer 26 and the first pin 31 are disposed at opposite ends of the insulating sheet 10 along the first direction X. The sixth metal cladding layer 26 and the third metal cladding layer 23 are located on the same side of the insulating sheet 10 along the third direction Z, and the sixth metal cladding layer 26 is provided with a plurality of stress holes 28 along the third direction Z.

[0053] The first direction X, the second direction Y, and the third direction Z are at an angle to each other, which can be 85-95°. Alternatively, the first direction X, the second direction Y, and the third direction Z can be set perpendicular to each other.

[0054] For example, there are two sixth metal cladding layers 26, and the two sixth metal cladding layers 26 are distributed at intervals along the second direction Y.

[0055] The sixth metal cladding layer 26 is disposed at opposite ends of the insulating sheet 10 along the first direction X, coinciding with the first pin 31. This symmetrical layout is designed based on the asymmetry of thermal expansion direction to balance the deformation stress caused by temperature changes, thereby reducing the risk of package distortion. Furthermore, the sixth metal cladding layer 26 is located on the same side of the insulating sheet 10 along the third direction Z, and is spaced apart from the third metal cladding layer 23 and the fourth metal cladding layer 24 along the first direction X. This design allows the cladding layers to be directly adjacent to the heat source area, enhancing heat dissipation efficiency and shortening the heat transfer path. Multiple stress holes 28 are provided along the third direction Z at the sixth metal cladding layer 26. The stress holes 28 can specifically absorb material expansion deformation, effectively suppressing crack initiation and propagation, avoiding the formation of stress peaks, thereby comprehensively improving the durability of the package in high-frequency switching applications.

[0056] Thus, through the arrangement and structure of the sixth metal coating 26, the problem of mechanical stress concentration generated during thermal cycling of the packaging structure is significantly improved, thereby extending the service life of the device and improving its reliability.

[0057] In some embodiments, such as Figure 2 and Figure 6 As shown, a seventh metal cladding 27 is provided on the other side of the insulating sheet 10. The seventh metal cladding 27 and the first metal cladding 21 are disposed on opposite sides of the insulating sheet 10 along the third direction Z.

[0058] The seventh metal cladding 27 refers to a thermally conductive metal structure added to the back of the insulating sheet 10. It can be made of metal materials with high thermal conductivity such as copper and aluminum. The purpose is to build additional heat dissipation channels to optimize the overall thermal management performance.

[0059] Thus, the insulating sheet 10, acting as an electrical isolation substrate, can electrically isolate the metal coatings on opposite sides, thereby achieving internal insulation of the packaging structure. With a metal coating already present on one side of the insulating sheet 10, a seventh metal coating 27 is added to the other side, allowing the heat generated by the power chip during operation to be conducted synchronously from both sides, avoiding heat accumulation and localized overheating caused by a single-sided structure.

[0060] This layout combines the geometric characteristics and physical insulation features of the insulating sheet 10, ensuring that the two cladding layers optimize the heat flow path in spatial orientation. This allows heat to be evenly distributed to the external heat dissipation structure, reducing thermal stress concentration, improving heat exchange efficiency, and ultimately enhancing the stability and durability of the device in high power density applications. Specifically, the inclusion of the seventh metal cladding layer 27 enhances the heat dissipation and cooling effect on both sides, effectively addressing the heat dissipation bottleneck, significantly reducing thermal resistance, improving the performance and lifespan of power devices, and meeting the demands of modern power electronic systems for efficient heat dissipation and compact design.

[0061] For example, the first metal cladding 21, the second metal cladding 22, the third metal cladding 23, the fourth metal cladding 24 and the sixth metal cladding 26 are connected to the insulating sheet 10 by active metal brazing or direct metal bonding.

[0062] Correspondingly, the fifth metal cladding layer 25 and the seventh metal cladding layer 27 are also connected to the insulating sheet 10 by active metal brazing or direct metal bonding.

[0063] For example, the first metal cladding layer 21, the second metal cladding layer 22, the third metal cladding layer 23, the fourth metal cladding layer 24, and the sixth metal cladding layer 26 are copper-based cladding layers. Correspondingly, the fifth metal cladding layer 25 and the seventh metal cladding layer 27 are also copper-based cladding layers.

[0064] The insulating sheet 10 is a ceramic material with high thermal conductivity. It can be made of materials such as alumina, aluminum nitride or silicon nitride. While providing electrical isolation to the metal coatings on both sides, it can significantly improve the heat conduction path and avoid the additional thermal resistance introduced by traditional mica sheets or silicone pads, thus meeting the high-temperature operating requirements of silicon carbide devices.

[0065] Among them, the active metal brazing connection structure is a connection method that forms an atomic-level bonding interface through active metal filler metal at high temperature. The direct metal bonding connection structure, on the other hand, utilizes direct chemical bonding between the metal and ceramic to achieve the connection. Both can ensure a strong and stable connection structure between the metal cladding and the insulating sheet 10, and provide sufficient contact area for stable support and heat transfer, thereby avoiding the accumulation of mechanical stress and interface failure caused by differences in material expansion during thermal cycling.

[0066] Metal cladding refers to a metal cladding with copper as the main component. It can be made of pure copper or copper alloy materials. The purpose is to take advantage of its high thermal and electrical conductivity to not only reduce resistance loss during current transmission, but also to optimize the overall heat dissipation efficiency, so that the metal cladding can maintain structural integrity while withstanding high-frequency switching stress.

[0067] In addition, such as Figure 2 and Figure 7 As shown, the single-tube encapsulation structure of the internal insulation series also includes an encapsulation layer 60, which covers the insulating sheet 10, the first metal coating 21, the second metal coating 22, the third metal coating 23, the fourth metal coating 24, and the seventh metal coating 27. The fifth metal coating 25 and the sixth metal coating 26 are also encapsulated within the encapsulation layer 60.

[0068] Encapsulation layer 60 refers to a structure used for overall sealing and protection of critical internal components. It can be implemented using processes such as epoxy resin molding or silicone potting. The main purpose of encapsulation layer 60 is to prevent the intrusion of moisture and contaminants by forming a physical barrier, ensuring long-term stable and effective electrical isolation. The encapsulation layer 60 can avoid short circuits and metal corrosion problems between pins during high-frequency switching, significantly reduce the risk of electromagnetic interference, and resolve oxidation at the heat dissipation interface and potential electrical safety hazards.

[0069] Thus, by encapsulating and covering the electrical components through a single package design, the installation process is simplified, eliminating the need for additional insulating materials such as external mica sheets or silicone pads. This reduces thermal resistance and improves the device's environmental adaptability and compactness. Furthermore, the combined design of the package layer 60 and the seventh metal coating layer 27 further enhances heat dissipation performance and electrical connection stability, resolving issues of heat dissipation interface degradation and reduced overall reliability.

[0070] Thus, in the single-tube package structure of the internally insulated series provided in this application embodiment, from left to right, the first pin 31 is used to receive control signals; the fifth pin 35, while realizing independent voltage detection, is used to reduce the influence of parasitic inductance on voltage detection, thereby improving switching accuracy; the second pin 32 serves as the current output terminal; the third pin 33 is used for current input and freewheeling; and the fourth pin 34 is connected to the cathode of the diode 50. By rationally allocating the functions of the five pins, the current path is optimized, thereby improving the current carrying capacity.

[0071] By directly plating copper onto a ceramic substrate, internal insulation is achieved while simultaneously improving insulation performance, simplifying the manufacturing process, and enhancing heat dissipation. Furthermore, integrating a MOSFET and SBD into a single package reduces parasitic inductance and improves system efficiency. It also reduces power consumption while increasing power density. By maintaining the original package size through integrated design and optimized circuit paths, it is suitable for high-power and small-size applications.

[0072] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “described” as used herein may also include the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0073] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0074] The above description is merely a specific embodiment of this application, enabling those skilled in the art to understand or implement this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A single-tube packaging structure with internal insulation, characterized in that, The device includes an insulating sheet, on one side of which are provided a first metal cladding layer, a second metal cladding layer, a third metal cladding layer, and a fourth metal cladding layer, which are sequentially and fixedly connected to a first pin, a second pin, a third pin, and a fourth pin. The third metal cladding layer is provided with a semiconductor transistor, and the third metal cladding layer is in contact with the drain of the semiconductor transistor; the gate of the semiconductor transistor is connected to the first metal cladding layer via a flying wire, and the source of the semiconductor transistor is connected to the second metal cladding layer via a flying wire; the fourth metal cladding layer is provided with a diode, and the fourth metal cladding layer is in contact with the negative terminal of the diode, and the positive terminal of the diode is connected to the third metal cladding layer via a flying wire.

2. The single-tube packaging structure of the internal insulation series according to claim 1, characterized in that, Along the first direction, the first pin, the second pin, the third pin, and the fourth pin are connected to the same end of the insulating sheet; The third metal cladding and the fourth metal cladding are distributed at intervals along the second direction, and there is an angle between the first direction and the second direction.

3. The single-tube packaging structure of the internal insulation series according to claim 2, characterized in that, Along the first direction, the first metal cladding and the second metal cladding are spaced apart from the semiconductor transistor.

4. The single-tube packaging structure of the internal insulation series according to claim 2, characterized in that, The insulating sheet is further provided with a fifth metal cladding layer spaced apart, the fifth metal cladding layer being fixedly connected to the fifth pin, and the fifth metal cladding layer being connected to the Kelvin flying wire of the semiconductor transistor.

5. The single-tube packaging structure of the internal insulation series according to claim 4, characterized in that, The spacing between the first pin, the fifth pin, and other pins along the second direction is greater than or equal to 1 mm; and / or, The spacing between the second pin, the third pin, and the fourth pin along the second direction is a first dimension, and the spacing between the adjacent first pin and the fifth pin along the second direction is a second dimension, the second dimension being larger than the first dimension.

6. The single-tube packaging structure of the internal insulation series according to any one of claims 2-5, characterized in that, A sixth metal cladding is also provided on one side of the insulating sheet. The sixth metal cladding is disposed at opposite ends of the insulating sheet along the first direction and the first pin. The sixth metal cladding is located on the same side of the insulating sheet along the third direction as the third metal cladding. The sixth metal cladding is spaced apart from the third metal cladding and the fourth metal cladding along the first direction, and the sixth metal cladding is provided with a plurality of stress holes along the third direction; The first direction, the second direction, and the third direction are at angles to each other.

7. The single-tube packaging structure of the internal insulation series according to claim 6, characterized in that, The number of the sixth metal cladding layers is two, and the two sixth metal cladding layers are distributed at intervals along the second direction.

8. The single-tube packaging structure of the internal insulation series according to claim 6, characterized in that, The main component of the insulating sheet is aluminum oxide, aluminum nitride, or silicon nitride; and / or, The first metal cladding, the second metal cladding, the third metal cladding, the fourth metal cladding, and the sixth metal cladding are connected to the insulating sheet by active metal brazing or direct metal bonding; and / or, The first metal cladding, the second metal cladding, the third metal cladding, the fourth metal cladding, and the sixth metal cladding are copper-based claddings.

9. The single-tube packaging structure of the internal insulation series according to any one of claims 1-5, characterized in that, A seventh metal cladding is provided on the other side of the insulating sheet, and the seventh metal cladding and the first metal cladding are disposed on opposite sides of the insulating sheet along a third direction.

10. The single-tube packaging structure of the internal insulation series according to claim 9, characterized in that, The single-tube encapsulation structure of the inner insulation series further includes an encapsulation layer, which covers the insulating sheet, the first metal coating, the second metal coating, the third metal coating, the fourth metal coating, and the seventh metal coating.

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