Semiconductor device and semiconductor package including the same

Abstract

Various embodiments of the present utility model relate to a semiconductor device. A capacitor structure is disposed in an interconnect layer of a semiconductor die that is bonded with another semiconductor die in a vertical stack of semiconductor dies. To enable an increase in the vertical length of the capacitor structure, a top electrode layer of the capacitor structure is directly connected to a bonding structure of the semiconductor die, rather than the top electrode layer of the capacitor structure being connected to the bonding structure through one or more intermediate conductive structures in the interconnect layer. This enables the capacitor structure to extend vertically through more layers of the interconnect layer, thereby increasing the length of the top electrode layer and a bottom electrode layer of the capacitor structure, which in turn increases the capacitance of the capacitor structure. The increased capacitance of the capacitor structure enables the semiconductor device to achieve increased performance.

Description

Technical Field

[0001] This utility model relates to a semiconductor device and a semiconductor package containing the same. Background Technology

[0002] Various semiconductor component packaging technologies can be used to integrate one or more semiconductor dies into a semiconductor package. In some cases, semiconductor dies can be horizontally interconnected via intermediaries. Additionally and / or as an alternative, semiconductor dies can be vertically arranged within the semiconductor package to achieve a smaller horizontal or lateral footprint and / or increase the semiconductor package density. Semiconductor dies can be directly connected via die-to-die (or wafer-to-wafer) bonding and / or via interconnects and one or more intermediaries. Utility Model Content

[0003] One embodiment of this invention provides a semiconductor device. The semiconductor device includes a component layer. The semiconductor device further includes one or more integrated circuit components located within the component layer. The semiconductor device also includes an interconnect layer located above the component layer. The semiconductor device further includes one or more conductive structures located within the interconnect layer. The semiconductor device also includes one or more bonding structures located above the interconnect layer. The semiconductor device further includes a trench capacitor structure directly coupled to the bonding structures in the one or more bonding structures.

[0004] Another embodiment of this utility model provides a semiconductor package. The semiconductor package includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first interconnect layer, one or more first conductive structures located in the first interconnect layer, a plurality of first bonding structures located above the first interconnect layer, and a trench capacitor structure directly coupled to the first bonding structures among the plurality of first bonding structures. The second semiconductor die is bonded to the first semiconductor die at a bonding interface, such that the first semiconductor die and the second semiconductor die are vertically aligned in the semiconductor package. The second semiconductor die includes a second interconnect layer, one or more second conductive structures located in the second interconnect layer, and a plurality of second bonding structures located below the second interconnect layer, wherein the second bonding structures among the plurality of second bonding structures are electrically coupled to the first bonding structures.

[0005] Another aspect of this utility model provides a method for forming a semiconductor device. The method includes forming one or more integrated circuit components in a component layer of the semiconductor device. The method further includes forming an interconnect layer of the semiconductor device above the component layer. The method further includes forming recesses through multiple dielectric layers of the interconnect layer. The method further includes forming a trench capacitor structure of the semiconductor device in the recesses. The method further includes forming a bonding structure of the semiconductor device on the trench capacitor structure.

[0006] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a diagram of an example embodiment of the semiconductor device described herein.

[0008] Figure 2 This is a diagram of another example embodiment of the semiconductor device described herein.

[0009] Figure 3A and Figure 3B This is a diagram of an example implementation of the capacitor structure described in this article.

[0010] Figures 4A to 4P This is a diagram of an example embodiment of forming a semiconductor device as described herein.

[0011] Figures 5A to 5C This is a diagram of an example embodiment of forming a semiconductor device as described herein.

[0012] Figure 6A and Figure 6B This is a diagram of an example implementation of the semiconductor package described herein.

[0013] Figure 7A and Figure 7B This is a diagram of an example implementation of the semiconductor package described herein.

[0014] Figure 8A and Figure 8B This is a diagram of an example embodiment of the semiconductor device described herein.

[0015] Figure 9 This is a flowchart of an example process related to the formation of a semiconductor device as described herein. Detailed Implementation

[0016] This invention provides numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the invention. These are merely examples and are not intended to be limiting. For instance, the following description of a first component being formed on or on a second component may include embodiments in which the first and second components are formed in direct contact, and may also include embodiments in which additional components may be formed between the first and second components, thereby potentially preventing direct contact between the first and second components. Furthermore, reference numerals and / or letters may be repeated in various instances. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of explanation, spatially relative terms such as “beneath,” “below,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one component or feature and another shown in the figures. In addition to the orientations illustrated in the figures, these spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein shall be interpreted accordingly.

[0018] Semiconductor devices may include multiple semiconductor dies bonded together in a vertically stacked manner. One or more semiconductor dies in the vertical stack may include one or more capacitor structures in their interconnect layers (e.g., back end of line or back end of line (BEOL) regions). The capacitor structure may include a metal-insulator-metal (MIM) stack, wherein an insulating layer is sandwiched between two electrode layers (a top electrode layer and a bottom electrode layer). The capacitance of the capacitor structure (e.g., the amount of charge that the capacitor structure can store) depends directly on the geometry of the conductive electrode layers of the capacitor structure. The larger the area of ​​the conductive electrode layers, the larger the capacitance of the capacitor structure. Therefore, increasing the size of the metal electrode layers can increase the capacitance of the capacitor structure.

[0019] However, increasing the lateral dimensions of capacitor structures directly contradicts the semiconductor industry's design principles of minimizing semiconductor device size to reduce power consumption, achieve higher operational performance and efficiency, and / or enable semiconductor devices for increasingly smaller form factor applications. Therefore, capacitor structures may not be able to increase in lateral dimension because the lateral area within the semiconductor device may be limited. This limits the capacitance of the capacitor structure, potentially limiting the benefits the capacitor structure brings to the semiconductor device's performance.

[0020] In some embodiments described herein, the capacitor structure is disposed within the interconnect layer of a semiconductor die, wherein the semiconductor die is bonded to another semiconductor die in a vertical stack of multiple semiconductor dies. To increase the vertical length of the capacitor structure, the top electrode layer of the capacitor structure is directly connected to the bonding structure of the semiconductor die (e.g., bonding pad, bonding via), rather than the top electrode layer of the capacitor structure being connected to the bonding structure via one or more intermediate conductive structures in the interconnect layer. This allows the capacitor structure to extend vertically through a greater number of layers in the interconnect layer, thereby increasing the length of the top and bottom electrode layers of the capacitor structure, and consequently increasing the capacitance of the capacitor structure. This increased capacitance enables the semiconductor device to achieve higher performance.

[0021] For example, the semiconductor device can be an image sensor device (e.g., a three-dimensional complementary metal oxide semiconductor imagesensor (3D CIS) device), comprising an image sensor die bonded to an application-specific integrated circuit (ASIC) die. The image sensor die may include multiple pixel sensors arranged in a pixel sensor array. The pixel sensors in the pixel sensor array may include photodiodes configured to convert photons of incident light into a photocurrent. The magnitude of the photocurrent is at least partially based on the intensity of the incident light. Therefore, if the pixel sensors in the pixel sensor array are capable of sensing incident light with a wide range of intensities, the images and / or videos generated by the semiconductor device can achieve a wide range of brightness and contrast.

[0022] A pixel sensor may have a limited number of incident photons it can absorb before reaching saturation. "Saturation" refers to the level of photon absorption beyond which the pixel sensor can no longer absorb additional photons. Saturation limits the dynamic range of a pixel sensor because it cannot obtain additional brightness and color information from further photon absorption. The amount of photocurrent charge a pixel sensor can store before reaching saturation is called its full well capacity (FWC). The FWC of a pixel sensor may be based at least in part on factors such as the size (e.g., depth, width, volume) and / or shape of the photodiode. However, while increasing the size of the photodiode can increase the FWC, this may come at the cost of reducing the pixel density in the pixel sensor array, which in turn may reduce the resolution of the pixel sensor array.

[0023] The capacitor structure can be configured to store charge associated with the photocurrent generated by the pixel sensor, thereby increasing the field of view (FWC) of the pixel sensor. The photocurrent can be transferred from the pixel sensor to the capacitor structure, allowing the pixel sensor to generate more charge for the photocurrent than would be if the photocurrent were entirely stored in the photodiodes and / or floating diffusion nodes of the pixel sensor. Therefore, the capacitor structure increases the FWC of the pixel sensor, enabling a wider range of brightness and / or contrast in the images and / or videos generated by the pixel sensor array. Furthermore, increasing the capacitance of the capacitor structure by directly connecting the top electrode layer to the bonding structure further increases the FWC of the pixel sensor by allowing a greater amount of charge to be stored in the capacitor structure, thereby further improving the performance of the semiconductor device.

[0024] Figure 1 This is a diagram of an example embodiment 100 of the semiconductor device 102 described herein. The semiconductor device 102 may include a system-on-a-chip (SoC) die, such as a logic die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, a digital signal processing (DSP) die, an application-specific integrated circuit (ASIC) die, and / or other types of SoC dies. Additionally and / or as an alternative, the semiconductor device 102 may include memory dies, input / output (I / O) dies, pixel sensor dies, and / or other types of semiconductor dies. Memory dies may include static random access memory (SRAM) dies, dynamic random access memory (DRAM) dies, NAND dies, high bandwidth memory (HBM) dies, and / or other types of memory dies. Generally, the semiconductor device 102 is a semiconductor device that includes one or more capacitor structures in its interconnect layer.

[0025] like Figure 1 As shown, the semiconductor device 102 includes a component layer 104, an interconnect layer 106 arranged perpendicularly to the component layer 104 in the semiconductor device 102 (e.g., in the z-direction), and a bonding layer 108 arranged perpendicularly to the interconnect layer 106 in the semiconductor device 102 (e.g., in the z-direction).

[0026] The component layer 104 may also be referred to as the front end of line (FEOL) region of the semiconductor device 102. The component layer 104 includes a substrate layer 110. The substrate layer 110 may correspond to the portion of the semiconductor device 102 formed on the top of the semiconductor wafer. The substrate layer 110 may include a silicon (Si) substrate, a substrate formed of a silicon-containing material, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of semiconductor substrates. The substrate layer 110 may extend in the semiconductor device 102 along the x-direction and / or y-direction.

[0027] Integrated circuit component 112 may be included within and / or on substrate layer 110 in component layer 104 of semiconductor device 102. Integrated circuit component 112 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (FinFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, front-end capacitors, front-end resistors, front-end inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor components. Front-end semiconductor components refer to semiconductor components formed in component layer 104 of semiconductor device 102 (e.g., within and / or on substrate layer 110), and not semiconductor components formed in interconnect layer 106 of semiconductor device 102.

[0028] A dielectric layer 114 is disposed on the substrate layer 110. The dielectric layer 114 includes an interlayer dielectric (ILD) layer, an etch stop layer (ESL), and / or other types of dielectric layers. The dielectric layer 114 includes a dielectric material that enables selective etching of portions of the substrate layer 110 and / or the integrated circuit assembly 112, or protects them from etching, and / or electrically isolates the integrated circuit assembly 112 within the assembly layer 104. The dielectric layer 114 includes silicon nitride (Si). x N y ), oxides (e.g., silicon oxide (SiO2) x (and / or other oxide materials), and / or other types of dielectric materials. The dielectric layer 114 may extend in the semiconductor device 102 along the x-direction and / or y-direction.

[0029] Interconnect layer 106 of semiconductor device 102 is located above substrate layer 110 and integrated circuit assembly 112 in semiconductor device 102 along the z-direction. Integrated circuit assembly 112 may be electrically coupled to interconnect layer 106. Interconnect layer 106 includes a plurality of dielectric layers (e.g., back-end dielectric layers) arranged in a direction approximately perpendicular to substrate layer 110 (e.g., z-direction). The dielectric layers may include interlayer dielectric layers 116 and etch stop layers 118 arranged alternately in the z-direction. ILD layer 116 and etch stop layer 118 may extend in semiconductor device 102 along the x-direction and / or y-direction.

[0030] ILD layers 116 may each comprise oxides (e.g., silicon oxide (SiO2)). x The dielectric material can be an undoped silicate glass (USG), a borosilicate glass (BSG), a fluorine-doped silicate glass (FSG), a tetraethyl orthosilicate (TEOS), a hydrogensilsesquioxane (HSQ), or other suitable dielectric materials. In some embodiments, the ILD layer 116 comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO₂). x ), amorphous fluorinated carbon (aC) x F y ), parylene, bisbenzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous hydrosilsesquioxane (HSQ), porous methylsilsesquioxane (MSQ), porous polyaryl ether (PAE), and / or porous silica (SiO2) x (and other examples).

[0031] Etch stop layers 118 may each contain silicon nitride (Si) x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the ILD layer 116 and the etch stop layer 118 contain different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 106.

[0032] Interconnect layer 106 includes multiple conductive structures. One or more conductive structures 120 are electrically coupled and / or physically coupled to one or more integrated circuit components 112 in component layer 104. Conductive structures 120 provide electrical wiring to enable signals and / or power to be supplied to and / or transmitted from integrated circuit components 112. Conductive structures 120 may include a combination of metallization structures and interconnect structures. Metallization structures may include trenches, metallization layers, conductive traces, and / or other types of metallization structures. Interconnect structures may include vias, plugs, interconnects, and / or other types of interconnect structures. Conductive structures 120 may contain one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials. In some embodiments, conductive structures 120 include one or more substrates. One or more substrates may include barrier substrates, adhesive substrates, and / or other types of substrates. Examples of materials used for one or more liner layers include tantalum nitride (TaN) and / or titanium nitride (TiN), as well as others.

[0033] In some embodiments, the conductive structures 120 may be arranged in multiple layers arranged vertically (e.g., in the z-direction) within the interconnect layer 106. In other words, layers of conductive structures 120 extend over the component layer 104 within the interconnect layer 106 to facilitate wiring of electrical signals and / or power between the component layer 104 and the interconnect layer 106. Metallization structures may be arranged in a metallization layer referred to as the M layer. For example, a metal-0 (MO) layer comprising multiple conductive structures 120 (e.g., metallization structures) may be located at the bottom of the interconnect layer 106 and may be directly coupled to the component layer 104 (e.g., to the integrated circuit component 112 within the component layer 104). A via-1 (V1) layer comprising multiple conductive structures (e.g., interconnect structures) may be included above the MO layer. A metal-1 (M1) layer comprising multiple conductive structures 120 (e.g., metallized structures) may be located above the V1 layer in the interconnect layer 106, a via-2 (V2) layer comprising multiple conductive structures (e.g., interconnect structures) may be included above the M1 layer, a metal-2 (M2) layer comprising multiple conductive structures 120 (e.g., metallized structures) may be located above the V2 layer, and so on.

[0034] One or more top metal layers may be included above the conductive structures 120 (e.g., M and V layers) in the interconnect layer 106. For example, the interconnect layer 106 may include an etch stop layer 122, an interlayer dielectric layer 124, an etch stop layer 126, an interlayer dielectric layer 128, an etch stop layer 130, an interlayer dielectric layer 132, an etch stop layer 134, and an interlayer dielectric layer 136, and may include a top via 138 (e.g., extending through the etch stop layer 122 and the interlayer dielectric layer 124), a top metal layer 140 (e.g., extending through the etch stop layer 126 and the interlayer dielectric layer 128), a top via 142 (e.g., extending through the etch stop layer 130 and the interlayer dielectric layer 132), and / or a top metal layer 144 (e.g., extending through the etch stop layer 134 and / or the interlayer dielectric layer 136), and other examples.

[0035] Top vias 138 and 142 may be substantially larger than the interconnect structure of conductive structure 120 (e.g., may be taller in the z-direction). Similarly, top metal layers 140 and 144 may be substantially larger than the metallization structure of conductive structure 120 (e.g., may be taller in the z-direction). For example, the metallization structure of conductive structure 120 may have a sub-micron z-direction height, while top metal layers 140 and 144 may have a z-direction height of about 1 micrometer or greater. However, the other z-direction heights for the metallization structure of conductive structure 120 and for top metal layers 140 and 144 are still within the scope of this invention.

[0036] The larger physical dimensions of the top vias 138 and 142, as well as the top metal layers 140 and 144, provide lower chip resistance and enable a larger volume of current signals to be handled at the top of the interconnect layer 106. The smaller physical dimensions of the conductive structure 120 allow for a higher density of conductive structures 120 to be included closer to the integrated circuit components 112 in the component layer 104, enabling the integrated circuit components 112 to be positioned more closely together to achieve a higher integrated circuit component density in the component layer 104.

[0037] In some embodiments, ESLs 122, 126, 130, and 134 may comprise alternating arrangements of materials. For example, ESLs 122 and 130 may comprise silicon carbide (SiC), while ESLs 126 and 134 may comprise silicon nitride (SiC). x N y (e.g., Si3N4). However, other combinations of materials such as ESL122, 126, 130 and 134 are still within the scope of this invention.

[0038] In some embodiments, the etch stop layer 122 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the interlayer dielectric layer 124 may have a z-direction thickness ranging from about 4000 angstroms to about 8000 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the etch stop layer 126 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the interlayer dielectric layer 128 may have a z-direction thickness ranging from about 6000 angstroms to about 12000 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the etch stop layer 130 may have a z-direction thickness ranging from about 300 angstroms to about 800 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the interlayer dielectric layer 132 may have a z-direction thickness ranging from about 4,000 angstroms to about 8,000 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the etch stop layer 134 may have a z-direction thickness ranging from about 300 angstroms to about 700 angstroms. However, other values ​​are still within the scope of this invention. In some embodiments, the interlayer dielectric layer 136 may have a z-direction thickness ranging from about 7,000 angstroms to about 10,000 angstroms. However, other values ​​are still within the scope of this invention.

[0039] Bonding layer 108 may be connected to the top metal layer 144 of interconnect layer 106. Bonding layer 108 may include additional etch stop layers and dielectric layers, such as ESL 146, dielectric layer 148, ESL 150 and / or dielectric layer 152, and other examples. Furthermore, bonding layer 108 may include bonding vias 154 (e.g., extending through etch stop layers 146 and / or dielectric layers 148) and bonding pads 156 (e.g., extending through ESL 150 and / or dielectric layers 152). Bonding vias 154 may be electrically connected and / or physically connected to the top metal layer 144, and bonding pads 156 may be electrically connected and / or physically connected to bonding vias 154.

[0040] Etch stop layers 146 and 150 may each include silicon nitride (Si). x N y The dielectric layers 148 and 152 may each comprise oxides (e.g., silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. x(and / or other oxide materials), undoped silicate glass (USG), borosilicate glass (BSG), fluorinated silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrosilsesquioxane (HSQ) and / or other suitable dielectric materials.

[0041] In some embodiments, the thickness of the etch stop layer 146 in the Z direction can range from about 500 angstroms to about 1000 angstroms. However, other ranges are still within the scope of this invention. In some embodiments, the thickness of the dielectric layer 148 in the Z direction can range from about 4000 angstroms to about 9000 angstroms. However, other ranges are still within the scope of this invention. In some embodiments, the thickness of the ESL 150 in the Z direction can range from about 800 angstroms to about 1600 angstroms. However, other ranges are still within the scope of this invention. In some embodiments, the thickness of the dielectric layer 152 in the Z direction can range from about 6000 angstroms to about 12000 angstroms. However, other ranges are still within the scope of this invention.

[0042] The bonding via 154 includes a conductive structure extending primarily in the Z direction. The bonding via 154 electrically couples the top metal layer 144 to the bonding pad 156. The bonding pad 156 includes a conductive pad for bonding the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. The bonding via 154 and the bonding pad 156 include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of conductive materials.

[0043] The bonding layer 108 also includes a bonding dielectric layer 158 surrounding the bonding pad 156. The bonding dielectric layer 158 can also be used to bond the semiconductor device 102 to another semiconductor device to form a vertically stacked semiconductor package. Therefore, the combination of the bonding pad 156 and the bonding dielectric layer 158 enables the semiconductor device 102 to be bonded to another semiconductor device via metal-to-metal bonding and dielectric-to-dielectric bonding. The bonding dielectric layer 158 may include one or more dielectric materials, such as silicon nitride (Si). x N y Silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the thickness of the bonding dielectric layer 158 in the Z direction can range from about 500 angstroms to about 1000 angstroms. However, other ranges of values ​​are still within the scope of this invention.

[0044] like Figure 1As further shown, the semiconductor device 102 may include one or more capacitor structures 160. The capacitor structure 160 may include a trench capacitor structure housed in and extending through a portion of the bonding layer 108, and housed in and extending through a portion of the interconnect layer 106. The capacitor structure 160 may include a deep trench capacitor (DTC) structure because the capacitor structure 160 has a high aspect ratio between its vertical (Z-direction) height and its lateral (X-direction) width. For example, the aspect ratio of the capacitor structure 160 may be greater than about 10:1, and in some embodiments, the aspect ratio of the capacitor structure 160 is in the range of about 18:1 to about 55:1. However, other values ​​and ranges of the aspect ratio of the capacitor structure 160 are also within the scope of this invention.

[0045] The high aspect ratio of capacitor structure 160 is achieved, at least in part, by directly connecting the top of capacitor structure 160 to conductive structure 120 or top metallization layer in interconnect layer 106, rather than by connecting the top of capacitor structure 160 directly to bonding via 154 in bonding layer 108. This direct connection between the top of capacitor structure 160 and bonding via 154 allows capacitor structure 160 to be housed within and extend through a portion of bonding layer 108, and within and extend through a portion of interconnect layer 106. This allows the capacitance of capacitor structure 160 to be increased to five times or more if capacitor structure 160 only extends through interconnect layer 106.

[0046] like Figure 1 As shown, the capacitor structure 160 includes multiple conformal layers that conform to the contours of trenches extending through multiple dielectric layers of interconnect layer 106 and bonding layer 108. The trenches may extend through, for example, etch stop layers 122, 126, 130, and 134 of interconnect layer 106, interlayer dielectric layers 124, 128, 132, and 136 of interconnect layer 108, etch stop layer 146 of bonding layer 108, and / or dielectric layer 148 of bonding layer 108. The trenches may extend to conductive structure 120 in interconnect layer 106, such that the bottom of capacitor structure 160 is electrically connected to conductive structure 120.

[0047] The conformal layer may include a bottom electrode layer 162, an insulating layer 164 situated on the bottom electrode layer 162, and a top electrode layer 166 situated on the insulating layer 164. Therefore, the insulating layer 164 is located between the bottom electrode layer 162 and the top electrode layer 166, allowing the capacitor structure 160 to store charge based on the capacitance between the bottom electrode layer 162 and the top electrode layer 166. The bottom electrode layer 162, the insulating layer 164, and the top electrode layer 166 may be conformal layers extending along the sidewalls and bottom surface of a trench in which the capacitor structure 160 is formed. A dielectric filler 168 may be located in the trench to electrically isolate sections of the top electrode layer 166 on opposite sidewalls of the trench. However, in other embodiments, the dielectric filler 168 may be omitted, and the top electrode layer 166 fills the remaining area of ​​the trench.

[0048] like Figure 1 As shown, the portion of the bottom electrode layer 162 located at the bottom of the capacitor structure 160 can be in physical contact with the conductive structure 120 located at the bottom of the capacitor structure 160. Therefore, the bottom electrode layer 162 can be electrically connected to the conductive structure 120 in the interconnect layer 106. The portion of the top electrode layer 166 located at the top of the capacitor structure 160 can be in physical contact (e.g., direct physical contact) with the bonding via 154 located at the top of the capacitor structure 160. Therefore, the top electrode layer 166 can be directly electrically connected to the bonding via 154 in the bonding layer 108.

[0049] The bottom electrode layer 162, insulating layer 164, and top electrode layer 166 correspond to the metal-insulator-metal (MIM) stack of the capacitor structure 160. Therefore, the capacitor structure 160 can also be referred to as an MIM capacitor structure. The bottom electrode layer 162 (also called capacitor bottom metal (CBM)) and the top electrode layer 166 (also called capacitor top metal (CTM)) may each include one or more conductive metals, one or more conductive metal-containing materials, one or more conductive ceramic materials, and / or other types of conductive materials. Examples include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), tantalum (Ta), aluminum (Al), copper (Cu), gold (Au), titanium nitride (TiN), and / or tantalum nitride (TaN). In some embodiments, the bottom electrode layer 162 and the top electrode layer 166 include the same material or the same material composition. In some embodiments, the bottom electrode layer 162 and the top electrode layer 166 include different materials or different material compositions.

[0050] The insulating layer 164 may include one or more electrically insulating materials. In some embodiments, the insulating layer 164 includes one or more low-k dielectric materials, such as silicon oxide (SiO2). x(e.g., SiO2). Additionally and / or as an alternative, the insulating layer 164 may include one or more high-k dielectric materials, such as zirconium oxide (ZrO2). x For example, ZrO2), aluminum oxide (Al) x O y For example, Al2O3), silicon nitride (Si) x N y For example, Si3N4), yttrium oxide (Y) x O y For example, Y2O3), lanthanum oxide (La) x O y For example, La2O3), and / or hafnium oxide (HfO) x For example, HfO2, etc. In some embodiments, the insulating layer 164 is a multilayer stack comprising multiple dielectric layers. For example, the insulating layer 164 may comprise a ZrO2 / Al2O3 / ZrO2 (ZAZ) layer stack.

[0051] like Figure 1 As further shown, the capacitor structure 160 may include one or more capping layers disposed above the top electrode layer 166. The one or more capping layers may include capping layer 170, capping layer 172, and / or other capping layers. The capping layers may provide electrical isolation for the MIM stack of the capacitor structure 160 and / or may also serve as a hard mask layer stack for forming recesses of the bonding via 154. Capping layers 170 and 172 may include an oxide-containing dielectric material, such as silicon oxide (SiO2). x For example, SiO2), nitrogen oxide dielectric materials such as silicon oxynitride (SiON), and nitride dielectric materials such as silicon nitride (SiO2). x N y (e.g., Si3N4) and / or other suitable dielectric materials. In some embodiments, capping layers 170 and 172 comprise the same material and / or have the same material composition. In some embodiments, capping layers 170 and 172 comprise different materials and / or have different material compositions.

[0052] A bonding via 154 connected to the top electrode layer 166 of the capacitor structure 160 may extend through the cover layers 170 and 172. In some embodiments, the bonding via 154 connected to the top electrode layer 166 of the capacitor structure 160 may extend into the top electrode layer 166 such that the bottom surface of the bonding via 154 is recessed in the top electrode layer 166.

[0053] like Figure 1As further shown, the capacitor structure 160 may include one or more sidewall spacers 174 and / or 176, which are disposed on the sidewalls of the capping layers 170 and / or 172, and / or on the sidewall of the top electrode layer 166 located at the top of the capacitor structure 160. The combination of the capping layers 170, 172 and the sidewall spacers 174, 176 can be used as a self-aligned mask when etching the layers to define the bottom electrode layer 162. The sidewall spacer 174 may include an oxide-containing dielectric material, such as silicon oxide (SiO2). x For example, SiO2). The sidewall spacers 176 may include nitride-containing dielectric materials, such as silicon nitride (SiO2). x N y For example, Si3N4, etc.

[0054] As mentioned above, Figure 1 This is provided as an example only. Other examples are available in relation to [the relevant information]. Figure 1 The descriptions are different.

[0055] Figure 2 This is a diagram of another example embodiment 200 of the semiconductor device 102 described herein. (See diagram for example.) Figure 2 As shown, an example embodiment 200 of the semiconductor device 102 may include... Figure 1 The example embodiment 100 of the semiconductor device 102 shown illustrates a combination and arrangement of layers and / or structures similar to those in the same manner. However, in Figure 2 In Example Implementation 200, the etch stop layer 146, dielectric layer 148, and bonding via 154 are omitted from the semiconductor device 102. Instead, bonding pad 156 is directly connected (e.g., physically and / or electrically) to the top metal layer 144 and directly connected (e.g., physically and / or electrically) to the top electrode layer 166 of the capacitor structure 160.

[0056] like Figure 2 As shown, ESL 150 can be disposed on interlayer dielectric layer 136, dielectric layer 152 can be disposed on ESL 150, and bonding dielectric layer 158 can be disposed on dielectric layer 152. The top of capacitor structure 160 can be disposed in dielectric layer 152. In some embodiments, the vertical (z-direction) thickness of dielectric layer 152 in example embodiment 200 of semiconductor device 102 can be in the range of about 6800 angstroms to about 16600 angstroms. However, other values ​​and ranges are also within the scope of this invention.

[0057] The bonding pad 156 connected to the top electrode layer 166 of the capacitor structure 160 may extend through the cover layers 170 and 172. In some embodiments, the bonding pad 156 connected to the top electrode layer 166 of the capacitor structure 160 may extend into the top electrode layer 166 such that the bottom surface of the bonding pad 156 is recessed in the top electrode layer 166.

[0058] As mentioned above, Figure 2 This is provided as an example only. Other examples may be related to... Figure 2 The descriptions are different.

[0059] Figure 3A and Figure 3B This is a diagram of an example embodiment of the capacitor structure 160 described herein. Figure 3A As shown in Example Embodiment 300, the capacitor structure 160 may have an elongated body (or finger) 302 extending in the z-direction. The elongated body 302 may extend into trenches formed in a plurality of dielectric layers in the interconnect layer 106 and bonding layer 108 of the semiconductor device 102 described herein. In some embodiments, the vertical (z-direction) height (or depth) of the elongated body 302 (in...) Figure 3A The dimension (D1) can range from about 3 micrometers to about 6 micrometers. In some embodiments, the lateral (x-direction) width of the elongated body 302 (in Figure 3A The dimension (D2) can range from about 500 angstroms to about 3300 angstroms. However, other values ​​and ranges of these dimensions are also within the scope of this invention.

[0060] like Figure 3B As shown in Example Embodiment 304, the capacitor structure 160 may include a plurality of fingers 306, each extending in the z-direction. A bottom electrode layer 162, an insulating layer 164, and / or a top electrode layer 166 may extend continuously through each finger 306 and between each finger 306, and may conform to the cross-sectional profile of each finger 306. In some embodiments, the capacitor structure 160 may include 1 to 10 fingers 306. However, other numbers of fingers 306 in the capacitor structure 160 are also within the scope of this invention.

[0061] As mentioned above, Figure 3A and Figure 3B This is provided as an example only. Other examples may be related to... Figure 3A and Figure 3B The descriptions are different.

[0062] Figures 4A to 4P This is a diagram illustrating an exemplary embodiment 400 of the semiconductor device 102 described herein. Specifically, exemplary embodiment 400 includes the formation of… Figure 1This is an example of an exemplary embodiment 100 of the semiconductor device 102 shown. However, it is possible to combine... Figures 4A to 4P Another example embodiment of the semiconductor device 102 described herein is the one or more semiconductor processing operations described herein. In some embodiments, one or more semiconductor processing tools may be used to perform the combination. Figures 4A to 4P The one or more semiconductor processing operations described herein, semiconductor processing tools such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0063] come Figure 4A A substrate layer 110 may be provided. The substrate layer 110 may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or other types of semiconductor workpieces. The semiconductor device 102 may be formed on the semiconductor wafer together with other semiconductor devices.

[0064] like Figure 4B As shown, integrated circuit component 112 may be formed within and / or on substrate layer 110 in component layer 104 of semiconductor device 102. One or more semiconductor processing tools may be used to form one or more portions of integrated circuit component 112. For example, an ion implantation tool may be used to dope one or more regions in substrate layer 110 with one or more types of dopants to form well regions, implantation regions, and / or other types of doped regions of integrated circuit component 112 in substrate layer 110. As another example, deposition tools may be used to perform various deposition operations to deposit layers and / or structures of integrated circuit component 112, and / or deposit photoresist layers for etching portions of substrate layer 110 and / or deposited layers. As another example, an exposure tool may be used to expose photoresist layers to form patterns in photoresist layers. As another example, a developing tool may be used to develop patterns in photoresist layers. As another example, an etching tool may be used to etch portions of substrate layer 110 and / or deposited layers to form integrated circuit component 112. As another example, a planarization tool may be used to planarize portions of integrated circuit component 112. As another example, an electroplating tool can be used to deposit the metal structure and / or layers of the integrated circuit assembly 112.

[0065] like Figure 4BAs further shown, a dielectric layer 114 is deposited on and / or on the substrate 110 and the integrated circuit assembly 112 using a deposition tool. The dielectric layer 114 can be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, a planarization operation, such as chemical mechanical planarization (CMP), can be performed using a planarization tool to planarize the dielectric layer 114 after deposition.

[0066] like Figure 4C As shown, contacts 402 of the integrated circuit component 112 may be formed through the dielectric layer 114. Contacts 402 may be formed in recesses within the dielectric layer 114. In some embodiments, a pattern in a photoresist layer is used to etch the dielectric layer 114 to form the recess. In these embodiments, a photoresist layer may be formed on the dielectric layer 114 using a deposition tool. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the dielectric layer based on the pattern to form the recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some implementations, a hard mask layer is used as an alternative technique to pattern-based etching of the dielectric layer 114 to form the recess.

[0067] Contact 402 may be formed in a recess. In some embodiments, contact 402 (e.g., a gate contact) is formed on the gate structure of integrated circuit assembly 112. In some embodiments, contact 402 (e.g., a source / drain contact) is formed on the source / drain region of integrated circuit assembly 112. Material for contact 402 may be deposited in the recess using deposition tools via CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. Material for contact 402 may be deposited in one or more deposition operations. In some embodiments, a seed layer is deposited first, and then material for contact 402 is deposited on the seed layer. In some embodiments, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize contact 402 after deposition, such that the top of contact 402 is substantially coplanar with the top of dielectric layer 114.

[0068] like Figure 4C As shown, a first portion of the interconnect layer 106 of the semiconductor device 102 is formed over the dielectric layer 114. Alternating ILD layers 116 and ESL layers 118 are deposited in the first portion of the interconnect layer 106 of the semiconductor device 102 using one or more deposition tools. In this way, the ILD layers 116 and ESL layers 118 can be aligned along the z-direction in the semiconductor device 102. Each ILD layer 116 and each ESL layer 118 can be deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, the ILD layers 116 and / or ESL layers 118 can be planarized using a planarization tool after deposition.

[0069] like Figure 4CAs further shown, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form a conductive structure 120 in a first portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, the first portion of the interconnect layer 106 may be formed in multiple layers. For example, ILD layers 116 and ESL 118 may be formed (e.g., using one or more deposition tools and / or one or more planarization tools), recesses may be formed in and / or through ILD layers 116 and ESL 118 (e.g., using exposure tools, developing tools, and / or etching tools), and a first layer (e.g., MO layer) of the conductive structure 120 (e.g., a metallized structure) may be formed in ILD layers 116 and ESL 118 (e.g., using one or more deposition tools and / or one or more planarization tools). Another ILD layer 116 and another ESL 118 may be formed, and a second layer (e.g., VO layer) of conductive structure 120 (e.g., interconnect structure) may be formed in ILD layer 116 and ESL 118. An additional layer of conductive structure 120 may be formed in interconnect layer 106 in a similar manner.

[0070] The conductive structure 120 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the conductive structure 120 can be planarized using a planarization tool after deposition.

[0071] like Figure 4D As shown, a second portion of the interconnect layer 106 of the semiconductor device 102 is formed over the first portion of the interconnect layer 106. The second portion of the interconnect layer 106 may include ESLs 122, 126, 130, and 134, ILD layers 124, 128, 132, and 136, top vias 138 and 142, and top metal layers 140 and 144. The ESLs 122, 126, 130, and 134, and the ILD layers 124, 128, 132, and 136 are deposited using one or more deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, planarization tools may be used to planarize the ESLs 122, 126, 130, and 134, and the ILD layers 124, 128, 132, and 136.

[0072] like Figure 4DAs further shown, various operations can be performed using deposition tools, exposure tools, developing tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form top vias 138, 142 and top metal layers 140, 144 in a second portion of the interconnect layer 106 of the semiconductor device 102. In some embodiments, ESL 122 and ILD layers 124 may be formed, and recesses may be formed in and / or through ESL 122 and ILD layers 124 (e.g., using exposure tools, developing tools, and / or etching tools), and top vias 138 may be formed in the recesses (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an ESL 126 and an ILD layer 128 may be formed, and a recess may be formed in and / or through the ESL 126 and ILD layers 128 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top metal layer 140 may be formed in the recess (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an ESL 130 and an ILD layer 132 may be formed, and a recess may be formed in and / or through the ESL 130 and ILD layers 132 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top via 142 may be formed in the recess (e.g., using one or more deposition tools and / or one or more planarization tools). In some embodiments, an ESL 134 and an ILD layer 136 may be formed, and a recess may be formed in and / or through the ESL 134 and ILD layer 136 (e.g., using an exposure tool, a development tool, and / or an etching tool), and a top metal layer 144 may be formed in the recess (e.g., using one or more deposition tools and / or one or more planarization tools).

[0073] The top vias 138, 142 and the top metal layers 140, 144 can be deposited using one or more deposition tools via PVD, ALD, CVD, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. In some embodiments, the top vias 138, 142 and the top metal layers 140, 144 can be planarized using a planarization tool after deposition.

[0074] like Figure 4EAs shown, portions of the ESL 146 and dielectric layer 148 of the bonding layer 108 can be formed over the interconnect layer 106. The ESL 146 and dielectric layer 148 portions can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The ESL 146 and dielectric layer 148 portions can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., CMP operation) can be performed using a planarization tool after the deposition of the ESL 146 and dielectric layer 148 portions to planarize the ESL 146 and dielectric layer 148 portions.

[0075] like Figure 4E As further shown, a patterned stack can be formed over a portion of the dielectric layer 148. The patterned stack may include multiple mask layers for forming recesses in which capacitor structures 160 in the semiconductor device 102 can be formed. The mask layers may include an advanced patterning film (APF) layer 404, a bottom anti-reflective coating (BARC) 406 on the APF layer 404, and / or a photoresist layer 408 on the BARC 406, etc. The patterned stacked mask layers can be selected to form the recesses of the capacitor structure 160 in a highly controlled manner, thereby achieving substantially vertical sidewalls (and thus a high aspect ratio) of the capacitor structure 160. The APF layer 404 may include an amorphous carbon material and / or other suitable materials. The BARC 406 may include silicon oxynitride (SiON), polymers, and / or other suitable materials. APF layer 404, BARC 406 and / or photoresist layer 408 can be deposited using deposition tools via PVD, CVD, ALD, spin coating and / or other suitable deposition techniques.

[0076] like Figure 4F As shown, an etching tool can be used to etch portions through dielectric layer 148, through ESL 146, through ILD layer 136, through ESL 134, through ILD layer 132, through ESL 130, through ILD layer 128, through ESL 126, through ILD layer 124, and / or through ESL 122 to form a recess 410. The recess 410 extends through bonding layer 108 and into interconnect layer 106 to reach the underlying conductive structure 120 in interconnect layer 106. The recess 410 may include trenches, vias, and / or other types of recesses.

[0077] In some embodiments, a pattern is formed in the photoresist layer 408, and the pattern is used to form the recess 410. The photoresist layer 408 can be patterned by exposing it to a radiation source using an exposure tool. A developing tool can be used to develop and remove portions of the photoresist layer 408 to reveal the pattern. An etching tool can be used to etch the BARC 406 and / or APF layer 404 based on the pattern to transfer the pattern to the BARC 406 and / or APF layer 404. An etching tool can be used to etch through the ILD layer 136, through ESL 134, through ILD layer 132, through ESL 130, through ILD layer 128, through ESL 126, through ILD layer 124, and / or through ESL 122 based on the pattern in the photoresist layer 408, BARC 406, and / or APF layer 404 to form the recess 410. In some embodiments, the etching operation that forms the recess 410 includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0078] In some implementations, a high aspect ratio of the recess 410 can be achieved using deep reactive ion etching (sometimes referred to as "BOSCH" etching). Deep reactive ion etching is a cyclic etching technique in which multiple deposition and etching cycles are performed using a protective liner to minimize lateral etching. For example, a deep reactive ion etching cycle may include etching the recess 410 to a first depth, forming a protective liner on the sidewalls and bottom of the recess 410, etching the protective liner to remove it from the bottom of the recess 410, and etching the bottom of the recess 410 to increase the depth of the recess 410 to a second depth while the protective liner protects the sidewalls of the recess 410 from lateral etching. Additional cycles may be performed to achieve a specific depth of the recess 410.

[0079] like Figure 4G As shown, the remaining portion of the photoresist layer 408 can be removed using a photoresist removal tool (e.g., using a chemical stripper, plasma ashing, and / or other techniques). Additionally, the remaining portion of BARC 406 and / or APF layer 404 can be removed using an etching tool and / or a planarization tool.

[0080] like Figure 4GAs further shown, a bottom electrode layer 162, an insulating layer 164, a top electrode layer 166, and a dielectric filler 168 may be formed in the recess 410. The bottom electrode layer 162 may be conformally deposited on the sidewalls and bottom surface of the recess 410 (corresponding to the top surface of the conductive structure 120 exposed through the recess 410). The bottom electrode layer 162 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, conformal CVD and / or ALD techniques are used to deposit the bottom electrode layer 162.

[0081] An insulating layer 164 may be deposited on the bottom electrode layer 162. Therefore, the insulating layer 164 is deposited on the sidewalls and bottom surface of the recess 410 (corresponding to the top surface of the conductive structure 120 exposed through the recess 410). The insulating layer 164 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, the insulating layer 164 is conformally deposited using a deposition tool via conformal CVD and / or ALD techniques.

[0082] A top electrode layer 166 may be deposited on the insulating layer 164. Therefore, the top electrode layer 166 is deposited on the sidewalls and bottom surface of the recess 410 (corresponding to the top surface of the conductive structure 120 exposed through the recess 410). The top electrode layer 166 may also be deposited on the top surface of a portion of the dielectric layer 148. In some embodiments, the top electrode layer 166 is conformally deposited using a deposition tool via conformal CVD and / or ALD techniques.

[0083] Dielectric filler 168 may be deposited on top electrode layer 166 to fill the remaining area of ​​recess 410. In some embodiments, dielectric filler 168 is deposited using deposition tools via PVD, CVD, ALD, and / or other suitable deposition techniques.

[0084] like Figure 4G As further shown, capping layers 170 and 172 may be formed over the recess 410. For example, capping layers 170 and 172 may be formed on the top surface of dielectric layer 148. Capping layers 170 and 172 may be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. In some embodiments, a planarization operation (e.g., CMP operation) may be performed using planarization tools after deposition of capping layers 170 and / or 172 to planarize capping layers 170 and / or 172.

[0085] like Figure 4HAs shown, a patterned mask layer 412 may be formed on a portion of the capping layer 172 above the capacitor structure 160. The patterned mask layer 412 may be formed using a deposition tool via spin coating and / or other suitable deposition techniques. The patterned mask layer 412 may be patterned by exposing it to a radiation source using an exposure tool. A development tool may be used to develop and remove portions of the patterned mask layer 412 to expose the pattern.

[0086] like Figure 4I As shown, the patterned mask layer 412 can be used to etch and define the capping layers 170 and 172, the top electrode layer 166, and / or the insulating layer 164 of the capacitor structure 160. An etching tool can be used to etch the capping layers 170 and 172, the top electrode layer 166, and / or the insulating layer 164 based on the patterned mask layer 412. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the patterned mask layer 412 (e.g., using chemical strippers, plasma ashing, and / or other techniques).

[0087] like Figure 4J As shown, sidewall spacers 174 and 176 are formed on the ends of insulating layer 164, top electrode layer 166, capping layer 170, and / or capping layer 172. Sidewall spacers 174 and 176 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. Sidewall spacers 174 and 176 can be deposited in one or more deposition operations.

[0088] like Figure 4K As shown, another etching operation can be performed to trim the portion of the bottom electrode layer 162 above the top surface of the dielectric layer 148 portion to define the bottom electrode layer 162 of the capacitor structure 160. The capping layer 172 and sidewall spacers 174 and 176 can be used as self-aligned masks to etch the bottom electrode layer 162. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations.

[0089] like Figure 4LAs shown, additional portions of the dielectric layer 148 can be formed on top of the capacitor structure 160 and on the first portion of the dielectric layer 148. The top of the capacitor structure 160 can be encapsulated within the dielectric layer 148. An ESL 150 of the bonding layer 108 can be formed on the dielectric layer 148, a dielectric layer 152 of the bonding layer 108 can be formed on the ESL 150, and a bonding dielectric layer 158 of the bonding layer 108 can be formed on the dielectric layer 152. The additional portions of the dielectric layer 148, the ESL 150, the dielectric layer 152, and / or the bonding dielectric layer 158 can be deposited using deposition tools via PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The additional portions of the dielectric layer 148, the ESL 150, the dielectric layer 152, and / or the bonding dielectric layer 158 can be deposited in one or more deposition operations. In some implementations, a planarization operation (e.g., a CMP operation) can be performed using a planarization tool to planarize dielectric layer 148, ESL 150, dielectric layer 152, and / or bonding dielectric layer 158.

[0090] like Figure 4M As shown, a via portion of recess 414 may be formed above capacitor structure 160. The via portion of recess 414 may be formed such that it extends through a portion of bonding dielectric layer 158, through dielectric layer 152, through ESL 150, through a portion of dielectric layer 148, through capping layers 170 and 172 of capacitor structure 160, and reaches the top electrode layer 166 of capacitor structure 160. In some embodiments, the via portion of recess 414 is formed into a portion of top electrode layer 166 such that the bottom of the via portion of recess 414 is recessed in top electrode layer 166. Similarly, the via portion of recess 416 may be formed to extend through bonding dielectric layer 158, through dielectric layer 152, through ESL 150, through dielectric layer 148, through ESL 146, and reach the top metal layer 144 in interconnect layer 106.

[0091] In some embodiments, the pattern in the photoresist layer is used to form the via portions of recess 414 and recess 416. In these embodiments, the photoresist layer can be formed on the bonding dielectric layer 158 using a deposition tool (e.g., using spin coating and / or other suitable deposition techniques). The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A developing tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch through the bonding dielectric layer 158, through the dielectric layer 152, through the ESL 150, through the dielectric layer 148, and through the ESL 146 based on the pattern to form the via portions of recess 414 and / or recess 416. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or other types of etching operations. In some embodiments, the remaining portion of the photoresist layer can be removed using a photoresist removal tool (e.g., using chemical strippers, plasma ashing, and / or other techniques). In some embodiments, a hard mask layer is used as an alternative technique for the via portions of pattern-forming recess 414 and / or recess 416.

[0092] like Figure 4N As shown, a plug 418 can be formed in the bottom of recesses 414 and 416. The plug 418 can be formed by forming a photoresist layer or other suitable plug material layer (e.g., dielectric layer) in the via portion of recesses 414 and 416, and trimming the photoresist layer (e.g., by photolithography) so that the remaining portion of the photoresist layer remains at the bottom of recesses 414 and 416.

[0093] like Figure 4O As shown, the trench portions of recess 414 and recess 416 are formed to penetrate the bonding dielectric layer 158, the dielectric layer 152, and / or the ESL 150. Therefore, recesses 414 and 416 can be dual-damascene recesses. Although Figures 4M to 4O The via-first dual damascene process is shown, but recesses 414 and 416 can also be formed via a trench-first dual damascene process. A plug 418 in the bottom of recesses 414 and 416 (e.g., the via portion) protects the bottom of recesses 414 and 416 from further etching during the etching of the trench portions of recesses 414 and 416 (thus preventing further critical dimension enlargement).

[0094] like Figure 4PAs shown, a bonding via 154 is formed in the via portions of recesses 414 and 416, and a bonding pad 156 is formed on the bonding via 154 in the trench portions of recesses 414 and 416. The bonding via 154 formed in the via portion of recess 414 lands on the top electrode layer 166 of the capacitor structure 160. As described above, the via portion of recess 414 can extend into a portion of the top electrode layer 166. Therefore, the bonding via 154 formed in the via portion of recess 414 can be recessed into a portion of the top electrode layer 166. In other words, the bottom surface of the bonding via 154 formed in the via portion of recess 414 can be located below the top surface of the top electrode layer 166. The bonding via 154 formed in the via portion of recess 416 lands on the top of the top metal layer 144 exposed through recess 416.

[0095] The bonding vias 154 and bonding pads 156 can be deposited using deposition tools via CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The bonding vias 154 and bonding pads 156 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited in recesses 414 and 416, and then the bonding vias 154 and bonding pads 156 are deposited on the seed layer. In some embodiments, a liner (e.g., an adhesive liner, a barrier liner) is first deposited in recesses 414 and 416, and then the bonding vias 154 and bonding pads 156 are deposited on the liner. The liner may include a suitable backing material, such as tantalum nitride (TaN) and / or titanium nitride (TiN). In some embodiments, after depositing the bonding vias 154 and bonding pads 156, a planarization operation (e.g., a CMP operation) is performed using planarization tools to planarize the bonding pads 156.

[0096] As mentioned above, Figures 4A to 4P Examples are provided. Other examples can be found in the section about... Figures 4A to 4P The descriptions are different.

[0097] Figures 5A to 5C This is a diagram of an example embodiment 500 of forming a semiconductor device 102 as described herein. In particular, example embodiment 500 includes forming... Figure 2 This is an example of an exemplary embodiment 200 of the semiconductor device 102 shown. However, it is possible to combine... Figures 5A to 5C Another example embodiment of the semiconductor device 102 described herein is illustrated by one or more semiconductor processing operations. In some embodiments, one or more semiconductor processing tools may be used to perform the combination. Figures 5A to 5C The description includes one or more semiconductor processing operations, semiconductor processing tools such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0098] like Figure 5A As shown, executable combination Figures 4A to 4K One or more semiconductor processing operations are described to form component layer 104, interconnect layer 106, and capacitor structure 160. However, in example embodiment 500, the steps of forming ESL 146 and dielectric layer 148 are omitted. Instead, ESL 150 is formed on ILD layer 136, dielectric layer 152 is formed on ESL 150, and bonding dielectric layer 158 is formed on dielectric layer 152. The recess 410 for capacitor structure 160 may be formed to extend through dielectric layer 152 and through ESL 150, rather than through dielectric layer 148 and through ESL 146.

[0099] like Figure 5B As shown, a recess 502 may be formed above the capacitor structure 160. The recess 502 may be formed such that it extends through the bonding dielectric layer 158, through a portion of the dielectric layer 152, through the capping layers 170 and 172 of the capacitor structure 160, and reaches the top electrode layer 166 of the capacitor structure 160. In some embodiments, the recess 502 is formed in a portion of the top electrode layer 166 such that the bottom of the recess 502 is recessed within the top electrode layer 166.

[0100] like Figure 5B As further shown, the recess 504 may be formed to extend through the bonding dielectric layer 158, through the dielectric layer 152, and through the ESL 150 to reach the top metal layer 144. The recesses 502 and 504 may be trench-shaped, pad-shaped, and / or other shapes with substantially vertical sidewalls.

[0101] like Figure 5C As shown, a bonding pad 156 is formed in recess 502 such that the bonding pad 156 lands on the top electrode layer 166 of the capacitor structure 160. As described above, recess 502 can extend into a portion of the top electrode layer 166. Therefore, the bonding pad 156 can be recessed into a portion of the top electrode layer 166. In other words, the bottom surface of the bonding pad 156 can be located below the top surface of the top electrode layer 166. The bonding pad 156 can also be formed in recess 504 such that the bonding pad 156 lands on the top metal layer 144. In some embodiments, after the bonding pad 156 is formed in recesses 502 and 504, a planarization tool can be used to planarize the bonding pad 156.

[0102] As mentioned above, Figures 5A to 5C Provided as an example. Other examples are available with reference to [link / reference]. Figures 5A to 5C The descriptions are different.

[0103] Figure 6A and Figure 6BThis is a diagram of an example embodiment 600 of the semiconductor package 602 described herein. (See diagram below.) Figure 6A As shown in the cross-sectional view of semiconductor package 602, semiconductor package 602 is a 3D structure, which includes semiconductor dies 102a and 102b directly bonded together at a bonding interface 604, such that semiconductor dies 102a and 102b are stacked and vertically arranged in semiconductor package 602. Semiconductor dies 102a and 102b may each include components related to... Figure 1 The example embodiment 100 of the semiconductor device 102 shown is similar to the combination and arrangement of layers and / or structures, and can be combined with Figures 4A to 4P The same semiconductor processing operations and / or techniques are used to form it.

[0104] At the bonding interface 604, semiconductor dies 102a and 102b can be bonded together by a combination of metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the bonding pad 156 of semiconductor die 102a can be bonded to the bonding pad 156 of semiconductor die 120b at the bonding interface 604 in a metal-to-metal manner. As another example, the bonding dielectric layer 158 of semiconductor die 102a can be bonded to the bonding dielectric layer 158 of semiconductor die 102b at the bonding interface 604 in a dielectric-to-dielectric manner.

[0105] In some embodiments, misalignment may occur between the bonding pad 156 of semiconductor die 102a and the bonding pad 156 of semiconductor die 102b at the bonding interface 604. Therefore, a misalignment region 606 may appear on one or more sides of the bonding between the bonding pads 156 of semiconductor dies 102a and 102b. The misalignment region 606 may include the portion of the bonding surface of the bonding pad 156 of semiconductor die 102a that contacts the bonding dielectric layer 158 of semiconductor die 102b. Another misalignment region 606 may include the portion of the bonding surface of the bonding pad 156 of semiconductor die 102b that contacts the bonding dielectric layer 158 of semiconductor die 102a. In other words, the bonding pads 156 are misaligned laterally, such that the edges of the bonding pads 156 of the bonded semiconductor dies 102a and 102b may be misaligned.

[0106] In some embodiments, semiconductor package 602 is an image sensor device (e.g., a 3D CIS device). Therefore, semiconductor die 102a may include an application-specific integrated circuit (ASIC) die for the image sensor device, while semiconductor die 102b may include an image sensor die for the image sensor device. Therefore, semiconductor die 102b may include a plurality of pixel sensors 608 in its substrate layer 110. Pixel sensors 608 may be configured to absorb photons of incident light and convert them into photocurrent to generate images and / or video. Semiconductor die 102a and / or semiconductor die 102b may include one or more capacitor structures 160 configured to store the charge of the pixel sensors 608 to increase the field of view (FWC) of the pixel sensors 608 and / or enable the global shutter function in semiconductor die 102b.

[0107] For example, semiconductor die 102a may include a capacitor structure 160 directly connected to a bonding via 154 in a bonding layer 108 of semiconductor die 102a. The capacitor structure 160 is electrically connected to a bonding pad 156 of semiconductor die 102b via the bonding via 154 and through a bonding pad 156 of semiconductor die 102a, wherein the bonding pad 156 of semiconductor die 102a is physically connected to the bonding via 154 and the bonding pad 156 of semiconductor die 102b. This allows the capacitor structure 160 disposed in semiconductor die 102a to be electrically connected to a pixel sensor 608 disposed in semiconductor die 102b.

[0108] Additionally and / or as an alternative, semiconductor die 102b may include a capacitor structure 160 directly connected to a bonding via 154 in bonding layer 108 of semiconductor die 102b. The capacitor structure 160 may be electrically connected to bonding pad 156 of semiconductor die 102a via the bonding via 154 and via bonding pad 156 of semiconductor die 102b, wherein bonding pad 156 of semiconductor die 102b is physically connected to the bonding via 154 and bonding pad 156 of semiconductor die 102a.

[0109] Figure 6B A top view of a semiconductor package 602 is shown, along with an example of a pixel sensor array 610 including multiple pixel sensors 608. (As shown) Figure 6B As shown, pixel sensors 608 can be arranged in a grid within pixel sensor array 610. (As...) Figure 6B As further shown, the peripheral region 612 may laterally surround the pixel sensor array 610. The peripheral region 612 may include other functional structures of the semiconductor package 602, such as black level correction (BLC) structures and / or other pixel circuit components (e.g., source follower transistors, row select transistors).

[0110] like Figure 6B As further shown, the capacitor structure 160 disposed in semiconductor die 102a and / or semiconductor die 102b may be located below the pixel sensor 608 of the pixel sensor array 610. Figure 6A The location of the section shown is determined by... Figure 6B The AA line is indicated in the diagram. The bonding pads 156 and bonding vias 154 of semiconductor dies 102a and 102b provide an "in-pixel" connection between the pixel sensors 608 of the pixel sensor array 610, because the capacitor structure 160 on semiconductor die 102a can be located below the pixel sensor 608, and the capacitor structure 160 on semiconductor die 102a can be electrically connected to the pixel sensor 608 through the bonding vias 154 and bonding pads 156 of semiconductor dies 102a and 102b below the pixel sensor 608.

[0111] As mentioned above, it can provide Figure 6A and Figure 6B As an example. Other examples can be found in relation to... Figure 6A and Figure 6B The descriptions are different.

[0112] Figure 7A and Figure 7B This is a diagram of an example embodiment 700 of the semiconductor package 702 described herein. (See diagram below.) Figure 7A As shown in the cross-sectional view of the semiconductor package 702, the semiconductor package 702 is a 3D structure, which includes semiconductor dies 102a and 102b directly bonded together at a bonding interface 704, such that semiconductor dies 102a and 102b are stacked and vertically arranged in the semiconductor package 702. Semiconductor dies 102a and 102b may each include components related to… Figure 2 The example embodiment 200 of the semiconductor device 102 shown is similar to the combination and arrangement of layers and / or structures, and can be combined with Figures 4A to 4P and / or Figures 5A to 5C The same semiconductor processing operations and / or techniques are used to form it.

[0113] At the bonding interface 704, semiconductor dies 102a and 102b can be bonded together via a combination of metal-to-metal bonding and dielectric-to-dielectric bonding. For example, the bonding pad 156 of semiconductor die 102a can be bonded to the bonding pad 156 of semiconductor die 120b at the bonding interface 704 in a metal-to-metal manner. As another example, the bonding dielectric layer 158 of semiconductor die 102a can be bonded to the bonding dielectric layer 158 of semiconductor die 102b at the bonding interface 704 in a dielectric-to-dielectric manner.

[0114] In some embodiments, misalignment may occur between the bonding pad 156 of semiconductor die 102a and the bonding pad 156 of semiconductor die 102b at the bonding interface 704. Therefore, a misalignment region 706 may appear on one or more sides of the bonding between the bonding pads 156 of semiconductor dies 102a and 102b. The misalignment region 706 may include the portion of the bonding surface of the bonding pad 156 of semiconductor die 102a that contacts the bonding dielectric layer 158 of semiconductor die 102b. Another misalignment region 706 may include the portion of the bonding surface of the bonding pad 156 of semiconductor die 102b that contacts the bonding dielectric layer 158 of semiconductor die 102a. In other words, the bonding pads 156 are misaligned laterally, such that the edges of the bonding pads 156 of the joined semiconductor dies 102a and 102b may be misaligned.

[0115] In some embodiments, the semiconductor package 702 is an image sensor device (e.g., a 3D CIS device). Therefore, semiconductor die 102a may include an ASIC die for the image sensor device, while semiconductor die 102b may include an image sensor die for the image sensor device. Thus, semiconductor die 102b may include a plurality of pixel sensors 708 in its substrate layer 110. Pixel sensors 708 may be configured to absorb photons of incident light and convert them into photocurrent to generate images and / or video. Semiconductor die 102a and / or semiconductor die 102b may include one or more capacitor structures 160 configured to store the charge of the pixel sensors 708 to increase the field of view (FWC) of the pixel sensors 708 and / or enable the global shutter function in semiconductor die 102b.

[0116] For example, semiconductor die 102a may include a capacitor structure 160 directly connected to bonding pads 156 in bonding layer 108 of semiconductor die 102a. The capacitor structure 160 can be electrically connected to bonding pads 156 of semiconductor die 102b via bonding pads 156 of semiconductor die 102a (which are bonded to bonding pads 156 on semiconductor die 102b). This allows the capacitor structure 160 disposed in semiconductor die 102a to be electrically connected to a pixel sensor 708 disposed in semiconductor die 102b.

[0117] Additionally and / or as an alternative, semiconductor die 102b may include a capacitor structure 160 directly connected to a bonding pad 156 in a bonding layer 108 of semiconductor die 102b. The capacitor structure 160 may be electrically connected to the bonding pad 156 of semiconductor die 102a via the bonding pad 156 of semiconductor die 102b (which is bonded to the bonding pad 156 on semiconductor die 102a).

[0118] Figure 7B A top view of a semiconductor package 702 is shown, along with an example of a pixel sensor array 710 including multiple pixel sensors 708. (As shown) Figure 7B As shown, the pixel sensors 708 can be arranged in a grid within the pixel sensor array 710. (As...) Figure 7B As further shown, the peripheral region 712 may laterally surround the pixel sensor array 710. The peripheral region 712 may include other functional structures of the semiconductor package 702, such as a BLC structure and / or other pixel circuit components (e.g., source follower transistors, row select transistors).

[0119] like Figure 7B As further shown, the capacitor structure 160 disposed in semiconductor die 102a and / or semiconductor die 102b may be located around the pixel sensor array 710. For example, the capacitor structure 160 may be located in the peripheral region 712, which may correspond to the die edge or die periphery of semiconductor die 102a and / or semiconductor die 102b. Figure 7A The location of the section shown is determined by... Figure 7B The line BB is indicated in the image. The bonding pads 156 around the semiconductor dies 102a and 102b provide a connection between the pixel sensor 708 of the pixel sensor array 710 and the capacitor structure 160 on the semiconductor die 102a.

[0120] As mentioned above, it can provide Figure 7A and Figure 7B As an example. Other examples can be found in relation to... Figure 7A and Figure 7B The descriptions are different.

[0121] Figure 8A and Figure 8B This is a diagram illustrating an example embodiment of the semiconductor device 102 described herein. Figure 8A As shown, an example embodiment 800 of the semiconductor device 102 may include [the following]. Figure 1 The example embodiment 100 of the semiconductor device 102 shown illustrates combinations and arrangements of layers and / or structures similar to those in the example embodiment 100. However, in Figure 8A In the example embodiment 800, in addition to the top electrode layer 166 of the capacitor structure 160 being directly connected (e.g., physically and / or electrically) to the bonding via 154 in the bonding layer 108, the bottom electrode layer 162 of the capacitor structure 160 is also directly connected (e.g., physically and / or electrically) to another bonding via 154 in the bonding layer 108. Therefore, relative to Figure 1 In example embodiment 100, the bottom electrode layer 162 of the capacitor structure 160 has a bottom connection in the interconnect layer 106 at the bottom of the capacitor structure 160. Figure 8AIn the example embodiment 800, the bottom electrode layer 162 and the top electrode layer 166 of the capacitor structure 160 each have a top connection at the top of the capacitor structure 160.

[0122] like Figure 8B As shown, an example embodiment 802 of the semiconductor device 102 may include [the following]. Figure 2 The example embodiment 200 of the semiconductor device 102 shown illustrates combinations and arrangements of layers and / or structures similar to those in other embodiments. However, in Figure 8B In example embodiment 802, in addition to the top electrode layer 166 of capacitor structure 160 being directly connected (e.g., physically and / or electrically) to bonding pad 156, the bottom electrode layer 162 of capacitor structure 160 is also directly connected (e.g., physically and / or electrically) to another bonding pad 156 in bonding layer 108. Therefore, relative to Figure 2 In Example Implementation 200, the bottom electrode layer 162 of the capacitor structure 160 has a bottom connection in the interconnect layer 106 at the bottom of the capacitor structure 160. Figure 8B In Example Implementation 802, the bottom electrode layer 162 and the top electrode layer 166 of the capacitor structure 160 each have a top connection at the top of the capacitor structure 160.

[0123] As mentioned above, providing Figure 8A and Figure 8B As an example. Other examples can be found in relation to... Figure 8A and Figure 8B The descriptions are different.

[0124] Figure 9 This is a flowchart of an example process 900 related to the formation of the semiconductor device described herein. In some embodiments, Figure 9 One or more process blocks are performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transfer tools, and / or other types of semiconductor processing tools.

[0125] like Figure 9 As shown, process 900 may include forming one or more integrated circuit components in a component layer of a semiconductor device (block 910). For example, one or more integrated circuit components (e.g., one or more integrated circuit components 112) may be formed in a component layer (e.g., component layer 104) of a semiconductor device (e.g., semiconductor device 102, semiconductor die 102a, semiconductor die 102b) using one or more semiconductor processing tools, as described herein.

[0126] like Figure 9As further illustrated herein, process 900 may include forming an interconnect layer of a semiconductor device over the component layer (block 920). For example, one or more semiconductor processing tools may be used to form an interconnect layer of a semiconductor device (e.g., interconnect layer 106) over the component layer, as described herein.

[0127] like Figure 9 As further illustrated herein, process 900 may include forming recesses (box 930) through multiple dielectric layers of the interconnect layer. For example, recesses (e.g., recess 410) through multiple dielectric layers (e.g., ESL122, 126, 130, 134, and / or 146, ILD layers 124, 128, 132, and / or 136) of the interconnect layer may be formed using one or more semiconductor processing tools, as described herein.

[0128] like Figure 9 As further shown, process 900 may include forming a trench capacitor structure of a semiconductor device in a recess (block 940). For example, one or more semiconductor processing tools may be used to form the trench capacitor structure of the semiconductor device in the recess (e.g., capacitor structure 160), as described herein.

[0129] like Figure 9 As further shown, process 900 may include forming a bonding structure for a semiconductor device on the trench capacitor structure (block 950). For example, one or more semiconductor processing tools may be used to form the bonding structure for the semiconductor device (e.g., bonding via 154, bonding pad 156) on the trench capacitor structure, as described herein.

[0130] Process 900 may include additional implementations, such as any single implementation or any combination of implementations described below and / or combined with one or more other processes described elsewhere herein.

[0131] In a first embodiment, process 900 includes bonding a semiconductor device to another semiconductor device (e.g., semiconductor device 102, semiconductor die 102a, semiconductor die 102b) such that a bonding structure is directly bonded to another bonding structure of the other semiconductor device (e.g., bonding pad 156).

[0132] In the second embodiment, either alone or in combination with the first embodiment, process 900 includes forming a bonding dielectric layer (e.g., bonding dielectric layer 158), forming a bonding structure through the bonding dielectric layer, and bonding a semiconductor device to another semiconductor device such that the bonding dielectric layer is directly bonded to another bonding dielectric layer (e.g., another bonding dielectric layer 158) surrounding another bonding structure of the other semiconductor device.

[0133] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the bonding structure is misaligned with another bonding structure, such that a first portion of the bonding surface of the bonding structure is bonded to the other bonding structure, and a second portion of the bonding surface (e.g., misaligned region 706) is in contact with another bonding dielectric layer.

[0134] In the fourth embodiment, forming a bonding structure, either alone or in combination with one or more of the first to third embodiments, includes forming a bonding via (e.g., bonding via 154) on the top electrode (e.g., top electrode layer 166) of the trench capacitor structure, and process 900 includes forming a bonding pad (e.g., bonding pad 156) on the bonding via.

[0135] although Figure 9 The diagram shows an example block of process 900, but in some embodiments, process 900 includes... Figure 9 The blocks shown are compared to additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally, or as an alternative, two or more blocks of process 900 can be executed in parallel.

[0136] In this manner, a capacitor structure is disposed within the interconnect layer of a semiconductor die, which is bonded to another semiconductor die in a vertical stack. To increase the vertical length of the capacitor structure, the top electrode layer of the capacitor structure is directly connected to the bonding structure of the semiconductor die, rather than being connected to the bonding structure via one or more intermediate conductive structures in the interconnect layer. This allows the capacitor structure to extend vertically through more layers of the interconnect layer, thereby increasing the length of the top and bottom electrode layers and increasing the capacitance of the capacitor structure. The increased capacitance of the capacitor structure enables enhanced performance in the semiconductor device.

[0137] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a component layer. The semiconductor device includes one or more integrated circuit components in the component layer. The semiconductor device includes an interconnect layer above the component layer. The semiconductor device includes one or more conductive structures in the interconnect layer. The semiconductor device includes one or more bonding structures above the interconnect layer. The semiconductor device includes a trench capacitor structure directly coupled to one of the bonding structures.

[0138] In some embodiments, the bonding structure includes a bonding via; wherein one or more bonding structures include bonding pads; and wherein the bonding pads are coupled to the bonding via. In some embodiments, wherein the top electrode layer of the trench capacitor structure contacts the bonding via; and wherein the bottom electrode layer of the trench capacitor structure contacts a conductive structure in one or more conductive structures. In some embodiments, the bottom surface of the bonding via is recessed in the top electrode layer. In some embodiments, the bonding structure includes a bonding pad. In some embodiments, wherein the top electrode layer of the trench capacitor structure contacts the bonding pad; and wherein the bottom electrode layer of the trench capacitor structure contacts a conductive structure in one or more conductive structures. In some embodiments, the bottom surface of the bonding pad is recessed in the top electrode layer.

[0139] As described in more detail above, some embodiments described herein provide a semiconductor package. The semiconductor package includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first interconnect layer, one or more first conductive structures in the first interconnect layer, a plurality of first bonding structures above the first interconnect layer, and a trench capacitor structure directly coupled to one of the first bonding structures. The second semiconductor die is bonded to the first semiconductor die at a bonding interface such that the first semiconductor die and the second semiconductor die are vertically aligned in the semiconductor package. The second semiconductor die includes a second interconnect layer, one or more second conductive structures in the second interconnect layer, and a plurality of second bonding structures below the second interconnect layer. One of the plurality of second bonding structures is electrically coupled to the first bonding structure.

[0140] In some embodiments, the first bonding structure includes a first bonding pad; and the second bonding structure includes a second bonding pad. In some embodiments, the first bonding pad is bonded to the second bonding pad; and the first bonding pad is laterally offset relative to the second bonding pad. In some embodiments, the second semiconductor die further includes a pixel sensor array including a plurality of pixel sensors, wherein a trench capacitor structure is located below the pixel sensor array. In some embodiments, the first bonding structure includes a bonding via; and the second bonding structure includes a bonding pad. In some embodiments, the bonding via is coupled to another bonding pad in the second semiconductor die; and the bonding pad in the second semiconductor die is bonded to another bonding pad in the first semiconductor die. In some embodiments, the second semiconductor die further includes a pixel sensor array including a plurality of pixel sensors, wherein a trench capacitor structure is located below a peripheral region laterally surrounding the pixel sensor array. In some embodiments, the second semiconductor die further includes another trench capacitor structure directly coupled to a third bonding structure of a plurality of second bonding structures of the second semiconductor die, wherein a fourth bonding structure of a plurality of first bonding structures of the first semiconductor die is electrically coupled to the third bonding structure of the second semiconductor die.

[0141] As described in more detail above, some embodiments described herein provide a method. The method includes forming one or more integrated circuit components in a component layer of a semiconductor device. The method includes forming an interconnect layer of the semiconductor device above the component layer. The method includes forming recesses through a plurality of dielectric layers passing through the interconnect layer. The method includes forming a trench capacitor structure of the semiconductor device in the recesses. The method includes forming a bonding structure of the semiconductor device on the trench capacitor structure.

[0142] In some embodiments, the method further includes bonding a semiconductor device to another semiconductor device such that the bonding structure is directly bonded to another bonding structure of the other semiconductor device. In some embodiments, the method further includes: forming a bonding dielectric layer; forming a bonding structure through the bonding dielectric layer; and bonding a semiconductor device to another semiconductor device such that the bonding dielectric layer is directly bonded to another bonding structure surrounding the other bonding structure of the other semiconductor device. In some embodiments, the bonding structure is misaligned with the other bonding structure such that a first portion of the bonding surface of the bonding structure engages with the other bonding structure, and a second portion of the bonding surface contacts the other bonding dielectric layer. In some embodiments, forming the bonding structure includes forming a bonding via on the top electrode layer of the trench capacitor structure, wherein the method further includes forming a bonding pad on the bonding via.

[0143] The terms "approximately" and "substantially" can indicate that a given quantity varies within a range of 5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and not intended to be limiting. It should be understood that the terms "approximately" and "substantially" can refer to a given quantity as a percentage of the content of this utility model.

[0144] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A semiconductor device, characterized in that, include: Component layer; One or more integrated circuit components are located in the component layer; An interconnect layer is located above the component layer; One or more conductive structures are located in the interconnect layer; One or more bonding structures are located above the interconnect layer; as well as The trench capacitor structure is directly coupled to the bonding structure in one or more bonding structures.

2. The semiconductor device according to claim 1, characterized in that, The joining structure includes a joining guide hole; The one or more engagement structures mentioned above include engagement pads; and The bonding pad is coupled to the bonding guide hole.

3. The semiconductor device according to claim 2, characterized in that, The top electrode layer of the trench capacitor structure is in contact with the bonding via; and The bottom electrode layer of the trench capacitor structure is in contact with the conductive structure in one or more conductive structures.

4. The semiconductor device according to claim 3, characterized in that, The bottom surface of the bonding guide hole is recessed in the top electrode layer.

5. A semiconductor package, characterized in that, include: The first semiconductor die includes: First interconnect layer; One or more first conductive structures are located in the first interconnect layer; Multiple first bonding structures are located above the first interconnect layer; and A trench capacitor structure, directly coupled to a first bonding structure among the plurality of first bonding structures; and A second semiconductor die is bonded to the first semiconductor die at a bonding interface, such that the first semiconductor die and the second semiconductor die are arranged perpendicularly in the semiconductor package. The second semiconductor die includes: Second interconnect layer; One or more second conductive structures are located in the second interconnect layer; and Multiple second bonding structures are located below the second interconnect layer. The second bonding structure of the plurality of second bonding structures is electrically coupled to the first bonding structure.

6. The semiconductor package according to claim 5, characterized in that, The first bonding structure includes a first bonding pad; and The second bonding structure includes a second bonding pad.

7. The semiconductor package according to claim 6, characterized in that, The first bonding pad is engaged with the second bonding pad; and The first bonding pad is laterally misaligned relative to the second bonding pad.

8. The semiconductor package according to claim 6, characterized in that, The second semiconductor die also includes: A pixel sensor array, comprising multiple pixel sensors, The trench capacitor structure is located below the pixel sensor array.

9. The semiconductor package according to claim 5, characterized in that, The first bonding structure includes a bonding guide hole; and The second bonding structure includes a bonding pad.

10. The semiconductor package according to claim 5, characterized in that, The second semiconductor die also includes: Another trench capacitor structure is directly coupled to a third bonding structure among the plurality of second bonding structures of the second semiconductor die. The fourth bonding structure of the plurality of first bonding structures of the first semiconductor die is electrically coupled to the third bonding structure of the second semiconductor die.

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