Dam-based storage computing power chip packaging structure

Abstract

The utility model discloses a kind of storage computing power chip packaging structures based on dam, including circuit carrier plate, storage packaging unit, computing power packaging unit, the storage packaging unit includes installation on the circuit carrier plate and is electrically connected with the circuit carrier plate by electric connector storage bare chip, spacing ring around the storage bare chip and its electric connector first dam, and first encapsulation is filled in the first dam and the storage bare chip and electric connector are wrapped in and encapsulated on the circuit carrier plate, the computing power packaging unit includes installation on the circuit carrier plate and is electrically connected with the circuit carrier plate computing power chip.Compared with prior art, the utility model can effectively prevent dispensing area diffusion, allow storage bare chip and computing power chip to be laid out with closer spacing, significantly reduce the interconnection distance between chip, reduce overall package size.

Description

Technical Field

[0001] This utility model relates to semiconductor packaging, and more particularly to the packaging of storage computing chips. Background Technology

[0002] Against the backdrop of explosive growth in computing power demand, the "memory wall" problem caused by the separation of storage and computing units in traditional computing architectures is becoming increasingly prominent—data transmission between independently packaged chips faces fundamental bottlenecks such as high latency, limited bandwidth, and high power consumption. To address this challenge, the industry has generally explored in-memory computing technology. Current mainstream in-memory computing solutions often involve first packaging one or more bare memory dies, and then mounting them as independent components onto the system-on-a-chip (SoC) substrate. This secondary packaging structure physically introduces multiple interconnect interfaces—signals must traverse a lengthy path: "bare memory die → packaging substrate → solder balls → PCB substrate → computing chip." This not only significantly increases wire impedance and parasitic capacitance and inductance, leading to limited signal transmission rates, increased latency, and higher power consumption, but also makes signal integrity control at high frequencies extremely complex, severely restricting further breakthroughs in system performance and failing to meet the essential requirements of in-memory computing architectures for high-bandwidth, low-latency interconnects.

[0003] To shorten the interconnection distance between the memory die and the computing chip, the following approach can be adopted: the memory die is directly mounted on the substrate surface in bare die form, and electrical interconnection with the substrate is achieved through wire bonding. To further ensure the mechanical reliability of the bonding wires and control signal interference, adhesive dispensing is required for protection on this structure. However, in practical applications, this dispensing process suffers from the difficulty in precisely controlling the rheological properties of the adhesive, which is prone to uncontrolled diffusion due to adhesive viscosity, dispensing parameters, or environmental fluctuations. To prevent adhesive overflow from contaminating the pads or affecting adjacent components, the layout safety spacing must be increased during the design phase, that is, the distance between the memory die and the computing chip must be increased. This design principle not only increases the physical area occupied by a single chip on the substrate but also makes it difficult to further reduce the overall package size, thus limiting the miniaturization and high-density integration of system-in-package.

[0004] Therefore, there is an urgent need for a storage computing chip packaging structure that can solve the above problems. Utility Model Content

[0005] The purpose of this invention is to provide a storage computing chip packaging structure based on a dam, which can effectively prevent the diffusion of the adhesive area, allow the storage die and the computing chip to be laid out at a closer distance, significantly reduce the interconnection distance between chips, and reduce the overall package size.

[0006] To achieve the above objectives, this utility model provides a storage computing chip packaging structure based on a dam, including a circuit board, a storage packaging unit, and a computing packaging unit. The storage packaging unit includes a storage die, a first dam, and a first package. The storage die is mounted on the circuit board and electrically connected to the circuit board via an electrical connector. The first dam surrounds the storage die and its electrical connector. The first package fills the first dam and encapsulates the storage die and electrical connector within it, and is packaged on the circuit board. The first package completely encapsulates the electrical connector, and its top surface height relative to the circuit board is higher than or equal to the top surface height of the tallest storage die in the storage packaging unit. The computing packaging unit includes a computing chip, which is mounted on the circuit board and electrically connected to the circuit board.

[0007] Preferably, a heat sink is also installed on the circuit board, the heat sink housing the storage packaging unit and the computing power packaging unit, and the heat sink is spaced apart from the storage packaging unit and the computing power packaging unit.

[0008] Preferably, the first dam is an epoxy resin ring wall or a polyimide ring wall.

[0009] Preferably, the thickness of the first cofferdam is 150-300 μm.

[0010] Preferably, the memory die is electrically connected to the circuit board via an electrical connector, which is enclosed in the first package. The electrical connector is an arc-shaped bonding wire soldered between the electrode pins of the memory die and the pads on the circuit board. The arc-shaped bonding wire enclosed in the first package can effectively distribute stress and suppress signal crosstalk.

[0011] Preferably, the distance between the storage die and the computing chip is 3 to 4 mm.

[0012] Preferably, the computing chip is flip-chip soldered onto the circuit board, and the space between the underside of the computing chip and the circuit board is filled with a protective colloid that wraps the flip-chip pins of the computing chip.

[0013] Preferably, the computing power packaging unit further includes a second enclosure surrounding the computing power chip, and a second package that fills the second enclosure, encapsulates the computing power chip, and is packaged on the circuit board, so as to increase the connection stability between the computing power packaging unit and the circuit board.

[0014] Preferably, the memory bare dies are stacked in multiple staggered positions on the circuit board to form a chip stack structure.

[0015] Preferably, the first encapsulation body is an epoxy encapsulation body or a polyimide encapsulation body.

[0016] Preferably, there are multiple storage packaging units arranged adjacent to the computing power packaging units.

[0017] Compared with existing technologies, in this invention, the bare memory die does not require pre-encapsulation and is directly mounted on the circuit board in the form of a bare die, effectively avoiding the volume waste caused by redundant structures such as lead frames and plastic encapsulation in traditional packages. Furthermore, in this invention, the bare memory die is mounted on the circuit board, and after a first dam surrounds the bare memory die, the first package encapsulating the bare memory die and its electrical connectors is filled and solidified within the first dam. This increases the stability of the electrical connection between the bare memory die and the circuit board while preventing glue overflow during encapsulation from contaminating the circuit board. The flow range of the first package during glue dispensing is limited to the first dam, eliminating the need for an excessively large safety distance to prevent glue overflow. This allows the bare memory die and the computing chip to be arranged at a closer distance, thereby compressing the physical distance between the bare memory die and the computing chip, significantly reducing the interconnection distance between chips and the overall package size. Attached Figure Description

[0018] Figure 1 This is a structural diagram of the storage computing chip packaging structure based on the dam in Embodiment 1 of this utility model.

[0019] Figure 2 This is a top view of the storage computing chip packaging structure based on the dam in Embodiment 1 of this utility model.

[0020] Figure 3 This is a top view of the storage computing chip packaging structure based on the dam in Embodiment 2 of this utility model.

[0021] Figure 4 This is a top view of the storage computing chip packaging structure based on the dam in Embodiment 3 of this utility model.

[0022] Figure 5 This is a structural diagram of the storage computing chip packaging structure based on the dam in Embodiment 4 of this utility model.

[0023] Figure 6 This is a structural diagram of the storage computing chip packaging structure based on the dam in Embodiment 5 of this utility model.

[0024] Figure label: Circuit board 1, storage packaging units 10, 10a, computing power packaging units 20, 20a, storage bare die 3, electrical connector 4, first dam 5, first package 6, computing power chip 7, flip pin 71, protective colloid 8, solder ball 9, second dam 11, second package 12, heat sink 13. Detailed Implementation

[0025] To explain in detail the technical content, structural features, objectives and effects of this utility model, the following description is provided in conjunction with the embodiments and accompanying drawings.

[0026] Example 1: refer to Figure 1 and Figure 2 This utility model discloses a storage computing chip packaging structure based on a dam, including a circuit board 1, a storage packaging unit 10, and a computing power packaging unit 20. The storage packaging unit 10 includes a storage die 3, a first dam 5, and a first package 6. The storage die 3 is mounted on the circuit board 1 and electrically connected to the circuit board 1 through an electrical connector 4. The first dam 5 surrounds the storage die 3 and the electrical connector 4. The first package 6 fills the first dam 5 and encapsulates the storage die 3 and the electrical connector 4 within it, and is packaged on the circuit board 1. The computing power packaging unit 20 includes a computing chip 7 mounted on the circuit board 1 and electrically connected to the circuit board 1. The first package 6 completely encloses the electrical connector 4 (i.e., the top surface of the first package 6 is higher than the highest point of the electrical connector 4), and its top surface height relative to the circuit carrier 1 is higher than or equal to the top surface height of the highest storage die 3 in the storage package unit 10, so that the first package 6 completely encloses the storage die 3, or only encloses the main body of the storage die 3 so that the top surface of the top storage die 3 is exposed.

[0027] Among them, the storage die 3 is a bare die, and it is a bare die formed by dicing a thinned wafer.

[0028] The first dam 5 is a UV-cured or thermosetting component. This design allows the first dam 5 to be formed by dispensing and curing, which effectively increases the tightness of the connection between the first dam 5 and the circuit board 1, and allows the width of the first dam 5 to be narrower.

[0029] Specifically, the first dam 5 is an epoxy resin ring wall or a polyimide ring wall. The first encapsulation body 6 is a ring-shaped encapsulation body formed after epoxy resin curing or a ring-shaped encapsulation body formed after polyimide curing. The materials of the first encapsulation body 6 and the first dam 5 can be the same or different. The main materials of the first encapsulation body 6 and the first dam 5 can be the same or different, preferably with the same main materials but different auxiliary materials and / or different component ratios, so that the fluidity of the adhesive forming the first dam 5 is less than that of the adhesive forming the first encapsulation body 6. For example, the auxiliary material in the first dam 5 is ABC material to reduce fluidity, while the auxiliary material in the first encapsulation body 6 is DEF material to increase fluidity and reduce viscosity.

[0030] In this embodiment, the thickness of the first dam 5 is 150-300μm, and the height of the first dam 5 is greater than or equal to the height of the first encapsulation body 6.

[0031] refer to Figure 1 The bare memory die 3 is electrically connected to the circuit carrier board 1 via an electrical connector 4. The first package 6 encloses the electrical connector 4, which is an arc-shaped bonding wire soldered between the electrode pins of the bare memory die 3 and the pads of the circuit carrier board 1. The arc-shaped bonding wire enclosed in the first package 6 can effectively disperse stress and suppress signal crosstalk. The height of the first package 6 is greater than the height of the arc-shaped bonding wire, thus ensuring that the arc-shaped bonding wire is completely enclosed within the first package 6.

[0032] The distance between the storage die 3 and the computing chip 7 is 3-4 mm. In this embodiment, the distance between the storage die 3 and the computing chip 7 is approximately 3.5 mm.

[0033] Continue to refer to Figure 1 The computing chip 7 is flip-chip soldered onto the circuit carrier board 1, and a protective colloid 8 covering the flip-chip pins 71 of the computing chip 7 is filled between the lower side of the computing chip 7 and the circuit carrier board 1. The bottom surface of the computing chip 7 has flip-chip pins 71, and solder balls 9 are embedded on the flip-chip pins 71. The flip-chip pins 71 of the computing chip 7 are soldered to the pads of the circuit carrier board 1 through the solder balls 9. The protective colloid 8 covers the flip-chip pins 71 and the solder balls 9. The solder balls 9 are solder balls. The computing chip 7 is a bare die or a bare die package.

[0034] Preferably, a third dam can be set on the circuit board 1 to surround the flip pins 7 of the computing chip 7. The third dam is filled with protective adhesive and cured to form a protective colloid 8. The third dam can prevent the adhesive from overflowing when the protective colloid 8 is formed, and also allows the adhesive to flow more freely when the protective colloid 8 is formed, effectively reducing air bubbles in the protective colloid 8.

[0035] In this embodiment, multiple bare memory dies 3 are stacked sequentially and staggered on the circuit carrier board 1 to form a chip stack structure. In this embodiment, one chip stack structure has two bare memory dies 3 stacked together, and adjacent bare memory dies 3 are bonded together with adhesive. Of course, the bare memory dies 3 in this chip stack structure can also be stacked in 3, 4, or even 8 layers. However, unlike this, there can also be only one storage packaging unit 3 disposed on the circuit carrier board 1.

[0036] Example 2: refer to Figure 3Unlike Embodiment 1, in Embodiment 2, there are multiple bare storage dies 3 stacked together to form multiple chip stack structures. Each chip stack structure participates in forming a storage packaging unit 10. Each storage packaging unit 10 is located adjacent to the computing power packaging unit 20 and on different sides of the computing power packaging unit 20. In this embodiment, there are two chip stack structures. Of course, there can also be four chip stack structures, with the four storage packaging units 10 respectively arranged around the computing power packaging unit 20.

[0037] Example 3: refer to Figure 4 Unlike Embodiments 1 and 2, in this embodiment, there are multiple storage packaging units 3, but they are not stacked into a chip stack structure. Each of the multiple storage packaging units 3 participates in forming multiple storage packaging units 10, and the multiple storage packaging units 10 are respectively disposed around the computing power packaging unit 20. In this embodiment, there are 4 storage packaging units 3, and the storage packaging units 10a containing the 4 storage packaging units 3 are disposed around the computing power packaging unit 20. Of course, there can also be 2, 3, or other numbers of storage packaging units 10a.

[0038] In this embodiment, each storage packaging unit 3 has a storage die 3, which can be fixed on the circuit board 1 and electrically connected to the circuit board 1 via an arc-shaped bonding wire as an electrical connector 4. Alternatively, the storage die 3 can be flip-chip soldered onto the circuit board 1 and electrically connected directly to the pads on the circuit board 1 via flip-chip pins on the storage die 3. In this case, the solder between the flip-chip pins and the pads serves as the electrical connector 4.

[0039] Example 4: refer to Figure 5 Unlike embodiments 1 to 3, the computing power packaging unit 20a further includes a second enclosure 11 surrounding the computing power chip 7, and a second package 12 filling the second enclosure 11 and encapsulating the computing power chip 7 on the circuit carrier board 1, thereby increasing the connection stability between the computing power packaging unit 20 and the circuit carrier board 1. The second package 12 completely encapsulates the computing power chip 7, or the main body encapsulating the computing power chip 7 only exposes the top of the computing power chip 7.

[0040] The second enclosure 11 is a UV-cured or thermosetting component. This design allows the second enclosure 11 to be formed by dispensing and curing, which effectively increases the tightness of the connection between the second enclosure 11 and the circuit board 1, and allows the width of the second enclosure 11 to be narrower.

[0041] Specifically, the second dam 11 is an epoxy resin ring wall or a polyimide ring wall. The second encapsulation body 12 is an epoxy resin encapsulation body or a polyimide encapsulation body. The main materials of the second encapsulation body 12 and the second dam 11 can be the same or different, preferably with the same main materials but different component ratios, so that the fluidity of the adhesive forming the second dam 11 is less than that of the adhesive forming the second encapsulation body 12. For example, the auxiliary material (functional filler) in the second dam 11 is ABC material to reduce fluidity, while the auxiliary material (functional filler) in the second encapsulation body 12 is DEF material to improve fluidity and reduce viscosity.

[0042] In this embodiment, the thickness of the second dam 11 is 150-300μm, and the height of the second dam 11 is greater than or equal to the height of the second encapsulation body 12.

[0043] Example 5: refer to Figure 6 Based on the above embodiments, in embodiment 5, a heat dissipation cover 13 is also fixed on the circuit board 1, which houses the storage packaging unit 10 and the computing power packaging unit 20 (20a). The heat dissipation cover 13 is spaced outside the storage packaging unit 10 and the computing power packaging unit 20 (20a). The heat dissipation cover 13 is installed on the edge of the circuit board 1.

[0044] The heat sink 13 can be a metal part with good heat dissipation performance, which can dissipate heat and shield the storage packaging unit 10 and the computing power packaging unit 20 (20a).

[0045] Compared with the prior art, in this invention, the bare memory die 3 does not need to be pre-packaged and is directly mounted on the circuit board 1 in the form of a bare die, effectively avoiding the volume waste caused by redundant structures such as lead frames and plastic seals in traditional packages. Furthermore, in this invention, the bare memory die 3 is mounted on the circuit board 1, and after being surrounded by the first enclosure 5, the first package 6 encapsulating the bare memory die 3 is filled and cured in the first enclosure 5. This increases the electrical connection stability between the bare memory die 3 and the circuit board 1, while preventing glue overflow during encapsulation from contaminating the circuit board 1. This restricts the flow range of the first package 6 during glue dispensing to the first enclosure 5, eliminating the need to reserve an excessively large safety distance to prevent glue overflow. This allows the bare memory die 3 and the computing chip 7 to be arranged at a closer distance, thereby compressing the physical distance between the bare memory die 3 and the computing chip 7, significantly reducing the interconnection distance between chips and the overall package size.

[0046] The above-disclosed embodiments are merely preferred embodiments of the present utility model and should not be construed as limiting the scope of the present utility model. Therefore, any equivalent variations made in accordance with the scope of the present utility model shall still fall within the scope of the present utility model.

Claims

1. A storage computing chip packaging structure based on a dam, characterized in that, include: Circuit board; A storage packaging unit, the storage packaging unit comprising a storage die, a first dam, and a first package body; The bare memory chip is mounted on the circuit board and electrically connected to the circuit board via an electrical connector; the first dam spacing surrounds the bare memory chip and its electrical connector; the first package is filled in the first dam and encapsulates the bare memory chip and electrical connector inside and on the circuit board, the first package fully encapsulates the electrical connector, and its top surface height relative to the circuit board is higher than or equal to the top surface height of the tallest bare memory chip in the storage package unit; A computing power packaging unit, the computing power packaging unit including a computing power chip, the computing power chip being mounted on the circuit board and electrically connected to the circuit board.

2. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The circuit board is also equipped with a heat sink cover, which covers the storage packaging unit and the computing power packaging unit. The heat sink cover is positioned at a distance from the storage packaging unit and the computing power packaging unit.

3. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The first dam is an epoxy resin ring wall or a polyimide ring wall.

4. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The thickness of the first dam is 150-300 μm.

5. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The electrical connector is an arc-shaped bonding wire, which is soldered between the electrode pins of the storage bare core and the circuit board pads.

6. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The distance between the storage die and the computing chip is 3-4 mm.

7. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The computing chip is flip-chip soldered onto the circuit board, and the space between the underside of the computing chip and the circuit board is filled with a protective colloid that wraps the flip-chip pins of the computing chip.

8. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The computing power packaging unit further includes a second enclosure surrounding the computing power chip, and a second package that fills the second enclosure, encapsulates the computing power chip, and is packaged on the circuit board.

9. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The memory bare dies are stacked in a staggered manner on the circuit carrier to form a chip stack structure.

10. The dam-based storage computing chip packaging structure as described in claim 1, characterized in that: The storage encapsulation unit is multiple and located adjacent to the computing power encapsulation unit.

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