Chip package structure

Abstract

The utility model belongs to the technical field of semiconductor packaging, disclose a kind of chip packaging structure, including pedestal, first chip, solder resist and second chip, first chip is set to pedestal, first chip has multiple first pads;Solder resist is set to first chip, solder resist sets multiple window opening structures, multiple window opening structures and multiple first pads are set one by one correspondence;Second chip has multiple second pads, multiple second pads and multiple first pads one by one correspondence, second chip is attached by second pad and first pad, and the material of second pad is tin.The utility model sets the material of second pad as tin, can avoid the rupture of second pad due to ultrasonic hot-pressing, and need not use ball mounter, effectively reduce the processing cost of second pad;By setting solder resist, can effectively avoid the height of second pad caused by tin diffusion during the welding process of first pad and second pad is too low to cause false welding or poor welding.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and in particular to a chip packaging structure. Background Technology

[0002] As a critical frequency control component in electronic devices, the assembly quality of the chip and crystal substrate in a temperature-compensated oscillator directly affects the frequency stability, reliability, and lifespan of the product. Currently, the industry commonly uses flip-chip bonding combined with ultrasonic welding to achieve electrical connection and mechanical fixation between the chip and the crystal substrate. The specific implementation process of this process is as follows: First, gold balls are welded onto the surface of the chip's pads using ultrasonic thermopressing technology through a ball-mounting machine; this process is called ball mounting. After ball mounting is completed, the flip-chip bonding machine is used to weld the ball-mounted chip to the corresponding pads of the crystal substrate using ultrasonic thermopressing, ultimately achieving the assembly and fixation of the chip and the substrate.

[0003] However, the existing assembly process described above has significant technical defects and limitations in practical applications, specifically in the following two aspects: First, the processing cost remains high. The core equipment required for this process is a ball-mounting machine and a flip-chip machine, which are expensive to purchase, and subsequent maintenance, parts replacement, and other costs are also high. At the same time, the equipment has a high operating threshold, requiring professional technicians for debugging and maintenance, further increasing labor costs. Ultimately, this leads to a significant increase in the overall processing cost of the temperature-compensated oscillator product, weakening its market competitiveness. Second, there are potential risks to product reliability. The existing process requires two ultrasonic hot-pressing operations (the ball-mounting stage and the chip soldering stage). The mechanical vibration and localized high temperatures generated during ultrasonic hot-pressing can repeatedly impact the chip pads.

[0004] Therefore, there is an urgent need for a chip packaging structure to solve the above-mentioned technical problems. Utility Model Content

[0005] The purpose of this invention is to provide a chip packaging structure that addresses the problems of high cost and easy breakage of chip pads in existing chip packaging technologies. This chip packaging structure can avoid pad breakage caused by ultrasonic hot pressing and has lower processing costs.

[0006] To achieve this objective, the present invention adopts the following technical solution:

[0007] Chip packaging structure, including:

[0008] Base;

[0009] A first chip is disposed on the base, and the first chip has a plurality of first pads;

[0010] A solder mask layer is disposed on the first chip. The solder mask layer has multiple window structures, and the multiple window structures are configured in a one-to-one correspondence with the multiple first pads.

[0011] The second chip has multiple second pads, each corresponding to one of the multiple first pads. The second chip is mounted to the first pads via the second pads, and the material of the second pads is tin.

[0012] In some possible implementations, the window structure is configured as a through hole with a diameter of d1, and the second pad has a first shape, which is a columnar structure with a diameter of d2, where d1 = (0.8-1.2)d2.

[0013] In some possible implementations, d2 ranges from 60 μm to 120 μm.

[0014] In some possible implementations, the second pad has a first shape and a second shape, the first shape being a columnar structure and the second shape being a spherical structure, the diameter of the columnar structure being d2 and the diameter of the spherical structure being d4, where d4 = (0.7-0.9)d2.

[0015] In some possible implementations, the window structure is configured as an elliptical hole, a polygonal hole, or an irregularly shaped hole.

[0016] In some possible implementations, the thickness of the solder resist layer is d3, and d3 ranges from 0.1 μm to 0.3 μm.

[0017] In some possible implementations, the size of the solder mask layer is matched to the size of the first chip, such that the solder mask layer covers the surface of the first chip.

[0018] In some possible implementations, the solder resist layer is made of epoxy resin.

[0019] In some possible implementations, the diameter of the soldering surface of the first pad is d5, and the second pad has a first shape, which is a columnar structure with a diameter of d2, where d5 = (0.7-0.9)d2.

[0020] In some possible implementations, a plurality of third pads are provided on the base, and the plurality of third pads surround the periphery of the first chip.

[0021] The beneficial effects of this utility model are:

[0022] The chip packaging structure provided by this utility model uses tin as the material for the second pad. Typically, the tin-material second pad is soldered to the second chip using reflow soldering. Compared with the existing method of using ultrasonic hot pressing to solder gold balls, this method can avoid the second pad cracking caused by ultrasonic hot pressing and eliminates the need for a ball-mounting machine, effectively reducing the processing cost of the second pad. By setting a solder resist layer with multiple window structures, each window structure corresponding to a first pad, the method can effectively avoid poor soldering or soldering defects caused by the second pad being too low in height due to tin diffusion during the soldering process between the first and second pads. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the second chip provided in this embodiment of the present invention;

[0024] Figure 2 This is a schematic diagram of the assembly structure of the base and the first chip provided in an embodiment of the present utility model;

[0025] Figure 3 This is a top view of the chip packaging structure provided in this embodiment of the utility model;

[0026] Figure 4 This is an assembly perspective view of the base and solder resist layer provided in an embodiment of this utility model.

[0027] In the picture:

[0028] 100, Base; 110, Third pad; 200, First chip; 210, First pad; 300, Solder mask; 400, Second chip; 410, Second pad. Detailed Implementation

[0029] The embodiments of this utility model are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar parts or parts having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this utility model, and should not be construed as limiting this utility model.

[0030] In the description of this utility model, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "fixed" should be interpreted broadly. For example, they can refer to a fixed connection or a detachable connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection through an intermediate medium; or the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.

[0031] In the description of this utility model, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0032] The technical solution of this utility model will be further described below with reference to the accompanying drawings and specific embodiments.

[0033] like Figures 1 to 4 As shown, this utility model provides a chip packaging structure, including a base 100, a first chip 200, a solder resist layer 300, and a second chip 400. The first chip 200 is disposed on the base 100 and has a plurality of first pads 210; the solder resist layer 300 is disposed on the first chip 200 and has a plurality of window structures, each corresponding to one of the plurality of first pads 210; the second chip 400 has a plurality of second pads 410, each corresponding to one of the plurality of first pads 210, and the second chip 400 is mounted to the first pads 210 via the second pads 410, the material of the second pads 410 being tin. It is understandable that the second chip 400 can also be other base or substrate structures, that is, multiple second pads 410 are disposed on other base or substrate structures, and other base or substrate structures are mounted to the first pads 210 on the first chip 200 through the second pads 410, thereby realizing the packaging of other base or substrate structures and chips.

[0034] In the chip packaging structure provided in this embodiment, the second pad 410 is made of tin. Typically, the tin-made second pad 410 is soldered to the second chip 400 using reflow soldering. Compared with the existing method of using ultrasonic hot pressing to solder gold balls, this method can avoid the second pad 410 from cracking due to ultrasonic hot pressing and eliminates the need for a ball-mounting machine, effectively reducing the processing cost of the second pad 410. By setting a solder resist layer 300 with multiple window structures, each window structure corresponds one-to-one with a number of first pads 210, it can effectively avoid the problem of poor soldering or soldering defects caused by the second pad 410 being too low in height due to tin diffusion during the soldering process of the first pad 210 and the second pad 410.

[0035] Optionally, the window structure is set as a through hole with a diameter of d1. The second pad 410 has a first shape, which is a columnar structure with a diameter of d2, where d1 = (0.8-1.2)d2. If the diameter of d1 relative to d2 is too large, the diffusion of solder during the soldering process will cause the height of the second pad 410 to be too low, resulting in poor soldering or cold solder joints between the second pad 410 and the first pad 210. If the diameter of d1 relative to d2 is too small, the solder will easily overfill the gap during the soldering process, forming irregular solder accumulation. Excessive solder may overflow from the through hole, creating a short circuit risk with other pads or circuits around it, leading to problems such as abnormal frequency and functional failure of the temperature-compensated oscillator.

[0036] In this embodiment, d2 ranges from 60μm to 120μm. Exemplarily, d2 can be any value among 60μm, 70μm, 80μm, 90μm, 100μm, 110μm, 120μm, or 60μm-120μm.

[0037] Optionally, the second pad 410 also has a second shape, which is a spherical structure with a diameter of d4, where d4 = (0.7-0.9)d2. If the diameter of d4 relative to d2 is too large, the fit between the spherical second pad 410 and the window structure will be poor, reducing the soldering accuracy. In addition, when the second pad 410 is melted from the first shape to the second shape, more energy is consumed, increasing the processing cost. If the diameter of d4 relative to d2 is too small, it may result in a large gap between the spherical second pad 410 and the window structure. During the soldering process, the diffusion of solder may cause the height of the second pad 410 to be too low, resulting in poor soldering or cold solder joints between the second pad 410 and the first pad 210, reducing the production yield.

[0038] Optionally, the window structure can also be set as an elliptical hole, a polygonal hole, or an irregularly shaped hole. In specific implementation, the size and specific shape of the window structure can be set according to the size and shape of the second pad 410. It is only necessary to ensure that the diffusion of solder during the soldering process will not cause cold solder joints or poor soldering between the second pad 410 and the first pad 210, and that there will be no overfilling of solder.

[0039] In this embodiment, the thickness of the solder resist layer 300 is d3, which ranges from 0.1μm to 0.3μm. If the thickness of the solder resist layer 300 is too large, on the one hand, because the thermal conductivity of the solder resist layer 300 is much lower than that of the first chip 200 and the second chip 400, an excessively thick solder resist layer 300 will hinder the dissipation of soldering heat, causing the operating temperature of the first chip 200 and the second chip 400 to rise, accelerating aging and shortening their service life; on the other hand, the difference in the coefficient of thermal expansion between the solder resist layer 300 and the first chip 200 and the second chip 400 is large, and an excessively thick layer will increase the thermal stress generated during temperature cycling, easily causing the solder resist layer 300 to crack and fall off; in addition, an excessively thick solder resist layer 300 will increase the processing difficulty of the window structure, resulting in a decrease in the dimensional accuracy of the window structure. If the thickness of the solder resist layer 300 is too small, it cannot effectively prevent solder overflow, which can easily cause short circuits in adjacent first pads 210, increasing the amount of rework after soldering, and affecting the appearance consistency and reliability of the product. For example, d3 can be any value among 0.1μm, 0.12μm, 0.14μm, 0.16μm, 0.2μm, 0.25μm, 0.3μm or 0.1μm-0.3μm.

[0040] Optionally, the size of the solder resist layer 300 matches the size of the first chip 200, so that the solder resist layer 300 covers the surface of the first chip 200. By setting the solder resist layer 300 to cover the surface of the first chip 200, the solder resist layer 300 can isolate friction and collision during assembly and transportation, avoid wear on the surface lines and first pads 210 of the first chip 200, and block the adhesion of dust and impurities, reducing the corrosion of the first chip 200 by contaminants; secondly, it can effectively isolate air and moisture, prevent oxidation and corrosion of the metal layer of the first chip 200, delay chip aging, and extend service life; at the same time, it can prevent the exposed lines on the surface of the first chip 200 from accidentally contacting surrounding components, eliminate the risk of leakage and short circuit, and ensure the stability of the chip circuit function; furthermore, it can prevent solder from overflowing into the non-pad areas of the first chip 200 during the soldering process, prevent the functional areas of the first chip 200 from being contaminated or damaged, and at the same time ensure the soldering accuracy of the second pad 410 and the first pad 210, reducing the risk of cold solder joints and short circuits.

[0041] Preferably, the solder mask layer 300 is made of epoxy resin. Epoxy resin has strong high temperature resistance and can withstand the instantaneous high temperature during the soldering process without melting or deforming, thus avoiding contamination of the solder pads and affecting the soldering quality. Epoxy resin also has a moderate thermal conductivity, with a small difference in thermal expansion coefficient compared to the first chip 200 and the second chip 400, which can alleviate the thermal stress generated by temperature cycling and reduce the risk of cracking and peeling of the solder mask layer 300.

[0042] In this embodiment, a plurality of third pads 110 are provided on the base 100, and the plurality of third pads 110 surround the periphery of the first chip 200. The third pads 110 can be used to connect to external components, or can also be used to connect to the first chip 200 or the second chip 400; the plurality of third pads 110 surrounding the periphery of the first chip 200 form multi-point welding with the corresponding pads of the first chip 200 or the second chip 400, increasing the connection contact area, reducing the risk of single solder joint failure, and ensuring continuous and stable electrical connection; the periphery distribution can match the circumferential signal pin layout of the first chip 200 or the second chip 400, shortening the signal transmission path, reducing delay and interference, and ensuring the frequency accuracy and signal integrity of the temperature-compensated oscillator. Figure 4 As shown, in this embodiment, a groove for accommodating the first chip 200 is provided on the base 100, and a plurality of third pads 110 are disposed on the surface of the groove and surround the periphery of the groove. The groove can improve the mounting stability of the first chip 200.

[0043] Optionally, the diameter of the soldering surface of the first pad 210 is d5, and when the second pad 410 has a columnar structure, the diameter of the columnar structure is d2, where d5 = (0.7-0.9)d2. If the diameter of d5 relative to d2 is too large, more energy will be consumed when the second pad 410 is melted from the first form to the second form, increasing processing costs. If the diameter of d5 relative to d2 is too small, after the second pad 410 is melted from the first form to the second form, the diffusion of solder during the soldering process will cause the height of the second pad 410 to be too low, resulting in poor soldering or cold solder joints between the second pad 410 and the first pad 210, reducing production yield.

[0044] Obviously, the above embodiments of this utility model are merely examples for clearly illustrating the present utility model, and are not intended to limit the implementation of the present utility model. Those skilled in the art can make other variations or modifications based on the above description. It is neither necessary nor possible to exhaustively list all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this utility model should be included within the protection scope of the claims of this utility model.

Claims

1. A chip packaging structure, characterized in that, include: Base (100); A first chip (200) is disposed on the base (100), and the first chip (200) has a plurality of first pads (210); A solder mask layer (300) is disposed on the first chip (200). The solder mask layer (300) is provided with multiple window structures, and the multiple window structures are provided in a one-to-one correspondence with the multiple first pads (210). The second chip (400) has multiple second pads (410), each of which corresponds to one of the multiple first pads (210). The second chip (400) is mounted to the first pads (210) via the second pads (410). The material of the second pads (410) is tin.

2. The chip packaging structure according to claim 1, characterized in that, The opening structure is configured as a through hole with a diameter of d1. The second pad (410) has a first shape, which is a columnar structure with a diameter of d2, where d1 = (0.8-1.2)d2.

3. The chip packaging structure according to claim 2, characterized in that, The range of d2 is 60μm-120μm.

4. The chip packaging structure according to claim 1, characterized in that, The second pad (410) has a first shape and a second shape. The first shape is a columnar structure and the second shape is a spherical structure. The diameter of the columnar structure is d2 and the diameter of the spherical structure is d4, where d4 = (0.7-0.9)d2.

5. The chip packaging structure according to claim 1, characterized in that, The window structure is configured as an elliptical hole, a polygonal hole, or an irregularly shaped hole.

6. The chip packaging structure according to claim 1, characterized in that, The thickness of the solder resist layer (300) is d3, and the range of d3 is 0.1μm-0.3μm.

7. The chip packaging structure according to claim 1, characterized in that, The size of the solder resist layer (300) matches the size of the first chip (200), such that the solder resist layer (300) covers the surface of the first chip (200).

8. The chip packaging structure according to claim 1, characterized in that, The solder resist layer (300) is made of epoxy resin.

9. The chip packaging structure according to claim 1, characterized in that, The diameter of the soldering surface of the first pad (210) is d5, and the second pad (410) has a first shape, which is a columnar structure with a diameter of d2, d5 = (0.7-0.9)d2.

10. The chip packaging structure according to claim 1, characterized in that, The base (100) is provided with a plurality of third pads (110), which surround the periphery of the first chip (200).

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