Integrated multi-mode intermediate frequency digitizing processing module for secondary radar interrogation response
Patent Information
- Application Number
- CN202522209762.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-20
- Publication Date
- 2026-10-20
- Estimated Expiration
- 2035-10-20
AI Technical Summary
[0004]现有二次雷达中频数字化处理一般是分别在询问机和应答机中，物理上分离，至少需要2个处理器；一般仅针对常规模式航管二次雷达A模式(MA)、C模式(MC)和S模式(MS)进行处理，只涉及ASK和DPSK解调
本实用新型的二次雷达询问应答一体化多模式中频数字化处理模块采用一体化设计，用1个FPGA处理器完成二次雷达询问和应答接收信号的中频数字化处理，实现一体化、小型化；不仅针对常规模式（MA、MC、MS）解调输出PSV、幅度、相位、DPSK码元等数据，也能针对特殊模式（M5等）解调MSK输出相关峰、P4同步触发、Walsh码等数据，实现多模式的中频数字化处理。
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Figure CN224873714U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of secondary radar technology, and in particular to a multi-mode intermediate frequency digital processing module integrating secondary radar interrogation and response. Background Technology
[0002] As a core module of modern communication and radar systems, the performance of the receiver directly affects the overall system performance. 。 With the development of microelectronics technology, digital signal processing technology is increasingly being used in radar systems. Furthermore, digitization is continuously moving from the end of the system forward. Digital processing offers many advantages that analog processing cannot match, especially when combined with computer technology, and has become the mainstream of modern radar development. The receiver converts received analog signals into digital signals, gradually moving from video signals and analog baseband signals to intermediate frequency (IF) signals. Most receiving functions are increasingly being performed using IF digital processing technology.
[0003] The key points of existing intermediate frequency digital processing for secondary radar are as follows: the intermediate frequency analog signal is converted into a digital signal through analog-to-digital sampling; the signal is converted into a baseband signal through digital down-conversion; and the digital or baseband signal is digitally demodulated and output according to the working mode.
[0004] Existing secondary radar intermediate frequency digital processing is generally physically separated in the interrogator and transponder, requiring at least two processors; it generally only processes the A mode (MA), C mode (MC), and S mode (MS) of conventional air traffic control secondary radar, involving only ASK and DPSK demodulation. Utility Model Content
[0005] In view of this, in order to solve the technical problems existing in the prior art, the present invention provides a secondary radar interrogation and response integrated multi-mode intermediate frequency digital processing module.
[0006] This utility model provides a multi-mode intermediate frequency digital processing module for a secondary radar interrogation and response system, which includes an FPGA processor and an analog-to-digital converter (ADC); the FPGA processor is connected to the ADC. The analog-to-digital converter (ADC) is used to sample the differential signal output by the conditioning circuit to obtain digital interrogation and response signals and send them to the FPGA processor. The FPGA processor is used to digitally down-convert the digital signal from the analog-to-digital converter (ADC) to obtain a baseband signal. It calculates the envelope of the baseband signal using a coordinate rotation digital calculation method, binarizes the obtained envelope using a preset threshold level, and outputs high and low level pulse signals to complete the amplitude shift keying (ASK) demodulation process. Furthermore, it obtains the phase and amplitude information of the baseband signal using a coordinate rotation digital calculation method and logarithmic compression. It performs delay multiplication and filtering on the digital signal output from the ADC, determines the amplitude information of the filtered signal, compares the amplitude information with a preset threshold level, and outputs differential phase shift keying (DPSK) symbol information. The processor also processes the digital signal output from the ADC... Digital down-conversion is performed to obtain the baseband signal. The phase of the baseband signal is obtained through a coordinate rotation digital calculation method. Phase difference processing is performed on the phase at different times to obtain the frequency symbol information of the minimum frequency shift keying (MSK) signal. The frequency symbol information of the MSK signal is subjected to sliding correlation processing using the synchronization head of the correlation mode to obtain the value of the correlation peak. The correlation mode includes M5 mode. The validity of the secondary radar M5 mode interrogation or response is determined based on the positional relationship of the correlation peak at different times. If valid, the data part of the MSK modulated pulse signal corresponding to the M5 mode is de-spread and MSK demodulated. The de-spread and MSK data is output, which includes the correlation peak signal, the P4 synchronization trigger signal, and the Walsh code.
[0007] Furthermore, it also includes interface units; The interface unit is used to send out the signals output by the FPGA.
[0008] Furthermore, the interface unit includes a GPIO interface; The data after ASK, DPSK, and MSK demultiplexing and expansion is output through the GPIO interface of the interface unit.
[0009] Furthermore, it also includes conditioning circuitry; The conditioning circuit is used to receive the intermediate frequency secondary radar interrogation signal and response signal, and to perform AC coupling, differential conversion and impedance matching on the intermediate frequency signal, and send it to the differential input port of the analog-to-digital converter (ADC).
[0010] Furthermore, it also includes an analog-to-digital converter (ADC); The analog-to-digital converter (ADC) is used to receive the differential signal output by the conditioning circuit.
[0011] Furthermore, it also includes multiple parallel branches, each branch including the conditioning circuit and the analog-to-digital converter (ADC) connected in series; each ADC is connected to the FPGA processor.
[0012] Furthermore, it also includes a frequency synthesis unit; The frequency synthesizer unit is used to generate the clock signals required for the operation of the analog-to-digital converter (ADC) and the FPGA processor.
[0013] Furthermore, it also includes a power management unit; The power management unit is used to convert the input voltage to provide the required power to each unit; each unit includes an FPGA processor, a frequency synthesizer unit, an analog-to-digital converter (ADC) unit, and an interface unit.
[0014] Furthermore, the FPGA processor is also used to control related components; the related components include a frequency synthesizer unit and input / output interfaces of each unit; each unit includes an FPGA processor, a frequency synthesizer unit, an analog-to-digital converter (ADC), and an interface unit.
[0015] Furthermore, the frequency synthesizer unit employs a clock buffer and a phase-locked loop (PLL) or a direct digital frequency synthesizer (DDS).
[0016] Due to the adoption of the above technical solution, this utility model has the following advantages: This utility model's integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response adopts an integrated design, using a single FPGA processor to complete the intermediate frequency digital processing of the received signals from the secondary radar interrogation and response, achieving integration and miniaturization. It can not only demodulate and output data such as PSV, amplitude, phase, and DPSK symbols for conventional modes (MA, MC, MS), but also demodulate MSK and output data such as correlation peaks, P4 synchronization triggers, and Walsh codes for special modes (M5, etc.), realizing multi-mode intermediate frequency digital processing. Attached Figure Description
[0017] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings.
[0018] Figure 1 This is a block diagram of a multi-mode intermediate frequency digital processing module for secondary radar interrogation and response, provided as an embodiment of the present invention. Detailed Implementation
[0019] It should be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0020] The features and performance of this utility model will be further described in detail below with reference to the embodiments.
[0021] like Figure 1 As shown, this utility model provides an embodiment of a multi-mode intermediate frequency digital processing module for integrated secondary radar interrogation and response, which includes an FPGA processor and an analog-to-digital converter (ADC); the FPGA processor is connected to the ADC. The analog-to-digital converter (ADC) is used to sample the differential signal output by the conditioning circuit, obtain the digital interrogation and response signals, and send them to the FPGA processor. The FPGA processor performs digital down-conversion on the digital signal from the analog-to-digital converter (ADC) to obtain a baseband signal. It calculates the envelope of the baseband signal using a coordinate rotation digital calculation method (Cordic algorithm), binarizes the envelope using a preset threshold level, and outputs high and low level pulse signals to complete the amplitude shift keying (ASK) demodulation. Furthermore, it obtains the phase and amplitude information of the baseband signal through coordinate rotation digital calculation and logarithmic compression. It performs delay multiplication and filtering on the digital signal output from the ADC, determines the amplitude information of the filtered signal, compares the amplitude information with a preset threshold level, and outputs differential phase shift keying (DPSK) symbol information. It also processes the digital signal output from the ADC... The digital down-conversion signal is used to obtain the baseband signal. The phase of the baseband signal is obtained through a coordinate rotation digital calculation method. The phase difference at different times is processed to obtain the frequency symbol information of the minimum frequency shift keying (MSK) signal. The frequency symbol information of the MSK signal is subjected to sliding correlation processing using the synchronization head of the correlation mode to obtain the value of the correlation peak. The correlation mode includes M5 mode. The validity of the secondary radar M5 mode interrogation or response is determined based on the positional relationship of the correlation peak at different times. If valid, the data part of the MSK modulated pulse signal corresponding to the M5 mode is de-spread and de-spread. The de-spread and de-spread data is output, which includes the correlation peak signal, the P4 synchronization trigger signal, and the Walsh code.
[0022] M5 mode is the core mode of the new generation IFF (Mark XIIA) system. It employs an interrogation and response mechanism, using encrypted signal exchange to achieve identification. M5 mode uses a series of MSK modulated pulse signals, including a synchronization header and subsequent data. Once the header is confirmed to be valid, the corresponding data is processed as described above. The P4 synchronization trigger signal is the synchronization trigger signal in the M5 mode signal.
[0023] Optionally, it may also include an interface unit; The interface unit is used to send out the signals output by the FPGA.
[0024] Optionally, the interface unit includes a GPIO interface; The data after ASK, DPSK, and MSK demultiplexing and expansion is output through the GPIO interface of the interface unit.
[0025] Optionally, it may also include a conditioning circuit; The conditioning circuit is used to receive the intermediate frequency secondary radar interrogation signal and response signal, and to perform AC coupling, differential conversion and impedance matching on the intermediate frequency signal before sending it to the differential input port of the analog-to-digital converter (ADC).
[0026] Optionally, it also includes an analog-to-digital converter (ADC); The analog-to-digital converter (ADC) is used to receive the differential signal output from the conditioning circuit.
[0027] Optionally, it also includes multiple parallel branches, each branch including a conditioning circuit and an analog-to-digital converter (ADC) connected in series; each ADC is connected to the FPGA processor.
[0028] Optionally, it may also include a frequency synthesis unit; The frequency synthesizer unit is used to generate the clock signals required for the operation of the analog-to-digital converter (ADC) and the FPGA processor.
[0029] Optionally, it also includes a power management unit; The power management unit converts the input voltage to provide power to the various units, including the FPGA processor, frequency synthesizer, analog-to-digital converter (ADC), and interface unit. The power management unit is not limited to a +5V power supply.
[0030] Optionally, the FPGA processor is also used to control related components; the related components include frequency synthesizer units and input / output interfaces of each unit; each unit includes an FPGA processor, a frequency synthesizer unit, an analog-to-digital converter (ADC) unit, and an interface unit.
[0031] Optionally, the frequency synthesizer unit employs a clock buffer and a phase-locked loop (PLL) or a direct digital frequency synthesizer (DDS).
[0032] This invention can not only demodulate and output PSV, amplitude, phase, DPSK symbols and other data for conventional modes (MA, MC, MS), but also demodulate MSK and output related peak signals, P4 synchronous trigger signals, Walsh codes and other data for special modes (M5 mode, etc.).
[0033] The embodiments described above merely illustrate specific implementations of this utility model, and while the descriptions are detailed, they should not be construed as limiting the scope of protection of this utility model. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these modifications and improvements all fall within the scope of protection of this utility model.
Claims
1. A multi-mode intermediate frequency digital processing module integrating secondary radar interrogation and response, characterized in that, It includes an FPGA processor and an analog-to-digital converter (ADC); the FPGA processor is connected to the ADC. The analog-to-digital converter (ADC) is used to sample the differential signal output by the conditioning circuit to obtain digital interrogation and response signals and send them to the FPGA processor. The FPGA processor is used to digitally down-convert the digital signal from the analog-to-digital converter (ADC) to obtain a baseband signal. It calculates the envelope of the baseband signal using a coordinate rotation digital calculation method, binarizes the obtained envelope using a preset threshold level, and outputs high and low level pulse signals to complete the amplitude shift keying (ASK) demodulation process. Furthermore, it obtains the phase and amplitude information of the baseband signal using a coordinate rotation digital calculation method and logarithmic compression. It performs delay multiplication and filtering on the digital signal output from the ADC, determines the amplitude information of the filtered signal, compares the amplitude information with a preset threshold level, and outputs differential phase shift keying (DPSK) symbol information. The processor also processes the digital signal output from the ADC... Digital down-conversion is performed to obtain the baseband signal. The phase of the baseband signal is obtained through a coordinate rotation digital calculation method. Phase difference processing is performed on the phase at different times to obtain the frequency symbol information of the minimum frequency shift keying (MSK) signal. The frequency symbol information of the MSK signal is subjected to sliding correlation processing using the synchronization head of the correlation mode to obtain the value of the correlation peak. The correlation mode includes M5 mode. The validity of the secondary radar M5 mode interrogation or response is determined based on the positional relationship of the correlation peak at different times. If valid, the data part of the MSK modulated pulse signal corresponding to the M5 mode is de-spread and MSK demodulated. The de-spread and MSK data is output, which includes the correlation peak signal, the P4 synchronization trigger signal, and the Walsh code.
2. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 1, characterized in that, It also includes interface units; The interface unit is used to send out the data output by the FPGA processor.
3. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 2, characterized in that, The interface unit includes a GPIO interface; The demultiplexed data from ASK, DPSK, and MSK is output through the GPIO interface of the interface unit.
4. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 1, characterized in that, It also includes conditioning circuitry; The conditioning circuit is used to receive the intermediate frequency secondary radar interrogation signal and response signal, and to perform AC coupling, differential conversion and impedance matching on the intermediate frequency signal, and send it to the differential input port of the analog-to-digital converter (ADC).
5. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 4, characterized in that, It also includes an analog-to-digital converter (ADC); The analog-to-digital converter (ADC) is used to receive the differential signal output by the conditioning circuit.
6. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 5, characterized in that, It also includes multiple parallel branches, each branch including the conditioning circuit and the analog-to-digital converter (ADC) connected in series; each ADC is connected to the FPGA processor.
7. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 1, characterized in that, It also includes a frequency synthesis unit; The frequency synthesizer unit is used to generate the clock signals required for the operation of the analog-to-digital converter (ADC) and the FPGA processor.
8. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 1, characterized in that, It also includes a power management unit; The power management unit is used to convert the input voltage to provide the required power to each unit; each unit includes an FPGA processor, a frequency synthesizer unit, an analog-to-digital converter (ADC) unit, and an interface unit.
9. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to claim 1, characterized in that, The FPGA processor is also used to control related components; the related components include a frequency synthesizer unit and input / output interfaces of each unit; each unit includes an FPGA processor, a frequency synthesizer unit, an analog-to-digital converter (ADC), and an interface unit.
10. The integrated multi-mode intermediate frequency digital processing module for secondary radar interrogation and response according to any one of claims 7-9, characterized in that, The frequency synthesizer unit employs a clock buffer and a phase-locked loop (PLL) or a direct digital frequency synthesizer (DDS).