Semiconductor package

Abstract

The present disclosure provides a semiconductor package including a photonic die having an optical coupler, an electronic die bonded on the photonic die, and an optical support bonded on the electronic die, the optical support including a plurality of lens structures, wherein light from an external optical signal source is sequentially coupled to the optical coupler through the plurality of lens structures.

Description

Technical Field

[0001] This disclosure relates to a semiconductor package. Background Technology

[0002] As data networks scale to meet ever-increasing bandwidth demands, the drawbacks of copper data channels become apparent. Signal attenuation and crosstalk caused by radiated electromagnetic energy are major obstacles for designers of such systems. These problems can be mitigated to some extent through equalization, coding, and shielding, but these techniques require considerable power, complexity, and cable bulk penalties, while offering only limited improvements in transmission distance and very limited scalability. Optical communication, unaffected by such channels, is considered the successor to copper links. However, modern optical communication systems are expensive and technologically complex. Utility Model Content

[0003] In embodiments of this disclosure, a semiconductor package includes a photonic die containing an optical coupler, an electronic die bonded to the photonic die, and an optical support member bonded to the electronic die and including multiple lens structures. Light from an external optical signal source is sequentially coupled to the optical coupler through the multiple lens structures.

[0004] In embodiments of this disclosure, a semiconductor package includes a photonic die containing an optical coupler, an electronic die bonded to the photonic die, and an optical support bonded to the electronic die. The optical support includes a first lens structure and a second lens structure configured to sequentially couple light to the optical coupler via the first lens structure and the second lens structure, wherein the size of the first lens structure is substantially larger than the size of the second lens structure.

[0005] In an embodiment of this disclosure, a method for manufacturing a semiconductor package includes: providing a photonic die, wherein the photonic die includes an optical coupler; bonding an electron die to the photonic die; providing an encapsulating material on the photonic die to form an encapsulated electron die, wherein the encapsulating material at least laterally encapsulates the electron die; forming a first lens structure and a second lens structure on an optical support; and bonding the optical support to the encapsulated electron die, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the first lens structure and the second lens structure.

[0006] To make the above-described features and advantages of this disclosure more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] The various aspects of this disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.

[0008] Figures 1 to 8 The diagram shows a cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure.

[0009] Figure 9 and Figure 10 Cross-sectional views of a semiconductor package according to different embodiments of the present disclosure are shown.

[0010] Figures 11 to 16 This diagram shows a partial cross-sectional view of an intermediate stage in the fabrication of a lens structure on a semiconductor package according to some embodiments of the present disclosure.

[0011] Figures 17 to 21 This diagram shows a partial cross-sectional view of an intermediate stage in the fabrication of a lens structure on a semiconductor package according to other embodiments of the present disclosure.

[0012] Explanation of reference numerals in the attached figures

[0013] 100, 100a, 100b: Semiconductor packaging, photonics packaging

[0014] 101, 1221: Substrate

[0015] 102a: Silicon layer

[0016] 102b: Oxide layer

[0017] 103, 108: Dielectric layer

[0018] 104: Waveguide

[0019] 106: Photonic elements

[0020] 110,110': Photon chip

[0021] 111,111': Support substrate

[0022] 112: Optical coupler, grating coupler

[0023] 112b: Optical coupler, edge coupler

[0024] 114, 1222: Interconnection structure

[0025] 115, 115', 116: Through holes

[0026] 117, 1223: Bonding pads

[0027] 118,156: Reflector

[0028] 120: Encapsulated electron tube die

[0029] 122: Electron tube chip

[0030] 124: Packaging Material

[0031] 130, 130a: Optical support components

[0032] 140: Bonding layer

[0033] 152, 154, 154', 172, 174: Lens structure

[0034] 1541: Filler material

[0035] 1541': Filler material layer

[0036] 1542: Reflective layer

[0037] 1543: Non-vertical sidewall

[0038] 1544: Convex bottom surface

[0039] 160: Polymer lens structure

[0040] 160: Patterned polymer layer

[0041] 162: Patterned Mask Layer

[0042] 170: Conductive connector

[0043] 172: Conductive pad

[0044] 173: Passivation layer

[0045] 180: Fiber optic cable, optical signal source

[0046] OP1, OP2: Openings

[0047] S1: Upper surface

[0048] S2: Lower surface Detailed Implementation

[0049] The following disclosure provides several different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these elements and arrangements are merely examples and are not intended to be limiting. For example, in the following description, the formation of a first feature over or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0050] Furthermore, for ease of description, spatially related terms such as “below,” “under,” “lower,” “above,” “upper,” etc., may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations depicted in the figures, spatially related terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. The terms “first,” “second,” “third,” “fourth,” etc., are merely general designations and are therefore interchangeable in various embodiments. For example, while an element (e.g., an opening) may be referred to as a “first” element in some embodiments, it may be referred to as a “second” element in other embodiments.

[0051] Figures 1 to 8 This diagram shows a cross-sectional view of an intermediate stage in the manufacture of a semiconductor package according to some embodiments of the present disclosure. (Refer to...) Figure 1A substrate 101 is provided according to some embodiments. In some embodiments, the substrate 101 may be a dielectric substrate, for example, formed of silicon oxide. In this embodiment, the substrate 101 may be a silicon-on-insulator (SOI) substrate. For example, the substrate 101 may include an oxide layer 102b formed on a carrier substrate 111' and a silicon layer 102a formed on the oxide layer 102b. The carrier substrate 111' may be a material such as glass, ceramic, dielectric material, semiconductor, similar material, or a combination thereof. In some embodiments, the carrier substrate 111' may be a semiconductor substrate, such as a bulk semiconductor or the like, which may be doped (e.g., doped with p-type or n-type dopant) or undoped. Integrated circuit devices may be formed on and / or therein on the carrier substrate 111'. According to some embodiments of this disclosure, the integrated circuit device may include active devices such as transistors and / or diodes (which may include photodiodes). The integrated circuit device may also include passive devices such as capacitors, resistors, or the like. According to alternative embodiments of this disclosure, no active devices are formed, but passive devices can be formed on / in the carrier substrate 111'. The carrier substrate 111' may be a wafer, such as a silicon wafer (e.g., a 12-inch silicon wafer). Other substrates may also be used, such as multilayer substrates or gradient substrates. In some embodiments, the semiconductor material of the substrate 101 may include silicon; germanium; compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide phosphide; or combinations thereof. In some embodiments, the carrier substrate 111' may have a thickness ranging from about 300 μm to about 2000 μm. The oxide layer 102b may be, for example, silicon oxide or the like. In some embodiments, the oxide layer 102b may have a thickness ranging from about 0.5 μm to about 4 μm. In some embodiments, the silicon layer 102a may have a thickness ranging from about 0.1 μm to about 1.5 μm. Other thicknesses are also possible. The substrate 101 may be referred to as having a front side or front surface (e.g., on...). Figure 1 The side facing upwards), and the back side or back surface (e.g., on the ...). Figure 1 (The side facing down). The term "about" can be used to include any numerical value that can vary without altering the fundamental function of the value. When used with a range, "about" also discloses a range defined by the absolute values ​​of its two endpoints; for example, "about 2 to about 4" also discloses a range "from 2 to 4". The term "about" can refer to plus or minus 10% of the number shown.

[0052] Reference Figure 2According to some embodiments, silicon layer 102a is patterned to form silicon regions for waveguide 104, photonic element 106, and optical coupler 112. Thus, in some cases, silicon layer 102a can be considered an "optical layer." Silicon layer 102a can be patterned using suitable photolithography and etching techniques. For example, in some embodiments, a hardmask layer (e.g., a nitride layer or other dielectric material, not present on the silicon layer) can be formed and patterned on silicon layer 102a. Figure 2 (as shown in the image). The pattern of the hard film layer can then be transferred to the silicon layer 102a using an etching process. The etching process may include, for example, dry etching and / or wet etching. The etching process may be anisotropic. For example, the silicon layer 102a may be etched to form a recess that defines the waveguide 104 (also referred to as silicon waveguide 104), with the sidewalls of the remaining unrecessed portion defining the sidewalls of the waveguide 104. In some embodiments, more than one photolithography and etching sequence may be used to pattern the silicon layer 102a.

[0053] One or more waveguides 104 can be patterned from silicon layer 102a. If multiple waveguides 104 are formed, they can be individual, separate waveguides 104 or connected to form a single continuous structure. In some embodiments, one or more waveguides 104 form a continuous loop. Other configurations or arrangements of waveguides 104, photonic elements 106, or optocouplers 112 are possible, and other types of photonic elements 106 or photonic structures can be formed. In some cases, waveguides 104, photonic elements 106, and grating couplers 112 may be collectively referred to as a "photonic layer" or a "photonic integrated circuit (PIC)".

[0054] Photonic element 106 may be integrated with waveguide 104 and may be formed together with silicon waveguide 104. Photonic element 106 may be optically coupled to waveguide 104 and may interact with optical signals within waveguide 104. Photonic element 106 may include, for example, photonic devices such as photodetectors, modulators, other photonic devices, or the like. For example, a photodetector may be optically coupled to waveguide 104 to detect optical signals within waveguide 104 and generate an electrical signal corresponding to the optical signal. As another example, a modulator may be optically coupled to waveguide 104 to receive electrical signals and generate a corresponding optical signal within waveguide 104 by modulating the optical power within waveguide 104. Thus, photonic element 106 may facilitate the input / output (I / O) of optical signals entering and exiting waveguide 104. In other embodiments, photonic element may include other active or passive elements such as laser diodes, optical signal splitters, phase shifters, interferometers, oscillators, or other types of photonic structures or devices.

[0055] In some embodiments, a photodetector can be formed by partially etching multiple regions of waveguide 104 and growing epitaxial material on the remaining silicon of the etched regions. Acceptable photolithography and etching techniques can be used to etch waveguide 104. The epitaxial material may include, for example, a semiconductor material such as germanium, which may be doped or undoped. In some embodiments, an implantation process can be performed to introduce a dopant into the silicon of the etched regions as part of forming the photodetector. The silicon of the etched regions may be doped with P-type dopant, N-type dopant, or a combination thereof. In some embodiments, a modulator can be formed by, for example, partially etching regions of waveguide 104 and then implanting an appropriate dopant within the remaining silicon of the etched regions. Acceptable photolithography and etching techniques can be used to etch waveguide 104. In some embodiments, the etched regions for the photodetector and the etched regions for the modulator can be formed using one or more of the same photolithography or etching steps. The silicon of the etched regions can be doped with P-type dopant, N-type dopant, or a combination thereof. In some embodiments, the etched regions for the photodetector and the etched regions for the modulator can be implanted using one or more of the same implantation steps.

[0056] In some embodiments, one or more optical couplers 112 may be formed together with waveguide 104. In one embodiment, the optical coupler 112 is, for example, but not limited to, a grating coupler or the like. In this embodiment, the top of the optical coupler 112 may have a grating, enabling the optical coupler 112 to function as a light receiver or a light transmitter. The optical coupler 112 for receiving light receives light from an upper light source or optical signal source (such as an optical fiber) and transmits the light to waveguide 104. The optical coupler 112 for transmitting light receives light from waveguide 104 and transmits the light to an optical fiber or the waveguide of another photonic system.

[0057] In some embodiments, the optical coupler 112 may be formed using acceptable photolithography and etching techniques. In one embodiment, the optical coupler 112 is formed after the waveguide 104 is defined. For example, a photoresist may be formed and patterned on the waveguide 104, the pattern of which corresponds to the optical coupler 112. The patterned photoresist may then be used as an etching mask to perform one or more etching processes on the waveguide 104 to form the optical coupler 112. The etching processes may include one or more dry etching processes and / or wet etching processes, which may include anisotropic processes. In some embodiments, other types of couplers (not separately labeled in the figures) may be formed, such as structures that couple optical signals between the waveguide 104 and other waveguides in the semiconductor package (such as nitride waveguides). Edge couplers (not shown in the figures) may also be formed, allowing the transmission of optical signals and / or optical power between the waveguide 104 and photonic elements horizontally mounted near the sidewalls of the semiconductor package. These and other photonic structures are considered to be within the scope of this disclosure.

[0058] Reference Figure 3 A dielectric layer 103 is formed on the optical layer to form a photonic routing structure. That is, the dielectric layer 103 is formed on the waveguide 104, photonic element 106, optical coupler 112, and oxide layer 102b. The dielectric layer 103 may be formed from one or more silicon oxide layers, silicon nitride layers, combinations thereof, or the like, and may be formed by CVD, PVD, atomic layer deposition (ALD), spin coating dielectric processes, similar processes, or combinations thereof. In some embodiments, the dielectric layer 108 may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by curing to transform it into another material, such as an oxide), similar processes, or combinations thereof. Other dielectric materials formed using any acceptable process may be used. In some embodiments, the dielectric layer 103 is then planarized using a planarization process (such as chemical mechanical polishing (CMP), grinding, or similar processes). In some cases, a thinner dielectric layer 103 may allow for more efficient optical coupling between the grating coupler 112 and a vertically mounted photonic element, or between the waveguide 104 and an upper waveguide (such as a nitride waveguide). In other embodiments, a planarization process may expose the surfaces of the waveguide 104, the photonic element 106, and / or the grating coupler 112.

[0059] Due to the difference in refractive indices between the waveguide 104 and the dielectric layer 103, the waveguide 104 exhibits high internal reflection, which confines light largely within the waveguide 104, depending on the wavelength of the light and the refractive index of the respective materials. In one embodiment, the refractive index of the waveguide 104 material is higher than that of the dielectric layer 103 material. For example, the waveguide 104 may comprise silicon, and the dielectric layer 103 may comprise silicon oxide and / or silicon nitride. Therefore, the waveguide 104 may be referred to herein as a "silicon waveguide".

[0060] Then, according to some embodiments, an interconnect structure 114 is formed on the dielectric layer 103 and the optical layer including the optocoupler 112. The interconnect structure 114 includes a plurality of dielectric layers, metal lines, and vias. The dielectric layers may be formed of a light-transmitting material (such as silicon oxide). The dielectric layers may also be formed of silicon oxynitride, silicon nitride, or the like, or of a low-k dielectric material with a k value less than about 3.0. Low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, hydrosilsesquioxane (HSQ), methylsilsesquioxane (MSQ), or the like. The metal lines and vias 116 may be formed using an damascene process and may include, for example, copper on a diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0061] In some embodiments, one or more nitride waveguides (not shown) may be formed within the interconnect structure 114. In some embodiments, the nitride waveguide (also referred to as a "silicon nitride waveguide") may be optically coupled to an upper or lower nitride waveguide. In some embodiments, one or more bottom-level nitride waveguides may be coupled to one or more lower-level silicon waveguides 104. In this way, the nitride waveguides can be used to transmit optical signals and / or optical power to or from other nitride waveguides and / or silicon waveguides 104.

[0062] In some cases, waveguides formed from silicon nitride (e.g., nitride waveguides) may have advantages over those formed from silicon (e.g., waveguide 104). For example, silicon nitride has a higher dielectric constant than silicon, so nitride waveguides may have greater internal optical confinement than silicon waveguides. This may also make the performance or leakage of nitride waveguides less sensitive to process variations, dimensional uniformity, and surface roughness (e.g., edge roughness or linewidth roughness). In some cases, reduced process sensitivity may make nitride waveguides easier or less costly to process than silicon waveguides. These characteristics may result in lower propagation losses in nitride waveguides than in silicon waveguides. In some cases, the propagation loss (dB / cm) of nitride waveguides may be between about 0.1% and about 50% of that of silicon waveguides. In some cases, nitride waveguides may also be less sensitive to ambient temperature than silicon waveguides. For example, the temperature sensitivity of nitride waveguides may be as low as about 1% of that of silicon waveguides.

[0063] In some embodiments, a plurality of bonding pads 117 are formed above and connected to the metal wire / via 116. At this time, the photonic die 110', including the optocoupler 112, is substantially formed. The bonding pads 117 may be formed of aluminum or copper, but this disclosure is not limited thereto. The bonding pads 117 are electrically connected via interconnect structure 114 to an integrated circuit device and / or a buried via 115', which may be a photoelectric conversion device and / or an electro-optical conversion device. The photoelectric conversion device and / or the electro-optical conversion device may be built into the photonic die 110' or externally attached to the photonic die 110'. The photoelectric conversion device may include a photodiode. The electro-optical conversion device may include a light-emitting diode, a lamp, or the like.

[0064] According to some embodiments of this disclosure Figure 3 The photonic die 110' shown may be part of a wafer comprising a plurality of (identical) photonic dies 110' arranged in an array, although only one photonic die 110' is described herein. In some embodiments, the photonic die 110' includes an optical coupler 112 configured to connect to an optical signal source (e.g., an optical fiber or the like) Figure 7 The optical signal source 180 shown is optically coupled. That is, the photonic chip 110' has the functions of receiving optical signals, transmitting optical signals within the photonic chip 110', transmitting optical signals out of the photonic chip 110', and connecting with an electronic chip (e.g., an electronic chip). Figure 5 The electron die 122 shown has electronic communication functions. Therefore, the photonic die 110' is also responsible for the input / output (I / O) of optical signals in the photonic package (also known as the optical engine), which may be part of a semiconductor package or other structure.

[0065] According to some embodiments of this disclosure, the photonic die 110' can be used as an interposer and includes vias penetrating the substrate (also referred to as through-substrate vias or through-silicon vias). These vias (e.g. Figure 8 The through-hole 115 shown is formed of a conductive material, which may also be a metallic material, such as tungsten, copper, titanium, or the like. The process for forming the through-hole can be as follows: Figure 3 As shown, it starts with multiple through holes 115', eventually exposing the metal as... Figure 8 It is shown to be essentially coplanar with the back side of the substrate.

[0066] Now refer to Figure 4 and Figure 5 An electronic die 122 is provided and coupled above the photonic die 110'. The electronic die 122 may be, for example, a semiconductor device, die, or chip that communicates with the photonic element 106 using electrical signals. In some embodiments, the electronic die 122 may process electrical signals received from the photonic element 106 or generate electrical signals that the photonic element 106 converts into optical signals. Figure 5The image shows one electron die 122, but in other embodiments, the semiconductor package may include two or more electron dies 122 to reduce processing costs or increase functionality. The electron die 122 includes connectors (e.g., bonding pads 1223), which may be, for example, conductive pads, conductive posts, or the like. In some embodiments, the electron die 122 may have a thickness ranging from about 10 μm to about 35 μm. Other thicknesses are also possible.

[0067] The die 122 may include an integrated circuit for interfacing with the photonic element 106, such as circuitry for controlling the operation of the photonic element 106. For example, the die 122 may include a controller, driver, transimpedance amplifier, the like, or a combination thereof. In some embodiments, the die 122 may include CPU or memory functionality. In some embodiments, the die 122 includes circuitry for processing electrical signals received from the photonic element 106, such as processing electrical signals received from the photonic element 106 including a photodetector. In some embodiments, the die 122 may control high-frequency signals of the photonic element 106 based on electrical signals (digital or analog) received from another device or die. In some embodiments, the die 122 may be an electronic integrated circuit (EIC) or the like providing serializer / deserializer (SerDes) functionality. Thus, the die 122 may serve as part of the input / output (I / O) interface between optical and electrical signals within the photonic package 100. In some cases, the photonic package 100 described herein can be considered a system-on-chip (SoC) or system-on-integrated-circuit (SoIC) device.

[0068] In some embodiments, the electron die 122 is bonded to the interconnect structure 114 of the photonic die 110' using dielectric-to-dielectric bonding and / or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, or the like). In these embodiments, dielectric-to-dielectric bonding may occur between the top dielectric layer of the photonic die 110' and the bonding layer (not shown separately) of the electron die 122. During the bonding process, metal-to-metal bonding may also occur between the bonding pads 1223 of the electron die 122 and the top bonding pads 117 of the photonic die 110'.

[0069] According to some embodiments of this disclosure, from a top view, the electron die 122 does not overlap with the optocoupler 112, therefore the optocoupler 112 can be connected to the optical signal source 180 (… Figure 7 Optical coupling, without being interfered with by electron tube chip 122.

[0070] In some embodiments, the electron die 122 may initially be part of a wafer comprising a plurality of electron dies 122 arranged in an array, which is then diced into a plurality of (separate) electron dies 122. The electron die 122 may include a substrate 1221, and interconnect structures 1222 may include a plurality of dielectric layers, metal lines, and vias. The dielectric layers may also be formed of silicon oxide, silicon oxynitride, silicon nitride, or the like, or of a low-k dielectric material having a k value below about 3.0. Low-k dielectric materials may include Black Diamond (a registered trademark of Applied Materials), carbon-containing low-k dielectric materials, silsesquioxane hydrogen oxyhydroxide (HSQ), methylsilsesquioxane hydrogen oxyhydroxide (MSQ), or the like. The metal lines and vias may be formed using an damascene process and may include, for example, copper on a diffusion barrier layer. The diffusion barrier layer may be formed of titanium, titanium nitride, tantalum, tantalum nitride, or the like. Bonding pads 1223 are formed over and connected to the metal lines / vias. The bonding pad 1223 may be formed of aluminum or copper, but this disclosure is not limited thereto.

[0071] In this embodiment, the photonic chip 110' is in wafer form, and the diced electron chip 122 can be selected and placed on the photonic chip 110'. In other words, in this embodiment, Figure 5 The bonding process shown is a die-to-wafer bonding process. It is worth noting that more or fewer dies can be provided on the photonic die 110'. In this embodiment, the electron die 122 is bonded to the photonic die 110' via a die-to-wafer bonding process. For example, direct metal-to-metal thermocompression bonding, or any type of hybrid bonding technique, can be applied. After the bonding process, the bonding pads 1223 of the electron die 122 are bonded to the bonding pads 117 of the photonic die 110'.

[0072] Reference Figure 6 Encapsulation material 124 is provided on photonic die 110'. Encapsulation material 124 encapsulates electron die 122 at least laterally. In some embodiments, encapsulation material 124 may be formed of a light-transmitting material, such as silicon oxide or any other suitable oxide material. In some embodiments, the upper surface of encapsulation material 124 may initially be higher than the upper surface of electron die 122. In other words, encapsulation material 124 may initially cover the upper surface of electron die 122.

[0073] Then, a thinning process can be performed on the encapsulation material 124 to expose the upper surface of the electron die 122 for further processing. The thinning process can be, for example, mechanical polishing or CMP, in which chemical etchants and abrasives are used to react and polish away the encapsulation material 124 until the electron die 122 is exposed. The resulting structure is as follows: Figure 4As shown. After the thinning process, the upper surface of the die 122 is substantially flush with the upper surface of the encapsulation material 124. However, while the CMP process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Alternatively, any other suitable removal process can be used to thin the encapsulation material 124 and the die 122. For example, a series of chemical etching processes or any other suitable processes can be used, all of which are fully intended to be included within the scope of the embodiments. In another embodiment, the thinning process may be omitted, and the encapsulation material 124 may cover or expose the upper surface of the die 122. Throughout the description, the resulting structure including the die 122 and the encapsulation material 124 is referred to as the encapsulated die 120, which may have wafer form in the process.

[0074] Then, refer to Figure 7 According to some embodiments, an optical support 130 (also referred to as a support substrate) is bonded to an encapsulated die 120 via a bonding layer 140. The optical support 130 is a rigid structure attached to the encapsulated die 120 to provide structural or mechanical stability. Using the optical support 130 reduces warpage or bending, thereby improving the performance of optical structures such as waveguide 104 or photonic element 106. According to some embodiments, the optical support 130 may be attached to the encapsulated die 120 (e.g., attached to encapsulation material 124 and / or die 122) using a bonding layer 140 formed on encapsulation material 124 and die 122. The bonding layer 140 may be, for example, an adhesive layer or dielectric layer for dielectric-to-dielectric bonding of the optical support 130. The dielectric bonding layer 140 may be a dielectric material suitable for bonding. In some embodiments, a planarization process is performed on the bonding layer 140. In other embodiments, the bonding layer 140 is not formed. In other embodiments, the bonding layer 140 may be an oxide material that is the same as or similar to the encapsulation material 124, so that the optical support 130 is bonded to the encapsulated die 120 by oxide bonding. In some embodiments, the bonding layer 140 may be a high thermal conductivity hybrid bonding layer, which may include a diamond-like carbon (DLC) coating, a silicon carbide coating, or a copper-silicon oxide (Cu-SiO2) coating. x Coatings, silicon oxynitride (SiON) coatings or the like.

[0075] The optical support 130 may comprise one or more materials, such as silicon (e.g., silicon wafer, bulk silicon, or the like), silicon oxide, metal, organic core material, the like, or other types of materials. In some embodiments, the optical support 130 may comprise a semiconductor element, such as germanium (Ge), or a compound semiconductor, such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), or indium phosphide (InP). In some embodiments, the optical support 130 may have a thickness ranging from about 500 μm to about 700 μm. The optical support 130 may also have a lateral dimension (e.g., length, width, and / or area) greater than, about equal to, or smaller than that of the structure. In some embodiments, the optical support 130 includes a bonding layer (not shown separately), which may be an adhesive layer or a layer adapted to bond with the bonding layer 140.

[0076] In some embodiments, the optical support 130 is formed of a material transparent to light of a relevant wavelength, allowing optical signals to be transmitted through the optical support 130. Figure 7 In this example, multiple lens structures (e.g., first lens structure 152 and second lens structure 154) are formed on the optical support 130. Lens structures 152 and 154 facilitate communication between the optical coupler 112 and an external optical signal source (e.g., [missing information]). Figure 8 Improved optical coupling between optical fibers (180) in the fiber optic cable. (Refer to...) Figure 7 and Figure 8 Light from an external optical signal source is sequentially coupled to the optical coupler 112 of the photonic chip 110' via a first lens structure 152 and a second lens structure 154. That is, the light from the optical signal source first passes through the first lens structure 152 and then through the second lens structure 154 to further focus (e.g., modify / reduce) the beam size projected onto the optical coupler 112. In these embodiments, the size (e.g., diameter D1) of the first lens structure 152 is substantially larger than the size (e.g., diameter D2) of the second lens structure 154 to further focus the light coupled to the optical coupler 112. In some embodiments, the lens structures 152, 154 are pre-formed on an optical support 130, which is then bonded to the encapsulated electron chip 120.

[0077] The configuration of the optical support 130 provides mechanical strength to the semiconductor package, increasing the distance between the optical signal source 180 and the optical coupler 112. This can lead to attenuation and / or divergence of the light beam from the optical signal source. Therefore, multiple lens structures 152, 154 are configured to focus the light beam from the optical signal source, allowing the optical coupler 112 to be optically coupled to the optical signal source via the lens structures 152, 154. Furthermore, one lens structure (e.g., the first lens structure 152) can be used to collimate the light from / to the optical signal source 180, while another lens structure (e.g., the second lens structure 154) is used to modify (e.g., reduce) the size of the light beam projected onto the optical coupler 112. Therefore, the size of the light beam projected onto the optical coupler 112, such as that of a grating coupler (GC) and / or an edge coupler (EC), is adjustable and can be tailored to match different optical coupler (e.g., grating coupler and / or edge coupler) designs to optimize coupling efficiency.

[0078] Reference Figure 7 and Figure 8 In this embodiment, the first lens structure 152 and the second lens structure 154 are respectively disposed on two opposing surfaces of the optical support member 130. For example, the second lens structure 154 is disposed on the lower surface S2 of the optical support member 130, which is bonded to the encapsulated electron die 120, while the first lens structure 152 is disposed on the upper surface S1 of the optical support member 130, which is opposite to the lower surface S2. In this embodiment, the second lens structure 154 formed on the lower surface S2 to be bonded to the encapsulated electron die 120 is filled with a filler material 1541, such that the top surface of the filler material 1541 is substantially coplanar with the surface S2 of the optical support member 130. The filler material 1541 may include inorganic materials, such as, but not limited to, alumina (Al2O3), silicon dioxide (SiO2), and silicon nitride (SiN). x (or similar materials). In some embodiments, the material of the filler 1541 may be the same as or similar to the encapsulating material 124, i.e., a light-transparent oxide material.

[0079] An optical signal source 180 is disposed on a substrate and optically coupled to a first lens structure 152 on the upper surface S1. In some embodiments, viewed from a top view, a second lens structure 154 overlaps with the optical coupler 112, and the first lens structure 152 overlaps with the second lens structure 154. Therefore, light from the optical signal source 180 first passes through the first lens structure 152, and then sequentially passes through the second lens structure 154 for further focusing and coupling to the optical coupler 112. By adjusting the size and position of the first lens structure 152 and the second lens structure 154, the beam size projected onto the optical coupler 112 can be precisely adjusted to match different optical coupler designs. It is worth noting that two lens structures are illustrated in the embodiment; however, this disclosure is not limited thereto. More lens structures can be formed on the optical support 130 to meet different optical requirements of semiconductor packaging.

[0080] Now refer to Figure 7 and Figure 8 After the optical support 130 is joined to the encapsulated electron tube die 120, according to some embodiments, Figure 7 The resulting structure is then flipped and attached to a carrier (not shown). The carrier may be, for example, a wafer (e.g., a silicon wafer), a panel, a glass substrate, a ceramic substrate, or the like. The structure may be attached to the carrier using, for example, an adhesive or a release layer (not shown). The back side of the carrier substrate 111' is then thinned until the end of the via 115' is exposed to form a structure as shown. Figure 8 The through-hole 115 shown is shown. The carrier substrate 111 can be thinned by chemical mechanical polishing, mechanical grinding, etching, similar processes, or combinations thereof.

[0081] Then, according to some embodiments, a plurality of conductive pads 172 are formed on the through-hole 115 and the carrier substrate 111. The conductive pads 172 may be conductive pads or conductive pillars electrically connected to the interconnect structure 114. The conductive pads 172 may be formed of conductive materials such as copper, other metals or metal alloys, the like, or combinations thereof. The material of the conductive pads 172 may be formed by suitable processes, such as electroplating. For example, in some embodiments, the conductive pads 172 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar processes. The metal pillars may be solderless and have generally vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive pads 172. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process. In some embodiments, a bottom metal layer (UBM, not shown) may be formed on the conductive pads 172. In some embodiments, a passivation layer 173, such as silicon oxide or silicon nitride, may be formed on the carrier substrate 111 to surround or partially cover the conductive pads 172.

[0082] Then, according to some embodiments, a plurality of conductive connectors 170 may be formed on conductive pads 172 to form a semiconductor package 100. The conductive connectors 170 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using the electroless nickel-electroless palladium-immersion gold technique (ENEPIG), or the like. The conductive connectors 170 may include conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or combinations thereof. In some embodiments, the conductive connectors 170 are formed by initially forming a solder layer using common methods such as vapor deposition, electroplating, printing, solder transfer, balling, or similar methods. Once the solder layer is structurally formed, reflow soldering may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connector 170 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, chemical vapor deposition, or similar processes. The metal pillar may be solderless and have generally vertical sidewalls. In some embodiments, a metal capping layer (not shown) is formed on top of the conductive connector 170. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by an electroplating process. In some embodiments, the conductive connector 170 is electrically connected to the through-hole 115 and may serve as an electrical terminal of the semiconductor package 100.

[0083] Then, after the above process is completed, the resulting structure is in the form of a wafer, and is ready to be divided into individual semiconductor packages 100 by cutting multiple dicing lines to provide... Figure 8 The semiconductor package 100 shown is separated into individual units.

[0084] Through this process and configuration, the encapsulated electron die 120 is directly bonded to the photonic die 110, for example, using hybrid bonding technology, to improve the electrical performance of the semiconductor package 100. The optical support 130 provides mechanical strength, and the lens structures 172 and 174 collimate and further focus the light beam from the optical signal source. Therefore, the optical coupler 112 can be optically coupled to the optical signal source via the lens structures 172 and 174 to avoid or at least reduce beam attenuation and / or divergence from the optical signal source due to the increased distance between the optical signal source 180 and the optical coupler 112.

[0085] Figure 9A cross-sectional view of a semiconductor package according to some exemplary embodiments of the present disclosure is shown. It should be noted that... Figure 9 The semiconductor package 100a shown contains many features that are the same as or similar to those of the semiconductor packages disclosed in the previous embodiments. For clarity and brevity, detailed descriptions of the same or similar features may be omitted, and the same or similar reference numerals denote the same or similar components.

[0086] Reference Figure 9 In this embodiment, the first lens structure 152 and the second lens structure 154 are disposed on the upper surface S1 of the optical support 130, away from the encapsulated die 120. In this embodiment, the semiconductor package 100a may further include a reflector 156 disposed on the lower surface S2 of the optical support 130 bonded to the encapsulated die 120. Furthermore, one of the first lens structure 152 and the second lens structure 154 is coated with a reflective layer 1542. In this embodiment, the reflective layer 1542 is coated on the outer surface of the second lens structure 154. Therefore, light from an external light source (e.g., Figure 8 The light from the optical fiber 180 shown passes through the first lens structure 152 and is sequentially reflected by the reflective layer 1542 on the mirror 156 and the second lens structure 154 to couple to the optical coupler 112. In these embodiments, the size (e.g., diameter) of the first lens structure 152 through which the light first passes is generally larger than the size (e.g., diameter) of the second lens structure 154 through which the light subsequently strikes, such that the smaller second lens structure 154 can further focus the light coupled to the optical coupler 112.

[0087] In this embodiment, a reflector 156 may be formed below the first lens structure 152 to reflect light passing through the first lens structure 152 toward the second lens structure 154. Thus, the first lens structure 152 and the second lens structure 154 may be disposed on the same surface (e.g., the upper surface S1) and may be formed simultaneously before or after the optical support 130 is bonded to the encapsulated electronic die 120. According to some embodiments, the reflector 156 and the reflective layer 1542 may be formed by depositing a reflective material. The reflective material may comprise a metallic or dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may comprise metals such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal may be deposited using suitable processes such as sputtering, electroplating, chemical vapor deposition, or similar processes. In some embodiments, a seed layer may be deposited first, followed by the deposition of the metal on the seed layer. In other embodiments, the reflective material may comprise a dielectric material such as silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the thickness of the reflective material is in the range of about 10 nanometers to about 1000 nanometers, but other thicknesses are also possible. In some embodiments, the reflective material has a reflectivity greater than about 90% for light of a suitable wavelength, but other values ​​are also possible.

[0088] Figure 10 Cross-sectional views of a semiconductor package are illustrated according to some exemplary embodiments of this disclosure. It is worth noting that... Figure 10 The semiconductor package 100b shown includes many features that are the same as or similar to those of the semiconductor packages disclosed in the previous embodiments. For clarity and brevity, detailed descriptions of the same or similar features may be omitted, and the same or similar elements are indicated by the same or similar reference numerals.

[0089] Reference Figure 10In this embodiment, the optical coupler 112b is an edge coupler (EC), which allows optical signals and / or optical power to be transmitted to / from the waveguide 104, which is horizontally mounted near the sidewall of the photonic package 100. Therefore, the first lens structure 152 and the second lens structure 154 are disposed on the upper surface S1 of the optical support 130, away from the encapsulated die 120, while the reflector 156 is disposed on the lower surface S2 of the optical support 130, and the second lens structure 154 is coated with a reflective layer 1542. Furthermore, the semiconductor package 100b also includes another reflector 118 disposed in the photonic die 110. In some embodiments, the reflector 118 may be formed in the dielectric layer 103 covering the waveguide 104 and the edge coupler 112b. The reflector 118 is configured such that light reflected by the reflective layer 1542 on the second lens structure 154 strikes the reflector 118 and is reflected as a horizontal beam toward the edge coupler 112b. Therefore, light from an external optical signal source (e.g., Figure 8 The light from the fiber 180 shown first passes through the first lens structure 152, and is then reflected sequentially by the reflective layer 1542 on the second lens structure 154 and the reflective mirror 118, to be horizontally coupled to the edge coupler 112b. In this embodiment, the size (e.g., diameter) of the first lens structure 152 through which the light first passes is generally larger than the size (e.g., diameter) of the second lens structure 154 through which the light subsequently hits, such that the smaller second lens structure 154 can further focus the light coupled to the edge coupler 112b.

[0090] Figures 11 to 16 A partial cross-sectional view of an intermediate manufacturing stage of forming a lens structure on a semiconductor package is illustrated according to some exemplary embodiments of this disclosure. Various methods are suitable for forming... Figure 8 The optical support 130 shown has a first lens structure 152 and a second lens structure 154 on two opposing surfaces of the optical support 130. Figures 11 to 16 This disclosure is only intended to illustrate one possible method and is not limited thereto.

[0091] Reference Figure 8 and Figure 11In this embodiment, a lens structure (i.e., a second lens structure 154) is first formed on the surface of the optical support 130 (the lower surface S2 to which it will be bonded to the encapsulated die 120). The method for forming the lens structure 154 includes the following steps: First, a patterned polymer layer 160 is formed on the surface S2 of the optical support 130. A polymer layer may be deposited on the optical support 130 first, and then patterned using a typical photolithography process to form the patterned polymer layer 160. The patterned polymer layer 160 is a cylindrical pattern of polymer material covering the area where the lens structure 154 will be formed. The patterned polymer layer 160 can serve as an etching protection layer in a later etching step of the optical support 130. In this sense, at least the surface portion of the optical support 130 may be formed of a material with etching selectivity to the patterned polymer layer 160. For example, the patterned polymer layer 160 can be made of polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl alcohol (PVA), polytetrafluoroethylene (PTFE), poly(methylmethacrylate) (PMMA), polyvinyl chloride (PVC), poly(ethylene terephthalate) (PET), polyester, phenolic resin, urea resin, urethane resin, polyurethane, etc. The patterned polymer layer 160 can be formed to an appropriate thickness, for example, considering the patterning burden, a thickness of 1 μm or less. The patterned polymer layer 160 can be formed using a suitable coating or printing method, such as spin coating, blade coating, electrostatic spraying, etc. Then, a reflow soldering process is performed on the patterned polymer layer 160 to form the polymer lens structure 160, such as... Figure 11 As shown, it has a curved surface formed by the surface tension of the polymer.

[0092] Then, refer to Figure 12 An etching process is performed on the surface S2 of the optical support 130 on which the polymer lens structure 160 is provided to transfer the curved profile of the polymer lens structure 160 onto the surface S2 of the optical support 130 and form a lens structure 154'. The lens structure 154' protruding from the surface S2 of the optical support 130 can also be used as a lens for collimating and / or focusing a beam. However, in this embodiment, Figure 8The top surface of the lens structure 154 shown is substantially equal to or lower than the surface S2 of the optical support 130. Therefore, another etching process is used.

[0093] Reference Figure 13 A patterned mask layer 162 is provided on the surface S2 of the optical support 130, and the patterned mask layer 162 includes exposure Figure 12 The lens structure 154' shown has an opening OP1. Then, another etching process is performed to form... Figure 13 The lens structure 154 is shown. The etching process may include one or more dry etching processes and / or wet etching processes. In this embodiment, the etching process includes a dry etching process, which involves selective material removal by ion-assisted processes such as ion beam etching (IBE), reactive ion etching (RIE), and inductively coupled plasma (ICP) etching or similar processes, but this disclosure is not limited thereto. Therefore, the resulting lens structure 154 includes a notch recessed from the outer surface (e.g., surface S2) of the optical support 130, and the notch includes non-vertical sidewalls 1543 and a convex bottom surface 1544 having a circular or spherical shape. Then, the patterned mask layer 162 is removed.

[0094] Reference Figure 14 Then Figure 13 The resulting structure is flipped, and through a similar Figures 11 to 13 The process shown forms a first lens structure 152 on the upper surface S1 of the optical support 130.

[0095] Then, refer to Figure 15 and Figure 16 A filler material 1541 is provided to fill the notch of the second lens structure 154. The filler material 1541 can be dispensed onto the surface S2 of the optical support 130 to form a filler material layer 1541'. The filler material layer 1541' can be dispensed in a liquid form and has high viscosity. After dispensing, the filler material layer 1541' can be cured into a solid form. Then, refer to... Figure 16 A planarization process can be performed on the filler material layer 1541' to remove excess filler material until the surface S2 of the optical support 130 is exposed. The planarization process may include CMP, etching, or similar processes. Therefore, the filler material 1541 fills the notch of the second lens structure 154, and the top surface of the filler material 1541 is substantially coplanar with the surface S2 of the optical support 130. The filler material 1541 may include inorganic materials, such as, but not limited to, alumina (Al2O3), silicon dioxide (SiO2), and silicon nitride (SiN). x(or similar materials). In some embodiments, the material of the filler 1541 may be the same as or similar to the material of the encapsulating material 124, which is a light-transparent oxide material.

[0096] After the filling material 1541 is filled into the recess of the second lens structure 154, the lower surface S2 of the optical support 130 having the second lens structure 174 filled with the filling material 1541 is then as follows: Figure 8 The shown component is bonded to the encapsulated electron tube die 120. It is noteworthy that, in other embodiments, the filler material 1541 may be provided immediately after the second lens structure 174 is formed, and then the optical support 130 may be flipped to form the first lens structure 172 on the upper surface S1. This disclosure does not limit the process sequence disclosed herein.

[0097] Figures 17 to 21 This illustration shows a partial cross-sectional view of an intermediate stage in the fabrication of a lens structure on a semiconductor package according to other exemplary embodiments of the present disclosure. Various methods are suitable for forming... Figure 9 The optical support 130a shown has a first lens structure 152 and a second lens structure 154 located on the same surface of the optical support 130a. Figures 17 to 21 This disclosure is limited to one possible method for illustrative purposes only.

[0098] Reference Figure 17 In this embodiment, the reflector 156 is formed on the surface S2 of the optical support 130a, and the surface will be as follows: Figure 9The optical support 130a is attached to the encapsulated electron die 120. According to some embodiments, an opening OP2 is formed on surface S2 of the optical support 130a. The opening OP2 can be formed using acceptable photolithography and etching techniques, such as by forming and patterning a photoresist, and then performing an etching process using the patterned photoresist as an etching mask. The etching process may include, for example, dry etching and / or wet etching processes, which may be anisotropic etching. Then, according to some embodiments, a reflective material is deposited in the opening OP2 to form a mirror 156. The reflective material may include a metallic or dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may include metals such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal can be deposited using suitable processes such as sputtering, electroplating, CVD, or similar processes. In some embodiments, a seed layer may be deposited first, and then the metal may be deposited on the seed layer. In other embodiments, the reflective material may include a dielectric material of silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as PVD, CVD, ALD, or similar processes. In some embodiments, the thickness of the reflective material is between about 10 nm and about 1000 nm, but other thicknesses are also possible. In some embodiments, the reflective material may fill the opening OP2. A planarization process (e.g., CMP or polishing) may be performed to remove excess reflective material. After the planarization process, the top surface of the mirror 156 and the surface S2 of the optical support 130a may be substantially flush or coplanar. In some embodiments, the reflective material has a reflectivity greater than about 90% for light of an appropriate wavelength, but other values ​​are also possible.

[0099] In other embodiments, the reflector 156 can be directly deposited or sputtered onto the surface S2 of the optical support 130a without forming an opening OP2. A filler material can then be applied to cover the surfaces S2 of both the reflector 156 and the optical support 130a. Next, a planarization process (e.g., CMP or polishing) can be performed on the filler material to flatten the surface for subsequent bonding processes.

[0100] Reference Figure 18 The optical support 130a is then flipped to form a first lens structure and a second lens structure on the upper surface S1 of the optical support 130a. The process for forming the first lens structure and the second lens structure may be similar to... Figures 11 to 13 The process is illustrated. For example, a patterned polymer layer is formed on the upper surface S1 of the optical support 130a to cover the areas where the first lens structure 152 and the second lens structure 154 will be formed. Then, a reflow soldering process is performed on the patterned polymer layer to form a plurality of polymer lens structures 160', corresponding to the areas where the first lens structure 152 and the second lens structure 154 will be formed, respectively. Figure 18 As shown, each polymer lens structure 160' has a curved surface formed by the surface tension of the polymer. For example, the polymer lens structure 160' may be made of polyimide (PI), polyethylene (PE), polypropylene (PP), polystyrene (PS), polyvinyl alcohol (PVA), polytetrafluoroethylene (PTFE), polymethyl methacrylate (PMMA), polyvinyl chloride (PVC), polyethylene terephthalate (PET), polyester, phenolic resin, urea resin, amino resin, polyurethane, etc.

[0101] Then, refer to Figure 19 An etching process is performed on the upper surface S1 of the optical support 130a, which has polymer lens structures 160', to transfer the curved profile of each polymer lens structure 160 onto the upper surface S1 of the optical support 130a. Thus, a shape is formed as shown... Figure 19 The first lens structure 152' and the second lens structure 154' are shown. The first lens structure 152' and the second lens structure 154', protruding from the upper surface S1 of the optical support 130a, can also be used as lenses for collimating and / or focusing beams. However, in this embodiment, Figure 9 The top surfaces of the first lens structure 152 and the second lens structure 154 shown are generally equal to or lower than the upper surface S1 of the optical support 130a. Therefore, another etching process is used.

[0102] Reference Figure 20 A patterned mask layer 162 is provided on the upper surface S1 of the optical support 130a. The patterned mask layer 162 includes a plurality of openings OP1, which expose the first lens structure 152 and the second lens structure 154, respectively. Then, another etching process is performed to form Figure 20 The first lens structure 152 and the second lens structure 154 are shown. In some embodiments, from a top view, the reflector 156 is located between the first lens structure 172 and the second lens structure 174. The etching process may include one or more dry etching processes and / or wet etching processes. In this embodiment, the etching process includes a dry etching process, which involves selective material removal by ion-assisted processes (such as ion beam etching (IBE), reactive ion etching (RIE), and inductively coupled plasma (ICP) etching) or similar processes, but this disclosure is not limited thereto. Therefore, the first lens structure 152 and the second lens structure 154 each include a notch recessed from the upper surface S1 of the optical support 130a, the notch including non-vertical sidewalls and a convex bottom surface (having an arcuate or spherical shape). Then, the patterned mask layer 162 is removed.

[0103] Next, a reflective layer 1542 is formed on the surface of the second lens structure 174. Therefore, a reflector 156 is formed below the first lens structure 152 to reflect light passing through the first lens structure 152 toward the second lens structure 154. The light is reflected by the reflective layer 1542 on the second lens structure 154 to couple to the optical coupler 112, as shown below. Figure 9 As shown. In this manner, the first lens structure 152 and the second lens structure 154 are located on the same surface (e.g., the upper surface S1) and can be formed simultaneously, thereby simplifying the manufacturing process. According to some embodiments, the reflector 156 and the reflective layer 1542 can be formed by depositing a reflective material. The reflective material may include a metallic material or a dielectric material that is reflective to light of a relevant wavelength. For example, in some embodiments, the reflective material may include metals such as copper, silver, gold, tungsten, cobalt, aluminum, alloys thereof, combinations thereof, or the like. The metal may be deposited using suitable processes such as sputtering, electroplating, chemical vapor deposition, or similar processes. In some embodiments, the metal may be deposited first as a seed layer and then deposited on the seed layer. In other embodiments, the reflective material may include a dielectric material such as silicon, silicon oxide, silicon nitride, titanium oxide, tantalum oxide, titanium nitride, tantalum nitride, combinations thereof, or the like. The dielectric material may be deposited using suitable processes such as physical vapor deposition, chemical vapor deposition, atomic layer deposition, or similar processes. In some embodiments, the thickness of the reflective material ranges from about 10 nm to about 1000 nm, but other thicknesses are also possible. In some embodiments, the reflective material has a reflectivity to light of an appropriate wavelength greater than about 90%, but other values ​​are also possible.

[0104] Based on the above discussion, it can be seen that this disclosure provides various advantages. However, it should be understood that not all advantages need to be discussed herein, and other embodiments may provide different advantages, and no particular advantage is required in any embodiment.

[0105] Other features and processes may also be included. For example, test structures may be included to aid in verification testing of 3D packaged or 3DIC devices. Test structures may include, for example, test pads formed in redistribution layers or on a substrate, to enable testing of 3D packages or 3DICs, use of probes and / or probe cards, and similar operations. Verification tests can be performed on intermediate and final structures. Furthermore, the structures and methods disclosed herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0106] According to some embodiments of this disclosure, a semiconductor package includes a photonic die containing an optical coupler, an electronic die bonded to the photonic die, and an optical support bonded to the electronic die and including a plurality of lens structures. Light from an external optical signal source is sequentially coupled to the optical coupler through the plurality of lens structures. In one embodiment, the semiconductor package further includes an encapsulation material that at least laterally encapsulates the electronic die. In one embodiment, the photonic die includes a carrier substrate, a photonic layer including the optical coupler, and interconnect structures disposed on the photonic layer. In one embodiment, the electronic die is bonded to and electrically connected to the interconnect structures. In one embodiment, the plurality of lens structures includes a first lens structure and a second lens structure respectively disposed on two opposing surfaces of the optical support. In one embodiment, the second lens structure is disposed on a lower surface of the optical support bonded to the electronic die, and, from a top view, the second lens structure overlaps with the optical coupler. In one embodiment, the plurality of lens structures includes a first lens structure and a second lens structure disposed on an upper surface of the optical support away from the electronic die. In one embodiment, one of the first lens structure and the second lens structure is coated with a reflective layer. In one embodiment, the semiconductor package further includes a reflector disposed on a lower surface of the optical support opposite to the upper surface, wherein light from the external optical signal source passes through the first lens structure and is sequentially reflected by the reflector and the second lens structure to couple to the optical coupler. In another embodiment, the semiconductor package further includes a first reflector disposed on the lower surface of the optical support opposite to the upper surface and a second reflector disposed in the photonic die. In another embodiment, light from the external optical signal source passes through the first lens structure and is sequentially reflected by the first reflector, the second lens structure, and the second reflector to couple to the optical coupler.

[0107] According to some embodiments of this disclosure, a semiconductor package includes a photonic die containing an optical coupler, an electronic die bonded to the photonic die, and an optical support bonded to the electronic die. The optical support includes a first lens structure and a second lens structure configured to sequentially couple light to the optical coupler via the first lens structure and the second lens structure, wherein the size of the first lens structure is substantially larger than the size of the second lens structure. In one embodiment, each of the first lens structure and the second lens structure includes a notch recessed from an outer surface of the optical support. In one embodiment, the notch includes a non-vertical sidewall and a convex bottom surface. In one embodiment, the first lens structure and the second lens structure are respectively disposed on two opposing surfaces of the optical support, and the size of the first lens structure is substantially larger than the size of the second lens structure. In one embodiment, both the first lens structure and the second lens structure are disposed on the upper surface of the optical support remote from the encapsulated electronic die.

[0108] According to some embodiments of this disclosure, a method of manufacturing a semiconductor package includes: providing a photonic die, wherein the photonic die includes an optical coupler; bonding an electron die to the photonic die; providing an encapsulating material on the photonic die to form an encapsulated electron die, wherein the encapsulating material at least laterally encapsulates the electron die; forming a first lens structure and a second lens structure on an optical support; and bonding the optical support to the encapsulated electron die, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the first lens structure and the second lens structure. In one embodiment, forming the first lens structure and the second lens structure on the optical support further includes: forming the second lens structure on a lower surface of the optical support to be bonded to the encapsulated electron die, wherein the second lens structure includes a notch; forming the first lens structure on an upper surface of the optical support opposite to the lower surface; and providing a filler material to fill the notch, wherein the lower surface of the optical support having the second lens structure filled with the filler material is bonded to the encapsulated electron die. In one embodiment, the method further includes: forming a reflector on a lower surface of the optical support to be bonded to the encapsulated electron tube die, wherein forming the first lens structure and the second lens structure on the optical support further includes: forming the first lens structure and the second lens structure on an upper surface of the optical support opposite to the lower surface; and forming a reflective layer on the surface of the second lens structure, wherein, from a top view, the reflector is located between the first lens structure and the second lens structure. In one embodiment, forming the first lens structure and the second lens structure on the optical support further includes: forming a patterned polymer layer on the optical support; performing a reflow soldering process on the patterned polymer layer to form a polymer lens structure; and performing an etching process on the surface of the optical support having the polymer lens structure to transfer the contour of the polymer lens structure onto the optical support.

[0109] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages of the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of this disclosure, and that various alterations, substitutions, and changes can be made to this document without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor package, characterized in that, include: Photonic chip, including optical coupler; An electron chip is bonded to the photonic chip; as well as An optical support, attached to the electron tube die, includes multiple lens structures, wherein light from an external optical signal source is sequentially coupled to the optical coupler via the multiple lens structures.

2. The semiconductor package according to claim 1, characterized in that, The plurality of lens structures include a first lens structure and a second lens structure, which are respectively disposed on two opposite surfaces of the optical support. The second lens structure is disposed on the lower surface of the optical support that is coupled to the electron tube die, and, from a top view, the second lens structure overlaps with the optical coupler.

3. The semiconductor package according to claim 1, characterized in that, The plurality of lens structures, including a first lens structure and a second lens structure, are disposed on the upper surface of the optical support member away from the electron tube die.

4. The semiconductor package according to claim 3, characterized in that, One of the first lens structure and the second lens structure is coated with a reflective layer.

5. The semiconductor package according to claim 3, characterized in that, It also includes a reflector disposed on the lower surface of the optical support opposite to the upper surface, wherein the light from the external light source passes through the first lens structure and is sequentially reflected by the reflector and the second lens structure to couple to the optical coupler.

6. The semiconductor package according to claim 3, characterized in that, It also includes a first reflecting mirror disposed on the lower surface of the optical support opposite to the upper surface and a second reflecting mirror disposed in the photonic chip.

7. A semiconductor package, characterized in that, include: Photonic chip, including optical coupler; The encapsulated electron chip is then bonded to the photonic chip. as well as An optical support, coupled to the encapsulated electron tube die, includes a first lens structure and a second lens structure for sequentially coupling light to the optical coupler.

8. The semiconductor package according to claim 7, characterized in that, Each of the first lens structure and the second lens structure includes a recess recessed from the outer surface of the optical support, and the recess includes a non-vertical sidewall and a convex bottom surface.

9. The semiconductor package according to claim 7, characterized in that, The first lens structure and the second lens structure are respectively disposed on two opposite surfaces of the optical support, and the size of the first lens structure is larger than the size of the second lens structure.

10. The semiconductor package according to claim 7, characterized in that, Both the first lens structure and the second lens structure are disposed on the upper surface of the optical support member away from the encapsulated electron tube die.

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