Device packaging

Abstract

A device package includes a grating coupler and a dielectric plug adjacent to the grating coupler. The dielectric plug defines a light signal path via which a light signal propagates to the grating coupler. To provide increased confinement of the light signal to reduce scattering and reduce crosstalk with other light signals, a reflector structure is included around a perimeter of the dielectric plug. The reflector structure is formed of a light-reflective material, such as one or more metallic materials. The reflector structure can reduce the likelihood of the light signal scattering into semiconductor device layers surrounding the dielectric plug by reflecting the light signal toward the grating coupler. Additionally and / or otherwise, the reflector structure can reduce the likelihood of the light signal being interfered with by other light signals by reflecting the other light signals away from the grating coupler.

Description

Technical Field

[0001] This disclosure relates to a device package. Background Technology

[0002] Semiconductor devices may include one or more photonic components for high-speed, high-bandwidth, and / or secure optical communication between integrated circuits and / or semiconductor chips of the semiconductor device using optical signals. Utility Model Content

[0003] Some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers over the grating coupler, a dielectric plug over the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewall of the dielectric plug.

[0004] Some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers above the grating coupler, a dielectric plug above the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewall of the dielectric plug. The dielectric plug is located in a region of the first integrated circuit die extending laterally outward from the second integrated circuit die. In a top view of the reflector structure, the reflector structure continuously surrounds the top view periphery of the dielectric plug.

[0005] Some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers over the grating coupler, a dielectric plug over the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewall of the dielectric plug, the reflector structure being positioned at an angle relative to the substrate of the second integrated circuit die. Attached Figure Description

[0006] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation.

[0007] Figures 1A to 1C This is a schematic diagram illustrating an example of the device package described in this article.

[0008] Figures 2A to 2D The illustration shows an example top view of the dielectric plug and associated reflector structure described in this article.

[0009] Figures 3A to 3L This is a schematic diagram of an example embodiment of an integrated circuit (IC) die as described herein.

[0010] Figures 4A to 4G This is a schematic diagram of an example embodiment of the device package described herein.

[0011] Figure 5A and Figure 5B This is a schematic diagram of an example embodiment of the device package described herein.

[0012] Figure 6 This is a schematic diagram of an example embodiment of the device package described herein.

[0013] Figure 7 This is a schematic diagram of an example embodiment of the device package described herein.

[0014] Figure 8 This is a schematic diagram of an example embodiment of the device package described herein.

[0015] Figure 9 This is a schematic diagram of an example embodiment of the device package described herein.

[0016] Figure 10 This is a schematic diagram of an example embodiment of the device package described herein.

[0017] Figure 11 This is a flowchart of an example process associated with forming the semiconductor device described herein.

[0018] [Symbol Explanation]

[0019] 100: Example Implementation

[0020] 102: Device Packaging

[0021] 104, 106: IC die

[0022] 108: Grating Coupler

[0023] 110: Joint Interface

[0024] 112, 114: Bonding dielectric layer

[0025] 116, 118: Joint structure

[0026] 120a, 120b: Dielectric filling layer

[0027] 122, 124, 126, 128, 130: Passivation layer

[0028] 132a,132b:Substrate

[0029] 134a, 134b: ILD layers

[0030] 136a, 136b: IC devices

[0031] 138a, 138b: Contacts

[0032] 140a, 140b: ILD layers

[0033] 142a, 142b: ESL

[0034] 144a, 144b: Conductive structure

[0035] 146a, 146b: Sealing ring structure

[0036] 148a, 148b: Passivation layers

[0037] 150a, 150b: Metal pad structure

[0038] 152a, 152b: Metal pad structure

[0039] 154a, 154b: Passivation layers

[0040] 156: Dielectric layer

[0041] 158a, 158b: Joint pads

[0042] 160: Through-substrate interconnect structure

[0043] 162: Connection Structure

[0044] 164: Dielectric embolism

[0045] 166: Incident light

[0046] 168: Reflector Structure

[0047] 170: Semiconductor layer

[0048] 172: Embedded Dielectric Layer

[0049] 174: Dielectric layer

[0050] 200: Top view shape

[0051] 202: Top

[0052] 204: Bottom

[0053] 206: Top View Shape

[0054] 208: Top View Shape

[0055] 210: Top view shape

[0056] 300: Example Implementation

[0057] 302: Carrier substrate

[0058] 304: Groove

[0059] 400: Example Implementation

[0060] 500: Example Implementation

[0061] 502: Non-active grains

[0062] 504: Gap

[0063] 600: Example Implementation

[0064] 602: Reflector Structure

[0065] 700: Example Implementation

[0066] 800: Example Implementation

[0067] 802: Non-active grains

[0068] 900: Example Implementation

[0069] 902: Reflector Structure

[0070] 1000: Example Implementation

[0071] 1002: Reflector Structure

[0072] 1100: Process

[0073] 1110, 1120, 1130, 1140, 1150, 1160: Squares

[0074] AA: Line

[0075] D1, D2, D3, D4, D5, D6: Dimensions

[0076] x, y, z: axes Detailed Implementation

[0077] The following disclosure provides numerous different embodiments or examples of various features for the subject matter provided in the embodiments. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0078] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” “upper,” and the like are used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptors used herein can be interpreted similarly accordingly.

[0079] The semiconductor device may include a grating coupler for receiving optical signals (e.g., laser signals or incident light) and directing the optical signals toward a photodetector within the semiconductor device. The photodetector can convert the optical signals into electrical signals, which can be processed by the integrated circuit (IC) device of the semiconductor device.

[0080] In some cases, the reception of optical signals at the grating couplers of a semiconductor device may be interfered with for various reasons. For example, a semiconductor device may include multiple grating couplers positioned close to each other, and the optical signals directed to these grating couplers may interfere with each other (a phenomenon known as optical crosstalk), which can increase conversion errors when converting the optical signals to electrical signals. The grating couplers may be further spaced apart to reduce the likelihood of optical crosstalk; this increases the lateral dimensions of the semiconductor device. As another example, optical signals may propagate through multiple layers before reaching the grating couplers of the semiconductor device, and the longer the distance traveled through these layers, the greater the scattering of the optical signal.

[0081] In some embodiments described herein, the semiconductor device includes a grating coupler and a dielectric plug adjacent to the grating coupler. The dielectric plug defines an optical signal path through which the optical signal propagates to the grating coupler. To provide additional limitation on the optical signal, thereby reducing scattering and crosstalk with other optical signals, a reflector structure is included around the dielectric plug. The reflector structure is formed of a light-reflecting material, such as one or more metallic materials. The reflector structure reduces the likelihood of the optical signal being scattered into the semiconductor device layer surrounding the dielectric plug by reflecting the optical signal toward the grating coupler. Additionally and / or otherwise, the reflector structure reduces the likelihood of the optical signal being interfered with by other optical signals by reflecting other optical signals away from the grating coupler. In this way, the reflector structure reduces the scattering and / or interference of the optical signal, which reduces the likelihood and / or rate of conversion errors when converting the optical signal into an electrical signal.

[0082] Figures 1A to 1C This is a schematic diagram of an example embodiment 100 of the device package 102 described herein. The device package 102 includes a packaged semiconductor device comprising a plurality of active IC dies or wafers. The plurality of active IC dies may be vertically configured and / or stacked in the device package 102 using three-dimensional (3D) packaging techniques such as direct bonding.

[0083] Figure 1A The diagram shows a top view of the device package 102. Figure 1A As shown, the device package 102 may be a semiconductor device, which includes an IC die 104 and an IC die 106 bonded to the IC die 104. The IC die 106 is included on the IC die 104, such that the IC dies 104 and 106 are stacked in the z-direction and vertically arranged in the device package 102.

[0084] IC die 104 is a semiconductor device that includes one or more photonic components, such as grating couplers, waveguides, photodiodes, shunts, polarizers, optical modulators, optical resonators, and / or edge couplers, as well as other examples. IC die 104 can be used to receive and / or transmit optical signals, process optical signals, and / or perform other functions associated with the optical signals. In some embodiments, IC die 104 is used to convert optical signals into electrical signals, and / or convert electrical signals into optical signals.

[0085] IC die 106 may include an active integrated circuit of device package 102 and may be used to perform various processing functions of device package 102. For example, IC die 106 may be used to process electrical signals converted from optical signals by IC die 104. As another example, IC die 106 may generate electrical signals that will be converted into optical signals by IC die 104. Examples of IC chips 104 include logic IC chips, memory IC chips, high-bandwidth memory (HBM) IC chips, input / output (I / O) chips, system-on-chip (SoC) IC chips, dynamic random access memory (DRAM) IC chips, complementary metal-oxide-semiconductor (CMOS) image sensor IC chips, silicon photonics IC chips, central processing unit (CPU) IC chips, graphics processing unit (GPU) IC chips, digital signal processing (DSP) IC chips, application-specific integrated circuit (ASIC) IC chips, and / or another type of active IC chip.

[0086] like Figure 1A As further shown, the top view area of ​​IC die 106 may differ from that of IC die 104. For example, the top view size of IC die 104 (e.g., the size of the xy region occupied by IC die 104) may be larger than the top view size of IC die 106 (e.g., the size of the xy region occupied by IC die 106). This allows one or more grating couplers 108 to be positioned within IC die 104, thereby providing the grating couplers 108 with an unobstructed light propagation path laterally adjacent to IC die 106.

[0087] Figure 1B The diagram follows Figure 1A Cross-sectional view of device package 102 with centerline AA. Therefore, Figure 1B The cross-sectional view shown includes IC die 104 and IC die 106 above and / or on IC die 104.

[0088] like Figure 1BAs shown, IC dies 104 and 106 are bonded together at bonding interface 110. IC dies 104 and 106 can be directly bonded (e.g., without an intermediate interposer or another intermediate structure), such that IC dies 104 and 106 are stacked in the z-direction and vertically configured in device package 102.

[0089] The bonding interface 110 may include a dielectric-to-dielectric bonding between the dielectric layer (or bonding dielectric layer) 112 of the IC die 104 and the bonding dielectric layer 114 of the IC die 106. Each of the bonding dielectric layers 112 and 114 includes one or more types of dielectric materials, such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)) and / or another type of dielectric bonding material.

[0090] Additionally and / or otherwise, the bonding interface 110 may include a metal-to-metal bond between the bonding structure 116 of the IC die 104 and the bonding structure 118 of the IC die 106. The bonding structures 116 and 118 may each include a bonding via, a bonding pad, and / or other types of bonding structures, and may each include one or more metals, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au), as well as other conductive materials.

[0091] like Figure 1B As further shown, the region surrounding the sides of IC die 104 is filled with a dielectric filling layer 120a (e.g., a filling material layer), such that the dielectric filling layer 120a surrounds IC die 104, and the region surrounding the sides of IC die 106 is filled with a dielectric filling layer 120b (e.g., a filling material layer), such that the dielectric filling layer 120b surrounds IC die 106. The dielectric filling layers 120a and 120b may each include one or more dielectric materials, such as silicon oxide (SiO2). x (e.g., silicon dioxide (SiO2)), silicon oxynitride (SiON), and / or another type of dielectric material. The dielectric filling layers 120a and 120b can provide enhanced stability and electrical isolation for IC dies 104 and 106.

[0092] Among other examples, device package 102 includes a plurality of passivation layers, including passivation layers 122 and 124 above and / or on the bottom side of device package 102, and passivation layers 126, 128, and 130 above and / or on the top side of device package 102, and other examples. In some embodiments, passivation layers 122, 124, 126, 128, and 130 may each comprise various types of electrically insulating materials, such as silicon nitride (Si). x N y ), undoped silicate glass (USG), silicon dioxide (SiO2)x (e.g., silicon dioxide (SiO2)), and / or another type of passivation material.

[0093] IC chips 104 and 106 may each include a substrate (e.g., substrate 132a in IC chip 104 and substrate 132b in IC chip 106). Substrates 132a and 132b may each include a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or another type of semiconductor substrate.

[0094] IC dies 104 and 106 may each include multiple stacked layers, including interlayer dielectric (ILD) layers (e.g., ILD layer 134a on substrate 132a and ILD layer 134b on substrate 132b). ILD layers 134a and 134b may each include silicon nitride (Si). x N y ), oxides (e.g., silicon oxide (SiO2) x (and / or another oxide material), and / or another type of dielectric material.

[0095] IC chips 104 and 106 may each include an IC device (e.g., IC device 136a in substrate 132a and / or ILD layer 134a, IC device 136b in substrate 132b and / or ILD layer 134b). IC device 136a of IC chip 104 may include photonic devices such as modulators, photodetectors, resonators, and / or waveguides, and other examples. A grating coupler 108 may also be included in substrate 132a of IC chip 104. Therefore, IC chip 104 may be referred to as a photonic integrated circuit (PIC) chip.

[0096] Each grating coupler 108 may include a plurality of gratings. In some embodiments, the gratings may be periodic, and the periodicity of the gratings may be selected to achieve diffraction of one or more wavelengths of the optical signal. In some embodiments, the periodicity of the gratings may be selected based on wavelength(s) for optical communication, or based on wavelength(s) for wavelength division multiplexing (WDM) and / or for other purposes.

[0097] The grating coupler 108 may be located in a portion or region of IC die 104 extending laterally outward from IC die 106. This provides an unobstructed optical propagation path for the optical signal to the grating coupler 108. The grating coupler 108 may be configured to redirect the optical signal to IC device 136a for processing (e.g., demodulation, filtering, photoelectric conversion).

[0098] In some embodiments, the grating coupler 108 is formed of a semiconductor material, such as silicon (Si), germanium (Ge), and / or silicon-germanium (SiGe), and other examples. In some embodiments, the grating coupler 108 is formed of a dielectric material, such as silicon nitride (SiGe). x N y Such as Si3N4) and / or silicon oxide (SiO) x (such as SiO2), and other examples. In some embodiments, the grating coupler 108 is a hybrid grating coupler structure, which includes a two-layer structure having dielectric and semiconductor portions.

[0099] IC device 136b of IC die 106 may include front-end transistor structures (e.g., front-end planar transistor structures, front-end fin field-effect transistor (finFET) structures, front-end gate all-around (GAA) transistor structures), pixel sensors, capacitors, resistors, inductors, photosensors, transceivers, transmitters, receivers, optical circuits, and / or other types of front-end semiconductor devices. IC device 136b can receive electrical signals from IC device 136a of IC die 104 and can use it to process these electrical signals. Therefore, IC die 106 may be referred to as an electronic IC (EIC) die.

[0100] IC chips 104 and 106 may each include contacts (e.g., contacts 138a and 138b) electrically coupled to an IC device. Contact 138a may extend through ILD layer 134a and be electrically coupled to IC device 136a, and contact 138b may extend through ILD layer 134b and be electrically coupled to IC device 136b. Contacts 138a and 138b may include vias, plugs, and / or other types of elongated conductive structures. Contacts 138a and 138b may include tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), and / or gold (Au), and other conductive materials.

[0101] IC dies 104 and 106 may each include multiple dielectric layers arranged alternately in the z-direction within the device package 102. For example, IC die 104 may include multiple alternating ILD layers 140a and etch stop layers (ESL) 142a. IC die 104 may include multiple conductive structures 144a in the ILD layers 140a and ESL 142a. The substrate 132a, ILD layer 134a, IC device 136a (and / or grating coupler 108), and contact 138a may correspond to the device layer or front end of line (FEOL) region of IC die 104, and the ILD layer 140a, ESL 142a, and conductive structures 144a may correspond to the interconnect layer or back end of line (BEOL) region of IC die 104.

[0102] Similarly, IC die 106 may include multiple alternating ILD layers 140b and ESL 142b. IC die 106 may include multiple conductive structures 144b in ILD layers 140b and ESL 142b. Substrate 132b, ILD layer 134b, IC device 136b, and contact 138b may correspond to the device layer or FEOL region of IC die 106, and ILD layer 140b, ESL 142b, and conductive structure 144b may correspond to the interconnect layer or BEOL region of IC die 106.

[0103] ILD layers 140a and 140b may each comprise an oxide (e.g., silicon oxide (SiO2)). x (and / or another oxide material), undoped silicate glass (USG), borosilicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or another suitable dielectric material. In some embodiments, ILD layers 140a or 140b comprise an extremely low dielectric constant (ELK) dielectric material having a dielectric constant of less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiO2). x amorphous fluorinated carbon (aC) x F y), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon carbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silica (SiO2). x ), and other examples. ESL 142a and 142b may each include silicon nitride (Si). x N y ), silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material.

[0104] Conductive structures 144a and 144b provide circuitry that enables signals and / or power to be supplied to, and / or from, IC devices 136a and / or 136b. Conductive structures 144a and 144b may include trenches, metallization layers, conductive traces, vias, interconnects, and / or combinations of other types of conductive structures. Conductive structures 144a and 144b may each include one or more conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials.

[0105] IC die 104 may further include a sealing ring structure 146a surrounding the conductive structure 144a to protect IC die 104 from physical and / or electrical damage during the die-cutting operation from the wafer. The sealing ring structure 146a further provides protection against moisture ingress and other contaminants. IC die 106 may similarly include a sealing ring structure 146b surrounding the conductive structure 144b to protect IC die 106 from physical and / or electrical damage during the die-cutting operation from the wafer. The sealing ring structure 146b further provides protection against moisture ingress and other contaminants.

[0106] IC die 104 may include a passivation layer 148a over and / or on a plurality of alternating dielectric layers (e.g., ILD layers 140a and ESL layers 142a) to passivate the interconnect layers of IC die 104. Similarly, IC die 106 may include a passivation layer 148b over and / or on a plurality of alternating dielectric layers (e.g., ILD layers 140b and ESL layers 142b) to passivate the interconnect layers of IC die 106.

[0107] A metal pad structure 150a may be included above and / or on the conductive structure 144a, and a metal pad structure 152a may be included above and / or on the sealing ring structure 146a. A metal pad structure 150b may be included above and / or on the conductive structure 144b, and a metal pad structure 152b may be included above and / or on the sealing ring structure 146b. The metal pad structures 150a and 152a may extend through the passivation layer 148a, and another passivation layer 154a may be included above the metal pad structures 150a and 152a. A dielectric layer 156 may be included on the passivation layer 154a. The metal pad structures 150b and 152b may extend through the passivation layer 148b, and another passivation layer 154b may be included above the metal pad structures 150b and 152b.

[0108] The passivation layers 148a, 148b, 154a, 154b and the dielectric layer 156 may each comprise an oxide (e.g., silicon oxide (SiO2)). x (and / or another oxide material), silicon-free glass (USG), borosilicate glass (BSG), fluorosilicone glass (FSG), tetraethyl orthosilicate (TEOS), silsesquioxane (HSQ), silicon nitride (Si) x N y The dielectric material may be silicon carbide (SiC), silicon oxynitride (SiON), or another suitable dielectric material. In some embodiments, passivation layers 148a, 148b, 154a and / or 154b, and / or dielectric layer 156 comprise an ELK dielectric material having a dielectric constant of less than about 2.5.

[0109] Metal pad structures 150a, 152a, 150b, and / or 152b may each comprise aluminum (Al), aluminum-copper (AlCu), copper (Cu), and / or another conductive material. Metal pad structures 150a and 152a may correspond to the redistribution layer (RDL) of IC die 104, and metal pad structures 150b and 152b may correspond to the RDL of IC die 106. In some embodiments, sealing ring structures 146a and 146b may further comprise pads 158a and 158b, respectively. Alternatively, bonding pads 158a and / or 158b may be omitted. Bonding pads 158a and 158b may each comprise tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials.

[0110] In some embodiments, the IC die 104 further includes a through-substrate interconnect structure 160 extending through the substrate 132a of the IC die 104. The through-substrate interconnect structure 160 may include a through-substrate via (TSV) or another type of through-substrate interconnect. The through-substrate interconnect structure 160 electrically connects the conductive structure 144a of the IC die 104 to the connection structure 162 of the device package 102. The through-substrate interconnect structure 160 includes a conductive material, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, and other examples of conductive materials. The through-substrate interconnect structure 160 may include vias, pillars, columns, and / or another type of elongated conductive structure extending between the front side of the substrate 132a of the IC die 104 (the side of the substrate 132a that includes the conductive structure 144a) and the rear side of the substrate 132b of the IC die 104 perpendicular to the front side.

[0111] Connection structure 162 may include solder balls, solder bumps, contact pads (e.g., land grid array (LGA) pads), contact pins (e.g., pin grid array (PGA) pins), under bump metallization (UBM) connections, microbumps, ball grid array (BGA) balls, controlled collapse chip connection (C4) bumps, and / or other types of connection structures that enable device package 102 to be connected to a substrate or plug, and other examples.

[0112] like Figure 1B As further shown, a dielectric plug 164 may be included above and / or over the grating coupler 108 in the IC die 104. The dielectric plug 164 may extend through the passivation layer 148a, the ILD layer 140a, the ESL 142a, and / or the ILD layer 134a. In some embodiments, the dielectric plug 164 extends partially into the substrate 132a. In some embodiments, the dielectric plug 164 extends into the ILD layer 134a but does not extend through it. In these embodiments, a portion of the ILD layer 134a remains between the bottom of the dielectric plug 164 and the substrate 132a. The dielectric plug 164 may provide an optical transmission path for incident light 166 (e.g., an optical signal) to propagate via the IC die 104 to the underlying grating coupler 108. The dielectric plug 164 may include one or more dielectric materials, such as silicon oxide (SiO2). x ), silicon nitride (Si x Ny Silicon carbide (SiC), silicon oxynitride (SiON), and / or another suitable dielectric material. In some embodiments, the dielectric plug 164 comprises a polymer material or a molding compound.

[0113] like Figure 1B As further shown, a reflector structure 168 is included on the sidewall of the dielectric plug 164. The reflector structure 168 may laterally surround the dielectric plug 164 such that the reflector structure 168 is a closed-loop conformal layer extending completely around the periphery of the dielectric plug 164. The reflector structure 168 may include a thin film layer (e.g., a conformal metal thin film layer) comprising one or more reflective materials, such that the reflector structure 168 reflects incident light 166 in the dielectric plug 164 toward the underlying grating coupler 108, rather than diffusing or scattering the incident light 166 into the surrounding dielectric layer. Furthermore, the reflective material of the reflector structure 168 enables the reflector structure 168 to block unwanted incident light 166 intended to be directed toward the adjacent grating coupler 108, thereby reducing optical crosstalk in the IC die 104. Examples of such materials include tantalum (Ta), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), another reflective metal, tantalum nitride (TaN), titanium nitride (TiN), and / or another reflective material.

[0114] In some embodiments, a liner is included between the reflector structure 168 and the surrounding dielectric layer. The liner may include a barrier liner, an adhesive liner, and / or another type of liner, and may include materials such as tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples of materials.

[0115] Figure 1C The diagram shows a detailed view of the dielectric plug 164 above the grating coupler 108 and the associated reflector structure 168. (See attached diagram.) Figure 1C As shown, in some embodiments, the substrate 132a of the IC die 104 includes an SOI substrate, which includes a semiconductor layer 170 and a buried dielectric layer (e.g., a buried oxide (BOX) layer) 172 on the semiconductor layer 170. Another semiconductor layer may have been initially included on the buried dielectric layer 172 and subsequently etched to define the grating coupler 108. Another dielectric layer 174 may be formed around and / or over the grating coupler 108 on the buried dielectric layer 172. Alternatively, the semiconductor layer 170 may be omitted from the IC die 104 because it can be removed during back-side processing after the formation of the grating coupler 108.

[0116] Figure 1C Further illustrations show various example dimensions of IC die 104. For example... Figure 1CAs shown, example dimension D1 includes the bottom lateral width of dielectric plug 164, and another example dimension D2 includes the top lateral width of dielectric plug 164. In some embodiments, dimension D2 is larger than dimension D1, such that the sidewalls of dielectric plug 164 (and the reflector structure 168 on the sidewalls of dielectric plug 164) are not perpendicular, but at an angle of less than 90 degrees (in Figure 1C The orientation is represented as dimension D3. This results in the dielectric plug 164 having a tapered cross-sectional profile, wherein the lateral width of the dielectric plug 164 decreases from the top to the bottom of the dielectric plug 164. Furthermore, this causes the reflector structure 168 to be angled away from the grating coupler 108 from the bottom to the top of the reflector structure 168, enabling the reflector structure 168 to more effectively capture and redirect optical signals toward the grating coupler 108. However, in other embodiments, the angle between the sidewall of the dielectric plug 164 and the sidewall of the reflector structure 168 may be approximately 90 degrees.

[0117] In some embodiments, the outward angle (dimension D3) of the sidewalls of the dielectric plug 164 and the sidewalls of the reflector structure 168 is based on the angle of the incident light 166 to be received at the grating coupler 108 (in Figure 1C (This is represented as dimension D4). For example, the angle of the incident light 166 (e.g., relative to the surface of the substrate 132a) may not be 90 degrees, and the outward angle (dimension D3) of the sidewalls of the dielectric plug 164 and the sidewalls of the reflector structure 168 may be approximately equal to the angle of the incident light 166. However, other angles of the outward angle (dimension D3) of the sidewalls of the dielectric plug 164 and the sidewalls of the reflector structure 168 are also within the scope of this disclosure.

[0118] The bottom width (dimension D1) of the dielectric plug 164 can be based on the dimensions of the underlying grating coupler 108. For example, the bottom width (dimension D1) of the dielectric plug 164 can be based on the lateral width (in the lateral direction of the underlying grating coupler 108). Figure 1C (represented as dimension D5). Specifically, the bottom width (dimension D1) of the dielectric plug 164 can be adjusted such that the underlying grating coupler 108 fits within the periphery of the bottom of the dielectric plug 164, so that the light propagation path from the incident light 166 to the grating coupler 108 is not blocked by the reflector structure 168 surrounding the dielectric plug 164. Therefore, the bottom width of the dielectric plug 164 can be greater than the lateral width of the grating coupler 108 (e.g., D1 > D5). However, other dimensions of the bottom width of the dielectric plug 164 are also within the scope of this disclosure.

[0119] like Figure 1C As further shown, the dielectric plug 164 may have in Figure 1CThe vertical (z-direction) height is represented by dimension D6. In some embodiments, the bottom width (dimension D1) and top width (dimension D2) of the dielectric plug 164 may be based on the outward angle (dimension D3) of the sidewalls of the dielectric plug 164 and the sidewalls of the reflector structure 168, may be based on the angle of the incident light 166 (dimension D4), and / or may be based on the vertical (z-direction) height (dimension D6) of the dielectric plug 164, and other examples.

[0120] As shown above, Figures 1A to 1C Provided as an example only. Other examples may be provided. Figures 1A to 1C The descriptions differ from those in the text.

[0121] Figures 2A to 2D The illustration shows an example top view of the dielectric plug 164 and associated reflector structure 168 described herein. Although Figures 2A to 2D Various examples are provided, but other example top views of the dielectric plug 164 and / or reflector structure 168 are also within the scope of this disclosure. Furthermore, the IC die 104 may include a plurality of dielectric plugs 164 and / or reflector structures 168 having combinations of example top views.

[0122] like Figure 2A As shown, the example top-view shape 200 includes an approximately circular top-view shape, wherein both the top 202 and the bottom 204 of the dielectric plug 164 have approximately circular top-view shapes. The width (dimension D1) of the bottom 204 of the dielectric plug 164 may be smaller than the width (dimension D2) of the top 202 of the dielectric plug 164. The reflector structure 168 may conform to the top-view shape 200 and may have a closed-loop hollow circular top-view shape (or annular).

[0123] like Figure 2B As shown, example top view shape 206 includes a polygonal top view shape, wherein the top 202 and bottom 204 of dielectric plug 164 both have approximately square top view shapes. Alternatively, the top 202 and / or bottom 204 of dielectric plug 164 may have another polygonal top view shape, such as a rectangular top view shape, a triangular top view shape, and / or a hexagonal top view shape, and other examples. The width (dimension D1) of the bottom 204 of dielectric plug 164 may be smaller than the width (dimension D2) of the top 202 of dielectric plug 164. Reflector structure 168 may conform to top view shape 200 and may have a closed-loop hollow polygonal top view shape (e.g., hollow square, hollow rectangle).

[0124] like Figure 2C and Figure 2D As shown, the dielectric plug 164 may have a composite top view shape. The associated reflector structure 168 around the dielectric plug 164 may also conform to the composite top view shape.

[0125] For example, Figure 2C The top view 208 shown includes a polygonal top view of the top 202 of the dielectric plug 164 and an approximately circular top view of the bottom 204 of the dielectric plug 164. The shape of the dielectric plug 164 may transition along the height of the dielectric plug 164 between the polygonal top view of the top 202 of the dielectric plug 164 and the approximately circular top view of the bottom 204 of the dielectric plug 164. The width (dimension D1) of the bottom 204 of the dielectric plug 164 may be smaller than the width (dimension D2) of the top 202 of the dielectric plug 164.

[0126] As another example, Figure 2D The top view shape 210 shown includes an approximately circular top view shape at the top 202 of the dielectric plug 164 and a polygonal top view shape at the bottom 204 of the dielectric plug 164. The shape of the dielectric plug 164 may transition along the height of the dielectric plug 164 between the approximately circular top view shape at the top 202 of the dielectric plug 164 and the polygonal top view shape at the bottom 204 of the dielectric plug 164. The width (dimension D1) of the bottom 204 of the dielectric plug 164 may be smaller than the width (dimension D2) of the top 202 of the dielectric plug 164.

[0127] As shown above, Figures 2A to 2D Provided as an example only. Other examples may be provided. Figures 2A to 2D The descriptions differ from those in the text.

[0128] Figures 3A to 3L This is a schematic diagram of an exemplary embodiment 300 for forming the IC die 104 described herein. While the processing operations of the exemplary embodiment 300 are illustrated and described in conjunction with the formation of the IC die 104 described herein, one or more of the processing operations of the exemplary embodiment 300 may be performed to form another IC die, such as IC die 106, shown herein. In some embodiments, in conjunction with Figures 3A to 3L One or more of the semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, wafer / die transport tools, and / or another type of semiconductor processing tool.

[0129] Transfer to Figure 3A A substrate 132a is provided for the IC die 104. The substrate 132a may be provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, and may be provided as an SOI wafer and / or another type of semiconductor workpiece. In some embodiments, the IC die 104 may be placed on a carrier substrate 302 for processing. Alternatively, the substrate 132a may serve as a carrier for the IC die 104.

[0130] like Figure 3BAs shown, IC device 136a may be formed in and / or on substrate 132a of IC die 104. One or more semiconductor processing tools may be used to form one or more portions of IC device 136a. For example, deposition tools may be used to perform various deposition operations to deposit layers and / or structures of IC device 136a, and / or deposit photoresist layers for etching portions of substrate 132a and / or deposited layers. As another example, exposure tools may be used to expose the photoresist layer to form a pattern in the photoresist layer. As another example, development tools may be used to develop the pattern in the photoresist layer. As another example, etching tools may be used to etch portions of substrate 132a and / or deposited layers to form IC device 136a. As another example, planarization tools may be used to planarize portions of IC device 136a. As another example, electroplating tools may be used to deposit metal structures and / or layers of IC device 136a.

[0131] like Figure 3B As shown, the grating coupler 108 may be formed in and / or on the substrate 132a of the IC die 104. One or more semiconductor processing tools may be used to form the grating coupler 108. For example, a patterned layer may be formed (e.g., using a deposition tool) over a semiconductor layer (e.g., a silicon (Si) layer, germanium (Ge) layer) of the substrate 132a, and used to etch (e.g., using an etching tool) to form the grating coupler 108 from the semiconductor layer. Alternatively, a recess may be formed in the substrate 132a (e.g., using an etching tool), and a deposition tool may be used to deposit (e.g., by epitaxy, chemical vapor deposition (CVD)) material of the grating coupler 108 in the recess. This material may be etched to define the grating of the grating coupler 108. A dielectric layer 174 may be deposited over the grating coupler 108.

[0132] like Figure 3B As further shown, an ILD layer 134a is deposited over and / or on the substrate 132a, over and / or on the IC device 136a, and / or over and / or on the grating coupler 108 using a deposition tool. The deposition tool can be used to deposit the ILD layer 134a using physical vapor deposition (PVD), atomic layer deposition (ALD), CVD, oxidation, and / or another suitable deposition technique. In some embodiments, a planarization tool, such as a chemical mechanical planarization (CMP) operation, can be used to perform a planarization operation after depositing the ILD layer 134a.

[0133] like Figure 3B Further shown, contacts 138a of the IC device 136a may be formed through the ILD layer 134a. Contacts 138a may be formed in grooves within the ILD layer 134a. In some embodiments, the ILD layer 134a is etched using a pattern in a photoresist layer to form the grooves. In these embodiments, a photoresist layer may be formed on the ILD layer 134a using a deposition tool. An exposure tool may be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch a dielectric layer based on the pattern to form the grooves. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of the ILD layer 134a to form grooves.

[0134] Deposition tools can be used to deposit material for contact 138a in a groove using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The material for contact 138a may be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the material for contact 138a is deposited on the seed layer. In some embodiments, after depositing contact 138a, a planarization operation (e.g., CMP operation) is performed using a planarization tool to planarize contact 138a such that the top of contact 138a is approximately coplanar with the top of ILD layer 134a.

[0135] like Figure 3C As shown, a first portion of the interconnect layer of IC die 104 is formed on ILD layer 134a. One or more deposition tools are used to deposit alternating layers of ILD layers 140a and ESL 142a in the first portion of the interconnect layer of IC die 104. In this manner, ILD layers 140a and ESL 142a can be disposed in IC die 104 in the z-direction. One or more deposition tools can be used to deposit each of ILD layers 140a and each of ESL 142a using PVD technology, ALD technology, CVD technology, oxidation technology, and / or another suitable deposition technology. In some embodiments, after depositing ILD layers 140a and / or ESL 142a, planarization tools can be used to planarize ILD layers 140a and / or ESL 142a.

[0136] like Figure 3CAs further shown, various operations can be performed using deposition tools, exposure tools, development tools, etching tools, planarization tools, electroplating tools, and / or other semiconductor processing tools to form a first portion of the conductive structure 144a and a first portion of the sealing ring structure 146a in a first portion of the interconnect layer of the IC die 104. The first portion of the conductive structure 144a and the sealing ring structure 146a may be included in the ILD layer 140a and / or ESL 142a.

[0137] The first portion of the conductive structure 144a and the sealing ring structure 146a may be formed in a groove in one or more ILD layers 140a and / or one or more ESLs 142a. In some embodiments, the ILD layers 140a and ESLs 142a are etched using a pattern in the photoresist layer to form the groove. In these embodiments, a photoresist layer may be formed on the topmost ILD layer 140a using a deposition tool. The photoresist layer may be exposed to a radiation source using an exposure tool to pattern the photoresist layer. A development tool may be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool may be used to etch the ILD layers 140a and ESLs 142a based on the pattern to form the groove. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique to pattern-based etching of ILD layers 140a and ESL 142a to form grooves.

[0138] Deposition tools can be used to deposit the material of the conductive structure 144a and the first portion of the sealing ring structure 146a in a groove using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. The material of the conductive structure 144a and the first portion of the sealing ring structure 146a can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the material of the conductive structure 144a and the first portion of the sealing ring structure 146a is deposited on the seed layer. In some embodiments, a planarization tool is used to perform a planarization operation (e.g., a CMP operation) to planarize the conductive structure 144a and the first portion of the sealing ring structure 146a.

[0139] like Figure 3D As shown, the through-substrate interconnect structure 160 is formed through a first portion of the interconnect layer and enters the substrate 132a. To form the through-substrate interconnect structure 160, a groove is formed through the first portion of the interconnect layer and enters a portion of the substrate 132a.

[0140] In some embodiments, a pattern in the photoresist layer is used to etch the ILD layer 140a and ESL 142a, ILD layer 134a, and substrate 132a of a first portion of the interconnect layer to form a groove. In these embodiments, a photoresist layer can be formed on the topmost ESL 142a using a deposition tool. An exposure tool can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching tool can be used to etch the ILD layer 140a and ESL 142a, ILD layer 134a, and substrate 132a of the first portion of the interconnect layer based on the pattern to form a groove. In some embodiments, the etching operation includes a plasma etching operation, a wet chemical etching operation, and / or another type of etching operation. In some embodiments, a photoresist removal tool can be used to remove the remaining portions of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based groove formation.

[0141] Deposition tools can be used to deposit through-substrate interconnect structures 160 using CVD, PVD, ALD, electroplating, and / or other suitable deposition techniques. The through-substrate interconnect structure 160 can be deposited in one or more deposition operations. In some embodiments, a seed layer is first deposited, and the through-substrate interconnect structure 160 is deposited on the seed layer. In some embodiments, one or more liners (e.g., barrier liners, adhesion liners) can be first deposited in a trench, and the through-substrate interconnect structure 160 can be deposited on one or more liners in the trench. In some embodiments, after depositing the through-substrate interconnect structure 160, a planarization operation (e.g., CMP operation) is performed using planarization tools to planarize the through-substrate interconnect structure 160.

[0142] like Figure 3E As shown, a second portion of the interconnect layer that can form the IC die 104 is illustrated. The second portion forming the interconnect layer may include components that can be bonded to… Figure 3C The same manner forms additional portions of the ILD layer 140a, additional ESL 142a, additional conductive structure 144a, and / or sealing ring structure 146a.

[0143] like Figure 3F As shown, a passivation layer 148a can be deposited, a metal pad structure 150a can be formed on one or more of the conductive structures 144a, and one or more metal pad structures 152a can be formed on the sealing ring structure 146a.

[0144] In some embodiments, the deposition tool can be used to deposit conductive material layers for metal pad structures 150a and 152a using CVD, PVD, ALD, electroplating, and / or another suitable deposition technique. A patterned layer can be used to etch the conductive material layers to define the metal pad structures 150a and 152a. Alternatively, a patterned layer can be deposited, grooves can be formed in the patterned layer, material for the metal pad structures 150a and 152a can be deposited in the grooves, and the patterned layer can then be removed. The deposition tool can be used to deposit passivation layer 148a using CVD, PVD, ALD, oxidation, and / or another suitable deposition technique.

[0145] like Figure 3G As shown, one or more recesses 304 may be formed in the IC die 104. For example, a recess 304 may be formed above the grating coupler 108. The recess 304 may be formed through (and may extend through) the passivation layer 148a, the ILD layer 140a, the ESL 142a, and / or the ILD layer 134a. In some embodiments, the recess 304 extends partially into the substrate 132a. In some embodiments, the recess 304 extends into the ILD layer 134a but does not extend through it. In these embodiments, a portion of the ILD layer 134a remains between the bottom of the recess 304 and the substrate 132a.

[0146] In some embodiments, the passivation layer 148a, ILD layer 140a, ESL 142a, and / or ILD layer 134a are etched using a pattern in the photoresist layer to form a groove 304. In these embodiments, the photoresist layer can be formed on the passivation layer 148a using a deposition tool (e.g., using spin-on coating and / or another suitable deposition technique). The photoresist layer can be patterned by exposing it to a radiation source using an exposure tool. A development tool can be used to develop and remove portions of the photoresist layer to expose the pattern. The passivation layer 148a, ILD layer 140a, ESL 142a, and / or ILD layer 134a can be etched based on the pattern using an etching tool to form the groove 304. In some embodiments, the etching operation includes a dry etching operation (e.g., a plasma-based etching operation, a gas-based etching operation), a wet chemical etching operation, and / or another type of etching operation. An etching operation can be performed to etch the passivation layer 148a, ILD layer 140a, ESL 142a, and / or ILD layer 134a to form non-vertical (or tapered) sidewalls of the recess 304. In other words, the top width (e.g., dimension D2) of the recess 304 is greater than the bottom width (e.g., dimension D1) of the recess 304, resulting in a tapered profile of the recess 304. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique).

[0147] like Figure 3H As shown, the reflector structure 168 is formed on the sidewall of the recess 304. In some embodiments, the reflector structure 168 is also formed on the bottom surface of the recess 304, and then etched to remove a portion of the reflector structure 168 from the bottom surface of the recess 304 so that the portion does not interfere with the transmission of optical signals to the underlying grating coupler 108.

[0148] Deposition tools can be used to conformally deposit the reflector structure 168 using CVD and / or ALD techniques. In this manner, the reflector structure 168 can conform to the profile of the sidewalls of the recess 304, such that the reflector structure 168 formed in the recess 304 is not perpendicular, but angled away from (e.g., angled away from the bottom of the recess 304 to the bottom of the recess 304) the grating coupler 108 lying beneath the recess 304. In some embodiments, another deposition technique, such as PVD and / or electroplating, is used to deposit the reflector structure 168.

[0149] In some embodiments, a liner is first deposited on the sidewall of the groove 304, and then a reflector structure 168 is deposited on the liner. The liner may include a barrier liner, an adhesive liner, and / or another type of liner, and may include materials such as tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples of materials.

[0150] like Figure 3I As shown, the remaining area in the groove 304 is filled with the material of the passivation layer 154a to form a dielectric plug 164 in the groove 304. The dielectric plug 164 is formed on the reflector structure 168 in the groove 304 such that the reflector structure 168 is located between the sidewall of the dielectric plug 164 and the surrounding dielectric layers (e.g., passivation layer 148a, ILD layer 140a, ESL 142a, and / or ILD layer 134a). Material is also deposited on the groove 304 to form a passivation layer 154a on the dielectric plug 164. The passivation layer 154a may cover the metal pad structures 150a and / or 152a.

[0151] Deposition tools can be used to deposit the dielectric material of the passivation layer 154a and the dielectric material of the dielectric plug 164 using PVD, ALD, CVD, oxidation, and / or other suitable deposition techniques. The dielectric material of the passivation layer 154a and the dielectric material of the dielectric plug 164 can be deposited in one or more deposition operations. In some embodiments, a planarization tool can be used to perform a planarization operation (e.g., CMP operation) after the deposition of the passivation layer 154a to planarize the passivation layer 154a.

[0152] like Figure 3JAs shown, dielectric layer 156a can be deposited over IC die 104. Deposition tools can be used to deposit dielectric layer 156a using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. Dielectric layer 156a can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., CMP operation) can be performed after depositing dielectric layer 156a using planarization tools to planarize dielectric layer 156a.

[0153] like Figure 3K As shown, a dielectric filling layer 120a can be used to fill the area surrounding the IC die 104. Deposition tools can be used to deposit the dielectric filling layer 120a using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The dielectric filling layer 120a can be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., CMP operation) can be performed after the deposition of the dielectric filling layer 120a to planarize the IC die 104.

[0154] like Figure 3L As shown, a bonding dielectric layer 112 may be formed above and / or on the IC die 104 (including above and / or on the dielectric layer 156a, and / or above and / or on the dielectric filler layer 120a). A bonding structure 116 may be formed on the IC die 104. The bonding structure 116 may rest on one or more metal pad structures 150a and may be electrically coupled to them.

[0155] Deposition tools can be used to deposit the bonding dielectric layer 112 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. In some embodiments, planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize the bonding dielectric layer 112 after deposition.

[0156] Deposition tools can be used to deposit the bonding structure 116 using PVD, ALD, CVD, electroplating, and / or another suitable deposition technique. In some embodiments, a liner is first deposited, followed by the deposition of the bonding structure 116 on the liner. The liner may include a barrier liner, an adhesive liner, and / or another type of liner, and may include materials such as tantalum nitride (TaN) and / or titanium nitride (TiN), and other examples of materials.

[0157] In some embodiments, a bonding dielectric layer 112 is first deposited, a groove is formed through the bonding dielectric layer 112 and through the dielectric layer 156a to reach one or more underlying metal pad structures 150a, and then a bonding structure 116 is formed in the groove. In some embodiments, the bonding structure 116 is first formed, and a bonding dielectric layer 112 is formed around the bonding structure 116.

[0158] As shown above, Figures 3A to 3L Provided as an example only. Other examples may be provided. Figures 3A to 3L The descriptions differ from those in the text.

[0159] Figures 4A to 4G This is a schematic diagram of an example embodiment 400 forming the device package 102 described herein. In some embodiments, combined with Figures 4A to 4G One or more of the semiconductor processing operations described may be performed using one or more semiconductor processing tools, such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools, and / or another type of semiconductor processing tool.

[0160] like Figure 4A and Figure 4B As shown, IC die 106 is bonded to IC die 104 such that IC die 104 and IC die 106 are stacked and vertically configured (e.g., in the z-direction) in device package 102. IC dies 104 and 106 may be bonded at bonding interface 110.

[0161] In some embodiments, IC dies 104 and 106 are joined using a bonding tool by forming a dielectric-to-dielectric bond between a bonding dielectric layer 112 on IC die 104 and a bonding dielectric layer 114 on IC die 106. In some embodiments, IC dies 104 and 106 are joined using a bonding tool by forming a metal-to-metal bond between a bonding structure 116 on IC die 104 and a bonding structure 118 on IC die 106. In some embodiments, IC dies 104 and 106 are joined using a bonding tool by forming a combination of dielectric-to-dielectric and metal-to-metal bonds. In some embodiments, IC dies 104 and 106 are joined using a bonding tool by forming a dielectric-to-metal bond between IC dies 104 and 106.

[0162] IC die 106 can be laterally positioned (e.g., in the x-direction and y-direction) above IC die 104, such that the portion of IC die 104 containing the grating coupler 108, associated dielectric plug 164, and reflector structure 168 extends laterally outward from IC die 106. In other words, IC die 106 can be laterally positioned above IC die 104 such that IC die 106 is not located above the portion of IC die 104 containing the grating coupler 108, associated dielectric plug 164, and reflector structure 168. This provides an unobstructed optical propagation path for optical signals to IC die 104.

[0163] like Figure 4CAs shown, the area surrounding IC die 106, including the area above the portion of IC die 104 where the grating coupler 108 and associated dielectric plug 164 and reflector structure 168 are located, is filled with a dielectric filler layer 120b. Deposition tools can be used to deposit the dielectric filler layer 120b using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. The dielectric filler layer 120b can be deposited in one or more deposition operations. Planarization tools can be used to perform planarization operations (e.g., CMP operations) to planarize the dielectric filler layer 120b and / or the substrate 132b of IC die 106 such that the dielectric filler layer 120b and the substrate 132b of IC die 106 are approximately coplanar.

[0164] like Figure 4D As shown, passivation layers 126-130 are formed or provided on IC die 106. Deposition tools can be used to deposit passivation layers 126-130 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. Passivation layers 126-130 may be deposited in one or more deposition operations. In some embodiments, a planarization operation (e.g., CMP operation) may be performed after depositing passivation layers 126-130 using a planarization tool to planarize the passivation layers 126-130. Additionally and / or otherwise, one or more of passivation layers 126-130 may be dispersed onto IC die 106. Additionally and / or otherwise, passivation layers 126-130 may be laminated onto or bonded to device package 102.

[0165] like Figure 4E As shown, the device package 102 is flipped, and one or more operations can be performed to remove the carrier substrate 302 (if used) from the device package 102. In some embodiments, the carrier substrate 302 is debonded from the device package 102 by a thermal operation to change the adhesive properties of the bonding layer used to bond the device package 102 to the carrier substrate 302. The bonding layer is irradiated and heated using an ultraviolet (UV) laser, a carbon dioxide (CO2) laser, or an infrared (IR) laser, and other example energy sources, until the adhesive properties of the bonding layer decrease. The carrier substrate 302 is then separated from the bonding layer entity and removed from the device package 102. Additionally and / or otherwise, the carrier substrate 302 and / or the bonding layer can be removed by etching and / or planarization.

[0166] like Figure 4F As shown, planarization operations (e.g., CMP operations, wafer polishing operations) can be performed using planarization tools or wafer polishing tools to remove material from the back side of the substrate 132a of the IC die 104, so that the (multiple) through-substrate interconnect structures 160 are exposed via the back side of the substrate 132a.

[0167] like Figure 4G As shown, passivation layers 122 and 124 are formed on the back side of substrate 132a of IC die 104. Deposition tools can be used to deposit passivation layers 122 and 124 using PVD, ALD, CVD, oxidation, and / or another suitable deposition technique. Passivation layers 122 and 124 may be deposited in one or more deposition operations. In some embodiments, a planarization tool may be used to perform a planarization operation (e.g., CMP operation) to planarize passivation layers 122 and 124 after deposition. Additionally and / or otherwise, passivation layers 122 and 124 may be dispersed onto IC die 104. Interconnect structure 162 may be further attached to device package 102 such that interconnect structure 162 is electrically coupled to (a plurality of) through-substrate interconnect structures 160.

[0168] As shown above, Figures 4A to 4G Provided as an example only. Other examples may be provided. Figures 4A to 4G The descriptions differ from those in the text.

[0169] Figure 5A and Figure 5B This is a schematic diagram of an example embodiment 500 of the device package 102 described herein. Figure 5A and Figure 5B Example embodiment 500 of the device package 102 shown is similar to Figures 1A to 1C The example embodiment 100 of the device package 102 shown differs in that, in the example embodiment 500 of the device package 102, one or more non-active dies 502 may be included above and / or on the IC die 104, above a region of the IC die 104 extending outwardly from the side of the IC die 106.

[0170] The passive die 502 may each include a die that is a passive component and / or a die that does not perform electrical and / or processing functions of the device package 102. Examples of passive dies 502 include dummy dies, integrated passive device (IPD) dies, dielectric structures (e.g., thick films), and / or other types of passive dies. A passive die may also be referred to as an insert die, a fill die, and / or another type of die that does not perform electrical and / or processing functions of the device package 102. IPD dies may include capacitors or capacitor dies, resistors or resistor dies, inductors or inductor dies, or combinations thereof.

[0171] The non-active die 502 and the IC die 106 may be in physical contact (e.g., in physical contact with each other), or they may be separated by a gap 504, such as... Figure 5A As shown in the top view. Figure 5BAs shown in the cross-sectional view along line AA, the passive die 502 may be positioned on one or more of the dielectric plugs 164 above the plurality of grating couplers 108 of the IC die 104. Optical signals may propagate via the passive die 502 toward the plurality of grating couplers 108 through the plurality of dielectric plugs 164. As the optical signal propagates from the IC die 104 to the plurality of grating couplers 108, the plurality of reflector structures 168 on the sidewalls of the plurality of dielectric plugs 164 provide limitation on the increase of the optical signal.

[0172] In some embodiments, a non-active die 502 is bonded to a bonding dielectric layer 112 of an IC die 104. In some embodiments, the non-active die 502 is formed or deposited on the IC die 104. In some embodiments, the IC die 104 includes an additional bonding structure 116 beneath the non-active die 502, and one or more reflector structures 602 are bonded to one or more bonding structures 116 of the IC die 104.

[0173] As mentioned above, Figure 5A and Figure 5B Provided as an example only. Other examples may be provided. Figure 5A and Figure 5B The descriptions differ from those in the text.

[0174] Figure 6 This is a schematic diagram of an example embodiment 600 of the device package 102 described herein. For example... Figure 6 As shown, Figure 6 The example embodiment 600 of the device package 102 shown is similar to Figure 5A and Figure 5B The example embodiment 500 of the device package 102 shown includes one or more non-active dies 502 on and / or above the IC die 104.

[0175] However, as Figure 6As shown, in an example embodiment 600 of the device package 102, the non-active die 502 includes one or more reflector structures 602 extending through at least a portion of the non-active die 502. The reflector structures 602 of the non-active die 502 may be positioned over a reflector structure 168 surrounding a dielectric plug 164 in the IC die 104. In some embodiments, the reflector structure 602 may be aligned with the reflector structure 168 in the x and / or y directions such that the reflector structure 602 overlaps with the reflector structure 168. In some embodiments, the reflector structure 602 may be partially aligned with the reflector structure 168 in the x and / or y directions such that one or more segments or portions of the reflector structure 602 overlap with one or more segments or portions of the reflector structure 168. In some embodiments, the reflector structure 602 may be laterally offset relative to the reflector structure 168 in the x and / or y directions.

[0176] In some embodiments, reflector structure 602 may include a closed-loop structure similar to reflector structure 168. Reflector structure 602 may be formed by forming grooves in non-active grains 502 and depositing material of reflector structure 602 in the grooves.

[0177] As mentioned above, Figure 6 Provided as an example only. Other examples may be provided. Figure 6 The descriptions differ from those in the text.

[0178] Figure 7 This is a schematic diagram of an example embodiment 700 of the device package 102 described herein. For example... Figure 7 As shown, Figure 7 The example embodiment 700 of the device package 102 shown is similar to Figure 6 The example embodiment 600 of the device package 102 shown includes one or more non-active dies 502 above and / or on (above a region of the IC die 104) the IC die 104, and the non-active die 502 includes one or more reflector structures 602.

[0179] However, as Figure 7 As shown, in example embodiment 700 of device package 102, reflector structure 602 extends completely through the non-active die 502 in the z-direction. In other words, the tops of (a plurality of) reflector structures 602 may be approximately coplanar with the tops of the non-active die 502. Additionally and / or, as... Figure 7 As shown, the z-direction height of the inactive die 502 may be smaller than the z-direction height of the IC die 106. Therefore, the dielectric filling layer 120b may be included on the top of the inactive die 502 and around the sides of the inactive die 502.

[0180] As mentioned above, Figure 7Provided as an example only. Other examples may be provided. Figure 7 The descriptions differ from those in the text.

[0181] Figure 8 This is a schematic diagram of an example embodiment 800 of the device package 102 described herein. (See attached diagram.) Figure 8 As shown, Figure 8 The example embodiment 800 of the device package 102 shown is similar to Figure 7 The example embodiment 700 of the device package 102 shown includes one or more non-active dies 502 above and / or on the IC die 104, and the non-active die 502 includes one or more reflector structures 602.

[0182] like Figure 8 Further illustrated, an example embodiment 800 of the device package 102 further includes another passive die 802 on and / or above the passive die 502. The passive dies 502 and 802 may be stacked in the z-direction and vertically configured within the device package 102. In some embodiments, the passive dies 502 and 802 are bonded together (e.g., in a dielectric-to-dielectric bond, a metal-to-dielectric bond, or a metal-to-metal bond). In some embodiments, the passive die 802 is formed on the passive die 502.

[0183] In some embodiments, the passive dies 502 and 802 may include different dielectric materials that allow the refractive indices of the passive dies 502 and 802 to be tuned to reduce the reflection of optical signals away from the IC die 104. In some embodiments, the passive dies 502 and 802 include the same dielectric material.

[0184] As mentioned above, Figure 8 Provided as an example only. Other examples may be provided. Figure 8 The descriptions differ from those in the text.

[0185] Figure 9 This is a schematic diagram of an example embodiment 900 of the device package 102 described herein. (See attached diagram.) Figure 9 As shown, Figure 9 The example embodiment 900 of the device package 102 shown is similar to Figure 8 The example embodiment 800 of the device package 102 shown includes a non-active die 802 on a non-active die 502 above and / or on the IC die 104, and the non-active die 502 includes one or more reflector structures 602.

[0186] like Figure 9Further illustrated, an example embodiment 900 of the device package 102 may further include an additional reflector structure 902 in the non-active die 802. The reflector structure 902 may extend through at least a portion of the non-active die 802. The reflector structure 902 of the non-active die 802 may be positioned above the reflector structure 602 in the non-active die 502. In some embodiments, the reflector structure 902 may be aligned with the reflector structure 602 in the x and / or y directions such that the reflector structure 902 overlaps with the reflector structure 602. In some embodiments, the reflector structure 902 may be partially aligned with the reflector structure 602 in the x and / or y directions such that one or more segments or portions of the reflector structure 902 overlap with one or more segments or portions of the reflector structure 602. In some embodiments, the reflector structure 902 may be laterally offset relative to the reflector structure 602 in the x and / or y directions.

[0187] In some embodiments, reflector structure 902 may include a closed-loop structure similar to reflector structure 168 and / or similar to reflector structure 602. Reflector structure 902 may be formed by forming grooves in non-active grains 802 and depositing material of reflector structure 902 in the grooves.

[0188] As mentioned above, Figure 9 Provided as an example only. Other examples may be provided. Figure 9 The descriptions differ from those in the text.

[0189] Figure 10 This is a schematic diagram of an example embodiment 1000 of the device package 102 described herein. For example... Figure 10 As shown, Figure 10 Example embodiment 1000 of the device package 102 shown is similar to Figure 7 The example embodiment 700 of the device package 102 shown includes one or more non-active dies 502 above and / or on the IC die 104, and the non-active die 502 includes one or more reflector structures 602.

[0190] like Figure 10Further illustrated, an example embodiment 1000 of the device package 102 may further include an additional reflector structure 1002 in a dielectric filling layer 120b above the non-active die 502. The reflector structure 1002 may extend through at least a portion of the dielectric filling layer 120b. The reflector structure 1002 may be positioned above the reflector structure 602 in the non-active die 502. In some embodiments, the reflector structure 1002 may be aligned with the reflector structure 602 in the x and / or y directions such that the reflector structure 1002 overlaps with the reflector structure 602. In some embodiments, the reflector structure 1002 may be partially aligned with the reflector structure 602 in the x and / or y directions such that one or more segments or portions of the reflector structure 1002 overlap with one or more segments or portions of the reflector structure 602. In some embodiments, the reflector structure 1002 may be laterally offset relative to the reflector structure 602 in the x and / or y directions.

[0191] In some embodiments, reflector structure 1002 may include a closed-loop structure similar to reflector structure 168 and / or similar to reflector structure 602. Reflector structure 1002 may be formed by forming a groove in dielectric filling layer 120b and depositing material of reflector structure 1002 in the groove.

[0192] As mentioned above, Figure 10 Provided as an example only. Other examples may be provided. Figure 10 The descriptions differ from those in the text.

[0193] Figure 11 This is a flowchart of an example process 1100 associated with forming the semiconductor device described herein. In some embodiments, one or more semiconductor processing tools (such as deposition tools, exposure tools, development tools, etching tools, planarization tools, ion implantation tools, annealing tools, bonding tools, wafer / die transfer tools, and / or another type of semiconductor processing tool) are used to perform Figure 11 One or more process blocks.

[0194] like Figure 11 As shown, process 1100 may include forming a grating coupler (block 1110) in a substrate of an IC die. For example, one or more semiconductor processing tools may be used to form a grating coupler (e.g., grating coupler 108) in a substrate (e.g., substrate 132a) of an IC die (e.g., IC die 106), as described herein.

[0195] like Figure 11As further shown, process 1100 may include forming a plurality of dielectric layers over the grating coupler (block 1120). For example, one or more semiconductor processing tools may be used to form a plurality of dielectric layers (e.g., dielectric layer 134a, ILD layer 140a, ESL 142a, passivation layer 148a) over the grating coupler, as described herein.

[0196] like Figure 11 As further shown, process 1100 may include forming a plurality of vertically arranged metallization layers in a plurality of dielectric layers (block 1130). For example, a plurality of vertically arranged metallization layers (e.g., conductive structure 144a) may be formed in a plurality of dielectric layers using one or more semiconductor processing tools, as described herein.

[0197] like Figure 11 As further shown, process 1100 may include forming grooves (block 1140) in multiple dielectric layers over the grating coupler. For example, one or more semiconductor processing tools may be used to form grooves (e.g., groove 304) through multiple dielectric layers over the grating coupler, as described herein.

[0198] like Figure 11 As further shown, process 1100 may include forming a conformal metal layer (block 1150) on the sidewalls of the recess. For example, one or more semiconductor processing tools may be used to form the conformal metal layer on the sidewalls of the recess (e.g., reflector structure 168), as described herein.

[0199] like Figure 11 As further shown, process 1100 may include filling a groove (block 1160) on the conformal metal layer with a dielectric layer. For example, as described herein, one or more semiconductor processing tools may be used to fill the groove on the conformal metal layer with a dielectric layer (e.g., a dielectric plug 164 during the formation of passivation layer 154a).

[0200] Process 1100 may include additional embodiments, such as any single embodiment or any combination of embodiments associated with one or more other processes described elsewhere herein.

[0201] In a first embodiment, forming a groove includes forming a groove such that the sidewalls of the groove are tapered between the bottom and top of the groove, wherein the conformal metal layer conforms to the angle of the sidewalls of the groove (e.g., dimension D5).

[0202] In the second embodiment, either alone or in combination with the first embodiment, the top view shape of the bottom of the groove is different from the top view shape of the groove.

[0203] In the third embodiment, forming a groove, alone or in combination with one or more of the first and second embodiments, includes forming a groove such that the sidewalls of the groove are approximately perpendicular between the bottom and top of the groove.

[0204] In the fourth embodiment, forming a groove, alone or in combination with one or more of the first to third embodiments, includes forming a groove such that the width of the bottom of the groove (e.g., dimension D1) is greater than the width of the grating coupler (e.g., dimension D3).

[0205] In the fifth embodiment, the conformal metal layer, alone or in combination with one or more of the first to fourth embodiments, includes at least one of tungsten (W), tantalum nitride (TaN), or titanium nitride (TiN).

[0206] although Figure 11 Example blocks of process 1100 are shown, but in some embodiments, process 1100 includes... Figure 11 The depicted blocks may include additional blocks, fewer blocks, different blocks, or blocks with different configurations. Alternatively, two or more blocks in process 1100 may be executed in parallel.

[0207] In this manner, the semiconductor device includes a grating coupler and a dielectric plug adjacent to the grating coupler. The dielectric plug defines an optical signal path through which the optical signal propagates to the grating coupler. To provide additional limitation on the optical signal to reduce scattering and crosstalk with other optical signals, a reflector structure is included around the periphery of the dielectric plug. The reflector structure is formed of a light-reflecting material, such as one or more metallic materials. The reflector structure reduces the likelihood of the optical signal being scattered into the semiconductor device layer surrounding the dielectric plug by reflecting the optical signal toward the grating coupler. Additionally and / or otherwise, the reflector structure reduces the likelihood of interference from other optical signals by reflecting other optical signals away from the grating coupler. In this way, the reflector structure reduces the scattering and / or interference of the optical signal, which reduces the likelihood and / or rate of conversion errors when converting the optical signal into an electrical signal.

[0208] As described in more detail above, some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers over the grating coupler, a dielectric plug over the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewalls of the dielectric plug. In some embodiments, the reflector structure includes a conformal metal film located between the dielectric plug and the dielectric layers. In some embodiments, the reflector structure includes a layer of at least one of the following: tantalum, titanium, aluminum, or copper. In some embodiments, the width of the bottom of the dielectric plug adjacent to the grating coupler is different from the width of the top of the dielectric plug, the sidewalls of the dielectric plug are angled between the bottom and top of the dielectric plug, and the reflector structure conforms to the plurality of sidewalls of the dielectric plug. In some embodiments, the lateral width of the grating coupler is smaller than the width of the bottom of the dielectric plug. In some embodiments, the grating coupler is laterally located within the periphery of the reflector structure. In some embodiments, the reflector structure is angularly positioned relative to the substrate of the second integrated circuit die at an angle less than approximately 90 degrees.

[0209] As described in more detail above, some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers over the grating coupler, a dielectric plug over the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewall of the dielectric plug. The dielectric plug is located in a region of the first integrated circuit die extending laterally outward from the second integrated circuit die. In a top view of the reflector structure, the reflector structure continuously surrounds the top view periphery of the dielectric plug. In some embodiments, the device package further includes a non-active die structure laterally adjacent to the second integrated circuit die over the region of the first integrated circuit die extending laterally outward from the second integrated circuit die. In some embodiments, the non-active die structure includes another reflector structure located over the reflector structure of the first integrated circuit die. In some embodiments, the passive die structure includes a first passive die and a second passive die, the first passive die being bonded to a first integrated circuit die, and the second passive die being bonded to the first passive die. The first passive die is perpendicularly positioned between the second passive die and the first integrated circuit die, and the first passive die includes another reflector structure located above a reflector structure of the first integrated circuit die. In some embodiments, the device package further includes a filler material layer surrounding the second integrated circuit die, surrounding the passive die, and above the passive die structure. In some embodiments, the reflector structure is a first reflector structure, and the passive die structure includes a second reflector structure located above the first reflector structure of the first integrated circuit die. The device package includes a third reflector structure in the filler material layer above the passive die structure. In some embodiments, the device package further includes a filler material layer surrounding the second integrated circuit die and above the first integrated circuit die extending outward from the second integrated circuit die side.

[0210] As described in more detail above, some embodiments described herein provide a method of forming a device package. The method includes forming a grating coupler in a substrate of an integrated circuit die. The method includes forming a plurality of dielectric layers over the grating coupler. The method includes forming a plurality of vertically arranged metallization layers in the plurality of dielectric layers. The method includes forming a groove over the grating coupler through the plurality of dielectric layers. The method includes forming a conformal metal layer on the sidewalls of the groove. The method includes filling the groove with a dielectric layer on the conformal metal layer. In some embodiments, the step of forming the groove includes forming the groove such that the sidewalls of the groove are tapered between the bottom and top of the groove, and the conformal metal layer conforms to the angle of the sidewalls of the groove. In some embodiments, the top view shape of the bottom of the groove is a different top view shape from the top view shape of the groove. In some embodiments, the step of forming the groove includes forming the groove such that the sidewalls of the groove are approximately perpendicular between the bottom and top of the groove. In some embodiments, the step of forming the groove includes forming the groove such that the width of the bottom of the groove is greater than the width of the grating coupler. In some embodiments, the conformal metal layer comprises at least one of the following: tungsten, tantalum nitride, or titanium nitride.

[0211] Some embodiments described herein provide a device package. The device package includes a first integrated circuit die. The device package includes a second integrated circuit die bonded to and perpendicularly disposed to the first integrated circuit die. The first integrated circuit die includes a grating coupler, one or more dielectric layers over the grating coupler, a dielectric plug over the grating coupler and extending perpendicularly through the one or more dielectric layers, and a reflector structure on the sidewall of the dielectric plug, the reflector structure being positioned at an angle relative to the substrate of the second integrated circuit die. In some embodiments, the angle is less than 90 degrees.

[0212] The terms “approximately” and “substantially” can mean that a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms “approximately” and “substantially” can refer to a percentage of the value of a given quantity.

[0213] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be easily used as a basis for designing or modifying other processes and structures used for the same purposes and / or to achieve the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, substituted, and replaced herein without departing from the spirit and scope of this disclosure.

Claims

1. A device package, characterized in that, Include: A first integrated circuit die; and A second integrated circuit die is bonded to the first integrated circuit die and disposed perpendicularly to the first integrated circuit die. The first integrated circuit die includes: A grating coupler; One or more dielectric layers are disposed on the grating coupler; A dielectric plug extends vertically through the one or more dielectric layers above the grating coupler; as well as A reflector structure is located on multiple sidewalls of the dielectric plug.

2. The device packaging as described in claim 1, characterized in that, The reflector structure includes a conformal metal film located between the dielectric plug and the one or more dielectric layers.

3. The device packaging as described in claim 1, characterized in that, The width of a bottom of the dielectric plug adjacent to the grating coupler is different from the width of a top of the dielectric plug; The plurality of sidewalls of the dielectric plug are angled between the bottom and the top of the dielectric plug; and The reflector structure conforms to the multiple sidewalls of the dielectric plug.

4. The device packaging as described in claim 3, characterized in that, The width of one side of the grating coupler is smaller than the width of the bottom of the dielectric plug.

5. The device packaging as described in claim 3, characterized in that, The grating coupler is located laterally within a periphery of the reflector structure.

6. A device package, characterized in that, Include: A first integrated circuit die; and A second integrated circuit die is bonded to the first integrated circuit die and disposed perpendicularly to the first integrated circuit die. The first integrated circuit die includes: A grating coupler; One or more dielectric layers are disposed on the grating coupler; A dielectric plug, extending vertically through the one or more dielectric layers above the grating coupler. The dielectric plug is located in a region of the first integrated circuit die that extends outward from the side of the second integrated circuit die; and A reflector structure is present on multiple sidewalls of the dielectric plug. In a top view of the reflector structure, the reflector structure surrounds a top-view periphery of the dielectric plug.

7. The device package as described in claim 6, characterized in that, The device package further includes: A non-active die structure is located on the region of the first integrated circuit die that extends outward from the side of the second integrated circuit die. The non-active die structure is laterally adjacent to the second integrated circuit die.

8. The device package as described in claim 7, characterized in that, The non-active grain structure includes: A first non-active die, bonded to the first integrated circuit die; and A second inactive grain is bonded to the first inactive grain. The first non-active die is perpendicularly positioned between the second non-active die and the first integrated circuit die, and The first non-active die includes another reflector structure located on top of the reflector structure of the first integrated circuit die.

9. A device package, characterized in that, Include: A first integrated circuit die; and A second integrated circuit die is bonded to the first integrated circuit die and disposed perpendicularly to the first integrated circuit die. The first integrated circuit die includes: A grating coupler; One or more dielectric layers are disposed on the grating coupler; A dielectric plug extends vertically through the one or more dielectric layers above the grating coupler; as well as A reflector structure is provided on a plurality of sidewalls of the dielectric plug, wherein the reflector structure is positioned at an angle relative to a substrate of the second integrated circuit die.

10. The device package as described in claim 9, characterized in that, The angle is less than 90 degrees.

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