Ethercat communication circuit based on digital isolator

Abstract

The utility model relates to the field of industrial automation and real -time communication technology provides an EtherCAT communication circuit based on digital isolator, the utility model discloses through double digital isolator and realizes the complete electrical isolation of MCU side and external IO side, and the anti -interference ability is improved significantly, through double power supply module independent power supply design, avoids the power noise coupling, and improved system stability. The utility model can realize the efficient electrical isolation of MCU and external IO, improve signal synchronous precision, reduce system cost and enhance supply chain stability, optimize SPI signal link design, significantly restrain high -frequency noise interference, reduce the error rate.

Description

Technical Field

[0001] This utility model relates to the field of industrial automation and real-time communication technology, and in particular to an EtherCAT communication circuit based on a digital isolator. Background Technology

[0002] Ethernet for Control Automation Technology (EtherCAT) is a real-time industrial communication protocol based on Ethernet. Due to its high speed (100 Mbit / s), low latency (<1 μs), and distributed clock synchronization capabilities, it is widely used in industrial automation fields such as CNC systems and motion control systems. EtherCAT achieves synchronization using the concept of a distributed clock. Through the calibration mechanism of the master and slave clocks in the system, clock jitter is kept far below 1 μs, and synchronization is also in the μs range. Furthermore, since this synchronization is implemented in hardware, it greatly ensures the reliability of EtherCAT.

[0003] However, the existing EtherCAT communication circuits have the following problems: (1) Signal interference: In the existing EtherCAT communication circuits, there is a lack of effective electrical isolation between the MCU and the external IO or physical layer (PHY), which leads to a decrease in signal integrity and an increase in bit error rate under strong noise environment. (2) Insufficient synchronization accuracy: Multi-channel signals (such as SYNC0 / SYNC1, MRST) are prone to transmission delay differences, which affect the distributed clock synchronization accuracy. (3) Bottleneck of domestic substitution: Mainstream digital isolators rely on imports (such as ADI ADuM5401), which are costly and have long supply cycles, limiting the self-controllability of domestic industrial equipment. (4) Lack of anti-interference design: Impedance matching and redundant pull-up design for SPI signal links are not carried out, resulting in serious high-frequency noise interference.

[0004] Therefore, there is an urgent need for a new type of EtherCAT communication circuit based on digital isolators to solve the above-mentioned technical problems. Summary of the Invention

[0005] The purpose of this invention is to provide an EtherCAT communication circuit based on a digital isolator, which can achieve efficient electrical isolation between the MCU and external I / O, improve signal synchronization accuracy, reduce system cost and enhance supply chain stability, optimize SPI signal link design, significantly suppress high-frequency noise interference, and reduce bit error rate.

[0006] To achieve the above objectives, this utility model provides an EtherCAT communication circuit based on a digital isolator, comprising: an MCU control module for running the EtherCAT slave protocol stack; an external I / O module for connecting to an Ethernet connector as a communication interface; a first digital isolator coupled to both the MCU control module and the external I / O module for electrical isolation between SPI signals; a second digital isolator coupled to both the MCU control module and the external I / O module for electrical isolation between synchronization signals and reset signals, and for electrical isolation from the SPI signals; a first power supply module coupled to the MCU control module for independent power supply to the MCU side; and a second power supply module coupled to the external I / O module for independent power supply to the external I / O side, thereby completely isolating the power supplies of the MCU control module and the external I / O module.

[0007] In some embodiments, the MCU control module uses an STM32H750VBT6 main control chip; the external IO module uses an ABCC_B40 chip; and both the first digital isolator and the second digital isolator use an SSP5841ED four-channel digital isolator.

[0008] The above technical solution achieves complete electrical isolation between the MCU side and the external I / O side through dual digital isolators, significantly improving anti-interference capabilities. The independent power supply design with dual power supply modules avoids power supply noise coupling, improving system stability. This invention enables efficient electrical isolation between the MCU and external I / O, improves signal synchronization accuracy, reduces system costs and enhances supply chain stability, optimizes the SPI signal link design, significantly suppresses high-frequency noise interference, and reduces the bit error rate. This invention is particularly suitable for distributed industrial control systems in high-precision synchronous control and strong electromagnetic interference (EMC) environments, such as motion control, semiconductor electroplating power supplies, and servo drives. Attached Figure Description

[0009] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A schematic diagram of the architecture of an EtherCAT communication circuit based on a digital isolator provided in an embodiment of this utility model; Figure 2 This is a circuit connection diagram of a digital isolator provided in an embodiment of the present invention; Figure 3A circuit connection diagram of an MCU control module provided in an embodiment of this utility model; Figure 4 A circuit connection diagram of an external I / O module provided in an embodiment of this utility model; Figure 5 A circuit connection diagram of an Ethernet connector provided in an embodiment of this utility model; Figure 6 A circuit connection diagram of a power supply module provided in an embodiment of this utility model; Figure 7 This is a circuit connection diagram of a reset chip provided in an embodiment of the present invention. Detailed Implementation

[0011] The technical solutions in the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments.

[0012] Please refer to the following: Figures 1-7 ,in, Figure 1 A schematic diagram of the architecture of an EtherCAT communication circuit based on a digital isolator provided in an embodiment of this utility model; Figure 2 This is a circuit connection diagram of a digital isolator provided in an embodiment of the present invention; Figure 3 A circuit connection diagram of an MCU control module provided in an embodiment of this utility model; Figure 4 A circuit connection diagram of an external I / O module provided in an embodiment of this utility model; Figure 5 A circuit connection diagram of an Ethernet connector provided in an embodiment of this utility model; Figure 6 A circuit connection diagram of a power supply module provided in an embodiment of this utility model; Figure 7 This is a circuit connection diagram of a reset chip provided in an embodiment of the present invention.

[0013] like Figure 1 As shown, the EtherCAT communication circuit based on a digital isolator described in this embodiment includes: an MCU control module 11, an external IO module 12, an Ethernet connector 13, a first digital isolator 141, a second digital isolator 142, a first power supply module 151, and a second power supply module 152.

[0014] Specifically, the MCU control module 11 is used to run the EtherCAT slave protocol stack. The external I / O module 12 is connected to the Ethernet connector 13 as a communication interface. The first digital isolator 141 is coupled to both the MCU control module 11 and the external I / O module 12 to achieve electrical isolation between SPI signals; the second digital isolator 142 is coupled to both the MCU control module 11 and the external I / O module 12 to achieve electrical isolation between synchronization signals and reset signals, and electrical isolation from the SPI signals. The first power supply module 151 is coupled to the MCU control module 11 to achieve independent power supply on the MCU side; the second power supply module 152 is coupled to the external I / O module 12 to achieve independent power supply on the external I / O side, so that the power supply of the MCU control module 11 and the external I / O module 12 is completely isolated, avoiding ground loop interference.

[0015] This embodiment achieves complete electrical isolation between the MCU side and the external I / O side through dual digital isolators, significantly improving anti-interference capability; and avoids power supply noise coupling through the independent power supply design of dual power supply modules, thus improving system stability.

[0016] like Figures 1-4 As shown, in this embodiment, the MCU control module 11 uses the STM32H750VBT6 main control chip U7. The external IO module 12 uses the ABCC_B40 chip U2. Both the first digital isolator 141 and the second digital isolator 142 use SSP5841ED four-channel digital isolators; specifically, the first digital isolator 141 uses SSP5841ED four-channel digital isolator U5, and the second digital isolator 142 uses SSP5841ED four-channel digital isolator U8. Replacing traditional imported isolators (such as ADuM5401) with SSP5841ED four-channel digital isolators significantly improves anti-interference capabilities while achieving domestic substitution, making the supply chain self-controllable, reducing costs by 40%, and supporting an industrial temperature range of -40℃ to +125℃.

[0017] In this embodiment, the STM32H750VBT6 master control chip is configured as follows: the SPI interface is in full-duplex mode with a baud rate of 10MHz, the EtherCAT slave protocol stack is enabled, and the EtherCAT MAC interface is supported. Hardware-wise, the MCU selected is the STM32H750VBT6 with a main frequency of 480MHz and support for the EtherCAT MAC interface. Software-wise, the STM32H750VBT6's SPI interface is configured to full-duplex mode with a baud rate of 10MHz; the EtherCAT slave protocol stack is enabled, and the communication parameters between the ESC (EtherCAT Slave Controller) and the application layer are set.

[0018] like Figures 1-4 As shown, in this embodiment, the first digital isolator 141 (specifically...) Figure 2 The input pin corresponding to the ISO_SPI_SS signal of U5 in part (a) is coupled to the pin corresponding to the ISO_SPI_SS signal of the STM32H750VBT6 main control chip U7. The input pin corresponding to the ISO_SPI_SCLK signal of the first digital isolator 141 (specifically U5) is coupled to the pin corresponding to the ISO_SPI_SCLK signal of the STM32H750VBT6 main control chip U7. The input pin corresponding to the ISO_SPI_MOSI signal of the first digital isolator 141 (specifically U5) is coupled to the pin corresponding to the ISO_SPI_MOSI signal of the STM32H750VBT6 main control chip U7. The output pin corresponding to the ISO_SPI_MISO signal of the first digital isolator 141 (specifically U5) is coupled to the pin corresponding to the ISO_SPI_MISO signal of the STM32H750VBT6 main control chip U7. The pins corresponding to the ISO_SPI_MISO signals of the control chip U7 are connected to the pins corresponding to the SPI_SS signals of the first digital isolator 141 (specifically U5); the output pins corresponding to the SPI_SS signals of the first digital isolator 141 (specifically U5) are coupled to the pins corresponding to the SPI_SS signals of the ABCC_B40 chip U2; the output pins corresponding to the SPI_SCLK signals of the first digital isolator 141 (specifically U5) are coupled to the pins corresponding to the SPI_SCLK signals of the ABCC_B40 chip U2; the output pins corresponding to the SPI_MOSI signals of the first digital isolator 141 (specifically U5) are coupled to the pins corresponding to the SPI_MOSI signals of the ABCC_B40 chip U2; and the input pins corresponding to the SPI_MISO signals of the first digital isolator 141 (specifically U5) are coupled to the pins corresponding to the SPI_MISO signals of the ABCC_B40 chip U2. Through the above settings, electrical isolation between SPI signals is achieved. SPI (Serial Peripheral Interface) is a classic 4-wire hardware architecture, consisting of 3 buses and 1 independent chip select line. This is the core design for SPI to achieve multi-device communication. The 3 buses are SCK, MOSI, and MISO, and the independent chip select line is SS. SS (Slave Select): Slave device select signal line, often called the chip select signal line. SCLK (Serial Clock): Clock signal line used for communication data synchronization. MOSI (Master Output, Slave Input): Master output, slave input pin. MISO (Master Input, Slave Output): Master input, slave output pin.

[0019] like Figures 1-4 As shown, in this embodiment, the second digital isolator 142 (specifically...) Figure 2 The input pin corresponding to the ABCC_MI1 signal of U8 in part (b) is coupled to the pin corresponding to the ABCC_MI1 signal of the ABCC_B40 chip U2; the input pin corresponding to the ABCC_MI0 signal of the second digital isolator 142 (specifically U8) is coupled to the pin corresponding to the ABCC_MI0 signal of the ABCC_B40 chip U2; the output pin corresponding to the MR_RESET signal of the second digital isolator 142 (specifically U8) is coupled to the pin corresponding to the ABCC_RESET signal of the ABCC_B40 chip U2; the ISO_AB signal of the second digital isolator 142 (specifically U8) is coupled to the pin corresponding to the ABCC_RESET signal of the ABCC_B40 chip U2; The output pin corresponding to the CC_MI1 signal is coupled to the pin corresponding to the ISO_ABCC_MI1 signal of the STM32H750VBT6 main control chip U7. The output pin corresponding to the ISO_ABCC_MI0 signal of the second digital isolator 142 (specifically U8) is coupled to the pin corresponding to the ISO_ABCC_MI0 signal of the STM32H750VBT6 main control chip U7. The input pin corresponding to the ISO_MR_RESET signal of the second digital isolator 142 (specifically U8) is coupled to the pin corresponding to the ISO_MR_RESET signal of the STM32H750VBT6 main control chip U7. Through the above settings, electrical isolation is achieved between the synchronization signal (SYNC) and the reset signal (MRST), as well as electrical isolation from the SPI signal.

[0020] Please continue reading. Figures 1-4 In this embodiment, a damping resistor (R25 / R29 / R31 / R33) is connected in series between the first digital isolator 141 (specifically U5) and each pair of pins corresponding to the ABCC_B40 chip U2; a damping resistor (R37 / R39 / R42) is connected in series between the second digital isolator 142 (specifically U8) and each pair of pins corresponding to the ABCC_B40 chip U2. A current-limiting resistor (R24 / R28 / R30 / R32) is connected in series between the first digital isolator 141 (specifically U5) and each pair of pins corresponding to the STM32H750VBT6 main control chip U7; a current-limiting resistor (R38 / R40 / R43) is connected in series between the second digital isolator 142 (specifically U8) and each pair of pins corresponding to the STM32H750VBT6 main control chip U7. The resistance value of the current-limiting resistor is less than the resistance value of the damping resistor. Specifically, the resistance value of the damping resistor can be set to 220Ω as needed. The current-limiting resistor can be set to 100Ω as needed. By adding a current-limiting resistor in conjunction with a damping resistor, signal reflection and ringing can be effectively suppressed.

[0021] Please refer to the following: Figure 1 , Figure 2 , Figure 4 , Figure 7 In this embodiment, the output pin corresponding to the MR_RESET signal of the second digital isolator 142 (specifically U8) is connected to the first reset chip (specifically U8) via a damping resistor (specifically R42). Figure 7 The pin corresponding to the MR_RESET signal of the TPS3823-33DBVR chip U1 in part (a) is connected; the pin corresponding to the ABCC_RESET signal of the first reset chip U1 is connected to the pin corresponding to the ABCC_RESET signal of the ABCC_B40 chip U2.

[0022] Please refer to the following: Figure 1 , Figure 2 , Figure 3 , Figure 6 , Figure 7 In this embodiment, the pin corresponding to the RESET-S signal of the STM32H750VBT6 main control chip U7 is connected to the second reset chip (specifically...) Figure 7 The pin corresponding to the RESET-S signal of the TPS3823-33DBVR chip U6 in part (b) is connected, and the pin corresponding to the RESET-S signal of the STM32H750VBT6 main control chip U7 is simultaneously connected to the first power supply module (specifically...). Figure 6 In section (a), the output terminal (specifically the +3.3V terminal) of the DC-DC power supply chip U3 of the TP6327GS6 is connected to the ground of the power layer via a decoupling capacitor. The pin corresponding to the RESET-S signal of the second reset chip U6 is connected to the output terminal of the first power supply module via a pull-up resistor (R36). The pull-up resistor is used to ensure that the signal of the corresponding pin is high when not driven, preventing false triggering.

[0023] Please refer to the following: Figure 1 , Figure 2 , Figure 6 In this embodiment, the pin corresponding to the EN1 signal of the first digital isolator 141 (specifically U5) is connected to the first power supply module (specifically U5) via a pull-up resistor (specifically R34). Figure 6The output terminal (specifically the +3.3V terminal) of the DC-DC power chip U3 of the TP6327GS6 in part (a) is connected to the output terminal (specifically the VCC_INF terminal) of the second power supply module (specifically the DC-DC power chip U4 of the TP6327GS6) via another pull-up resistor (specifically R35). The pin corresponding to the EN2 signal of the second digital isolator 141 (specifically U5) is connected to the output terminal (specifically the VCC_INF terminal) of the second power supply module (specifically the DC-DC power chip U4 of the TP6327GS6) via a pull-up resistor (R45). The pin corresponding to the EN1 signal of the second digital isolator 142 (specifically U8) is connected to the output terminal (specifically the VCC_INF terminal) of the second power supply module (specifically U4) via a pull-up resistor (R45). Figure 6 In section (b), the output terminal (specifically the VCC_INF terminal) of the DC-DC power chip U4 of the TP6327GS6 is connected via another pull-up resistor to the output terminal (specifically the +3.3V terminal) of the first power supply module (specifically the DC-DC power chip U3 of the TP6327GS6). The pin corresponding to the EN2 signal of the second digital isolator 142 (specifically U8) is connected to the output terminal (specifically the +3.3V terminal) of the first power supply module (specifically the +3.3V terminal) via another pull-up resistor. The pull-up resistor is used to ensure that the signal of the corresponding pin is high when not driven, preventing false triggering.

[0024] Please refer to the following: Figure 1 , Figure 2 , Figure 6 In this embodiment, the pin corresponding to the VCC1 signal of the first digital isolator 141 (specifically U5) is connected to the output terminal (specifically +3.3V terminal) of the first power supply module (specifically the DC-DC power chip U3 of TP6327GS6), and is simultaneously connected to the ground GND of the power layer via a decoupling capacitor (specifically C30); the pin corresponding to the VCC2 signal of the first digital isolator 141 (specifically U5) is connected to the output terminal (specifically VCC_INF terminal) of the second power supply module (specifically the DC-DC power chip U4 of TP6327GS6), and is simultaneously connected to the ground GND_SIGNAL of the signal layer via a decoupling capacitor (specifically C31). The pin corresponding to the VCC1 signal of the second digital isolator 142 (specifically U8) is connected to the output terminal (specifically the VCC_INF terminal) of the second power supply module (specifically the DC-DC power chip U4 of TP6327GS6), and simultaneously connected to the ground GND_SIGNAL of the signal layer via a decoupling capacitor (specifically C35); the pin corresponding to the VCC2 signal of the second digital isolator 142 (specifically U8) is connected to the output terminal (specifically the +3.3V terminal) of the first power supply module (specifically the DC-DC power chip U3 of TP6327GS6), and simultaneously connected to the ground GND of the power layer via a decoupling capacitor (specifically C34). The decoupling capacitor enables signal integrity optimization.

[0025] Please refer to the following: Figures 1-6In this embodiment, both the first power supply module 151 and the second power supply module 152 use the TP6327GS6 DC-DC power chip. Specifically, the first power supply module 151 uses the TP6327GS6 DC-DC power chip U3, and the second power supply module 152 uses the TP6327GS6 DC-DC power chip U4. The first reference power supply (specifically +12V) is converted to a first power supply (specifically +3.3V) by the first power supply module through DC-DC conversion, and then output to the MCU control module 11. The second reference power supply (specifically VCC_12V) is converted to a second power supply (specifically VCC_INF) by the second power supply module through DC-DC conversion, and then output to the external IO module 12. That is, the MCU-side power supply (3.3V) is converted from +12V by the DC-DC power chip U3, and the external IO-side power supply (3.3V) is converted from VCC_12V by the DC-DC power chip U4. The dual-power independent power supply design avoids power supply noise coupling and improves system stability.

[0026] In this embodiment, the voltage values ​​of the first reference power supply and the second reference power supply are both 12V, and the voltage values ​​of the first power supply and the second power supply are both 3.3V.

[0027] Preferably, the circuit includes a multilayer PCB board, wherein the ground GND_SIGNAL of the signal layer and the ground GND of the power layer are located on different layers of the PCB board, so as to separate the signal layer from the power layer and reduce coupling noise.

[0028] Please refer to the following: Figure 1 , Figure 4 , Figure 5 In this embodiment, the Ethernet connector 13 uses the HR911205C chip RJ1. Specifically, the pin corresponding to the A_1P / RXP signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_1P / RXP signal of the HR911205C chip RJ1. The pin corresponding to the A_1CEN / SDA signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_1CEN / SDA signal of the HR911205C chip RJ1, and then connected to the signal layer ground GND_SIGNAL via a decoupling capacitor (specifically C3). The pin corresponding to the A_1N / RXN signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_1N / RXN signal of the HR911205C chip RJ1. The decoupling capacitor enables signal integrity optimization.

[0029] Please continue reading. Figure 1 , Figure 4 , Figure 5 In this embodiment, the pin corresponding to the A_2P / SDP signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_2P / SDP signal of the HR911205C chip RJ1. The pin corresponding to the A_2CEN / SCL signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_2CEN / SCL signal of the HR911205C chip, and then connected to the ground GND_SIGNAL of the signal layer via a decoupling capacitor (specifically C4). The pin corresponding to the A_2N / SDN signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the A_2N / SDN signal of the HR911205C chip RJ1. The decoupling capacitor enables signal integrity optimization.

[0030] Please continue reading. Figure 1 , Figure 4 , Figure 5 In this embodiment, the pin corresponding to the B_1P / RXP signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the B_1P / RXP signal of the HR911205C chip RJ1. The pin corresponding to the B_1CEN / SDA signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the B_1CEN / SDA signal of the HR911205C chip, and then connected to the signal layer ground GND_SIGNAL via a decoupling capacitor (specifically C5). The pin corresponding to the B_1N / RXN signal of the ABCC_B40 chip is connected to the pin corresponding to the B_1N / RXN signal of the HR911205C chip RJ1. The decoupling capacitor enables signal integrity optimization.

[0031] Please continue reading. Figure 1 , Figure 4 , Figure 5 In this embodiment, the pin corresponding to the B_2P / SDP signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the B_2P / SDP signal of the HR911205C chip RJ1. The pin corresponding to the B_2CEN / SCL signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the B_2CEN / SCL signal of the HR911205C chip RJ1, and then connected to the ground GND_SIGNAL of the signal layer via a decoupling capacitor (specifically C6). The pin corresponding to the B_2N / SDN signal of the ABCC_B40 chip U2 is connected to the pin corresponding to the B_2N / SDN signal of the HR911205C chip RJ1. The decoupling capacitor enables signal integrity optimization.

[0032] Preferably, the pin pairs corresponding to the A_1P / RXP signals of the ABCC_B40 chip U2 and the pin pairs corresponding to the A_1N / RXN signals of the HR911205C chip RJ1 are wired with equal length and spacing; wherein the trace length error is less than 5mm.

[0033] Preferably, the pin pairs corresponding to the A_2P / SDP signals and the pin pairs corresponding to the A_2N / SDN signals of the ABCC_B40 chip U2 and the HR911205C chip RJ1 are wired with equal length and equal spacing; wherein the trace length error is less than 5mm.

[0034] Preferably, the pin pairs corresponding to the B_1P / RXP signals and the pin pairs corresponding to the B_1N / RXN signals of the ABCC_B40 chip U2 and the HR911205C chip RJ1 are wired with equal length and equal spacing; wherein the trace length error is less than 5mm.

[0035] Preferably, the pin pairs corresponding to the B_1N / RXN signals and the pin pairs corresponding to the B_2N / SDN signals of the ABCC_B40 chip U2 and the HR911205C chip RJ1 are wired with equal length and equal spacing; wherein the trace length error is less than 5mm.

[0036] Differential signals (A_1P / RXP and A_1N / RXN, A_2P / SDP and A_2N / SDN, B_1P / RXP and B_1N / RXN, B_2P / SDP and B_2N / SDN signals) are routed with equal lengths and a trace length error of <5mm, which can make the transmission delay difference <1ns.

[0037] The following is in conjunction with the appendix Figures 2-7 The connection relationship of the main pins is given: Pin 96 of the ISO_SPI_SS signal of U7 (STM32H750VBT6) is connected to pin 3 of the ISO_SPI_SS signal of U5 (SSP5841ED) via resistor R24. Pin 46 of the ISO_SPI_SCLK signal is connected to pin 4 of the ISO_SPI_SCLK signal of U5 (SSP5841ED) via resistor R28. Pin 16 of the ISO_SPI_MOSI signal is connected to pin 5 of the ISO_SPI_MOSI signal of U5 (SSP5841ED) via resistor R30. Pin 17 of the ISO_SPI_MISO signal is connected to... Pin 6 of U5 (SSP5841ED) is connected to the ISO_SPI_MISO signal; pin 61 of U5 (SSP5841ED) is connected to pin 14 of U8 (SSP5841ED) via resistor R38; pin 60 of U8 (SSP5841ED) is connected to pin 13 of U8 (SSP5841ED) via resistor R43; and pin 62 of U8 (SSP5841ED) is connected to pin 10 of U8 (SSP5841ED) via resistor R43.

[0038] Pin 14 of the RESET-S signal of U7 (STM32H750VBT6) is connected to pin 1 of the RESET-S signal of U6 (reset chip TPS3823-33DBVR), and then connected to GND via decoupling capacitor C32. Pin 3 of the MR_RESET signal of U6 (reset chip TPS3823-33DBVR) is connected to the +3.3V terminal of pin 6 of U3 (TP6327GS6) via pull-up resistor R36. Pin 5 of the VDD signal of U6 (reset chip TPS3823-33DBVR) is also connected to the +3.3V terminal of pin 6 of U3 (TP6327GS6).

[0039] The A_13 pin corresponding to the SPI_SS signal of U2 (ABCC_B40_Module) is connected to the SPI_SS signal pin 14 of U5 (SSP5841ED) via resistor R25. The A_15 pin corresponding to the SPI_SCLK signal is connected to the SPI_SCLK signal pin 13 of U5 (SSP5841ED) via resistor R29. The A_17 pin corresponding to the SPI_MOSI signal is connected to the SPI_MOSI signal pin of U5 (SSP5841ED) via resistor R31. The corresponding pin 12 is connected. The A_16 pin corresponding to the SPI_MISO signal is connected to the SPI_MISO signal pin 11 of U5 (SSP5841ED) via resistor R33. The A_53 pin corresponding to the ABCC_MI1 signal is connected to the ABCC_MI1 signal pin 3 of U8 (SSP5841ED) via resistor R37. The A_54 pin corresponding to the ABCC_MI0 signal is connected to the ABCC_MI0 signal pin 4 of U8 (SSP5841ED) via resistor R42.

[0040] Pin A_3 of the ABCC_RESET signal of U2 (ABCC_B40_Module) is connected to pin 1 of the ABCC_RESET signal of U1 (TPS3823-33DBVR reset chip). Pin 3 of the MR_RESET signal of U1 (TPS3823-33DBVR reset chip) is connected to pin 6 of the MR_RESET signal of U8 (SSP5841ED) via resistor R42. Pin 5 of the VDD signal of U1 (TPS3823-33DBVR reset chip) is connected to the VCC_INF terminal of pin 6 of U4 (TP6327GS6). Pin 5 of the VDD signal of U1 (TPS3823-33DBVR reset chip) is also connected to the signal layer ground GND_SIGNAL via decoupling capacitor C1 (0.1uF).

[0041] The N_29 pin of the U2 (ABCC_B40_Module) corresponding to the A_1P / RXP signal is connected to pin 1 of the RJ1 (Ethernet connector) corresponding to the A_1P / RXP signal. The N_30 pin of the A_1CEN / SDA signal is connected to pin 4 of the RJ1 (Ethernet connector) corresponding to the A_1CEN / SDA signal, and then connected to GND_SIGNAL via decoupling capacitor C3 (0.1uF). The N_31 pin of the A_1N / RXN signal is connected to the A_1N / RXN pin of the RJ1 (Ethernet connector). Pin 2 corresponding to the N signal is connected. Pin N_33 corresponding to the A_2P / SDP signal is connected to pin 3 corresponding to the A_2P / SDP signal of the RJ1 (Ethernet connector). Pin N_34 corresponding to the A_2CEN / SCL signal is connected to pin 5 corresponding to the A_2CEN / SCL signal of the RJ1 (Ethernet connector), and then connected to GND_SIGNAL via decoupling capacitor C4 (0.1uF). Pin N_35 corresponding to the A_2N / SDN signal is connected to pin 6 corresponding to the A_2N / SDN signal of the RJ1 (Ethernet connector). The pins are connected as follows: pin N_3, corresponding to the B_1P / RXP signal, is connected to pin 2(1) of the RJ1 (Ethernet connector); pin N_4, corresponding to the B_1CEN / SDA signal, is connected to pin 2(4) of the RJ1 (Ethernet connector) via decoupling capacitor C5 (0.1uF) and then connected to GND_SIGNAL; pin N_5, corresponding to the B_1N / RXN signal, is connected to pin 2(2) of the RJ1 (Ethernet connector). The N_7 pin corresponding to the B_2P / SDP signal is connected to the 2(3) pin corresponding to the B_2P / SDP signal of the RJ1 (Ethernet connector). The N_8 pin corresponding to the B_2CEN / SCL signal is connected to the 2(5) pin corresponding to the B_2CEN / SCL signal of the RJ1 (Ethernet connector) and then connected to GND_SIGNAL via the decoupling capacitor C3 (0.1uF). The N_9 pin corresponding to the B_2N / SDN signal is connected to the 2(6) pin corresponding to the B_2N / SDN signal of the RJ1 (Ethernet connector).

[0042] Test and verification: (1) SPI signal jitter (<100ps) was measured using an oscilloscope; (2) Signal synchronization accuracy (±0.8μs) was tested using an EtherCAT master station; (3) EMC tests (ESD 8kV contact discharge, EFT 4kV burst) were performed to verify anti-interference capability. After SPI signal link optimization, the bit error rate was reduced from 10⁻ 4 Reduced to 10⁻ 7Significantly suppresses high-frequency noise interference, and passes EMC tests of IEC 61000-4-2 (ESD Level 4) and IEC 61000-4-4 (EFT Level 4); (4) SPI signals (SS, SCLK, MOSI, MISO) are isolated through four channels of SSP5841ED, with an isolation voltage of 5kVrms and CMTI (Common Mode Transient Immunity) > 100kV / μs, meeting the IEC 61158 standard.

[0043] The above embodiments achieve complete electrical isolation between the MCU side and the external I / O side through dual digital isolators, significantly improving anti-interference capabilities. The independent power supply design with dual power supply modules avoids power supply noise coupling, improving system stability. This invention achieves efficient electrical isolation between the MCU and external I / O, improves signal synchronization accuracy, reduces system costs and enhances supply chain stability, optimizes the SPI signal link design, significantly suppresses high-frequency noise interference, and reduces the bit error rate. This invention is particularly suitable for distributed industrial control systems in high-precision synchronous control and strong electromagnetic interference (EMC) environments, such as motion control, semiconductor electroplating power supplies, and servo drives.

[0044] It should be noted that in the above embodiments, each embodiment focuses on the differences from other embodiments, and the same / similar parts between the embodiments can be referred to each other.

[0045] The terms "comprising" and "having," and variations thereof, used in this document are intended to cover non-exclusive inclusion. The terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence, unless explicitly indicated by the context; such use of terms should be understood to be interchangeable where appropriate. The term "one or more," at least in part depending on the context, can be used to describe features, structures, or characteristics in a singular sense, or in a plural sense, to describe combinations of features, structures, or characteristics. The term "based on" can be understood as not necessarily intended to express an exclusive set of factors, but can instead, at least in part depending on the context, allow for the presence of other factors that are not necessarily explicitly described. Furthermore, embodiments and features within embodiments of this invention can be combined with each other without conflict. In addition, descriptions of well-known components and technologies have been omitted in the above description to avoid unnecessarily obscuring the concepts of this invention.

[0046] The above description is merely a preferred embodiment of this utility model and is not intended to limit the scope of protection of this utility model. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principle of this utility model, and these improvements and modifications should also be considered within the scope of protection of this utility model.

Claims

1. An EtherCAT communication circuit based on a digital isolator, characterized in that, include: The MCU control module is used to run the EtherCAT slave protocol stack; An external I / O module, which serves as a communication interface, connects to the Ethernet connector. The first digital isolator is coupled to the MCU control module and the external IO module respectively, and is used to achieve electrical isolation between SPI signals; The second digital isolator is coupled to the MCU control module and the external IO module respectively, and is used to achieve electrical isolation between the synchronization signal and the reset signal, and electrical isolation from the SPI signal; The first power supply module is coupled to the MCU control module and is used to realize independent power supply on the MCU side; The second power supply module is coupled to the external I / O module to provide independent power to the external I / O side, so that the power supply of the MCU control module is completely isolated from the power supply of the external I / O module.

2. The EtherCAT communication circuit based on a digital isolator according to claim 1, characterized in that, The MCU control module uses an STM32H750VBT6 main control chip. The external I / O module uses the ABCC_B40 chip; Both the first and second digital isolators are SSP5841ED four-channel digital isolators.

3. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, The STM32H750VBT6 master control chip is configured as follows: the SPI interface is in full-duplex mode with a baud rate of 10MHz, the EtherCAT slave protocol stack is enabled, and the EtherCAT MAC interface is supported.

4. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, The input pin corresponding to the ISO_SPI_SS signal of the first digital isolator is coupled to the pin corresponding to the ISO_SPI_SS signal of the STM32H750VBT6 main control chip; the input pin corresponding to the ISO_SPI_SCLK signal of the first digital isolator is coupled to the pin corresponding to the ISO_SPI_SCLK signal of the STM32H750VBT6 main control chip; the input pin corresponding to the ISO_SPI_MOSI signal of the first digital isolator is coupled to the pin corresponding to the ISO_SPI_MOSI signal of the STM32H750VBT6 main control chip; and the output pin corresponding to the ISO_SPI_MISO signal of the first digital isolator is coupled to the pin corresponding to the ISO_SPI_MISO signal of the STM32H750VBT6 main control chip. The output pin corresponding to the SPI_SS signal of the first digital isolator is coupled to the pin corresponding to the SPI_SS signal of the ABCC_B40 chip; the output pin corresponding to the SPI_SCLK signal of the first digital isolator is coupled to the pin corresponding to the SPI_SCLK signal of the ABCC_B40 chip; the output pin corresponding to the SPI_MOSI signal of the first digital isolator is coupled to the pin corresponding to the SPI_MOSI signal of the ABCC_B40 chip; and the input pin corresponding to the SPI_MISO signal of the first digital isolator is coupled to the pin corresponding to the SPI_MISO signal of the ABCC_B40 chip. The input pin corresponding to the ABCC_MI1 signal of the second digital isolator is coupled to the pin corresponding to the ABCC_MI1 signal of the ABCC_B40 chip; the input pin corresponding to the ABCC_MI0 signal of the second digital isolator is coupled to the pin corresponding to the ABCC_MI0 signal of the ABCC_B40 chip; and the output pin corresponding to the MR_RESET signal of the second digital isolator is coupled to the pin corresponding to the ABCC_RESET signal of the ABCC_B40 chip. The output pin corresponding to the ISO_ABCC_MI1 signal of the second digital isolator is coupled to the pin corresponding to the ISO_ABCC_MI1 signal of the STM32H750VBT6 main control chip, the output pin corresponding to the ISO_ABCC_MI0 signal of the second digital isolator is coupled to the pin corresponding to the ISO_ABCC_MI0 signal of the STM32H750VBT6 main control chip, and the input pin corresponding to the ISO_MR_RESET signal of the second digital isolator is coupled to the pin corresponding to the ISO_MR_RESET signal of the STM32H750VBT6 main control chip.

5. The EtherCAT communication circuit based on a digital isolator according to claim 4, characterized in that, A damping resistor is connected in series between the first digital isolator and each pair of pins corresponding to the ABCC_B40 chip; a damping resistor is connected in series between the second digital isolator and each pair of pins corresponding to the ABCC_B40 chip; a current-limiting resistor is connected in series between the first digital isolator and each pair of pins corresponding to the STM32H750VBT6 main control chip; and a current-limiting resistor is connected in series between the second digital isolator and each pair of pins corresponding to the STM32H750VBT6 main control chip.

6. The EtherCAT communication circuit based on a digital isolator according to claim 4, characterized in that, The output pin corresponding to the MR_RESET signal of the second digital isolator is connected to the pin corresponding to the MR_RESET signal of the first reset chip via a damping resistor; the pin corresponding to the ABCC_RESET signal of the first reset chip is connected to the pin corresponding to the ABCC_RESET signal of the ABCC_B40 chip. The pin corresponding to the RESET-S signal of the STM32H750VBT6 main control chip is connected to the pin corresponding to the RESET-S signal of the second reset chip. The pin corresponding to the RESET-S signal of the STM32H750VBT6 main control chip is also connected to the output terminal of the first power supply module. The pin corresponding to the RESET-S signal of the second reset chip is also connected to the ground of the power layer through a decoupling capacitor. The pin corresponding to the MR_RESET signal of the second reset chip is connected to the output terminal of the first power supply module via a pull-up resistor.

7. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, The pin corresponding to the EN1 signal of the first digital isolator is connected to the output terminal of the first power supply module via a pull-up resistor, and the pin corresponding to the EN2 signal of the first digital isolator is connected to the output terminal of the second power supply module via another pull-up resistor. The pin corresponding to the EN1 signal of the second digital isolator is connected to the output terminal of the second power supply module via a pull-up resistor, and the pin corresponding to the EN2 signal of the second digital isolator is connected to the output terminal of the first power supply module via another pull-up resistor.

8. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, The pin corresponding to the VCC1 signal of the first digital isolator is connected to the output terminal of the first power supply module, and is also connected to the ground of the power layer via a decoupling capacitor; the pin corresponding to the VCC2 signal of the first digital isolator is connected to the output terminal of the second power supply module, and is also connected to the ground of the signal layer via a decoupling capacitor. The pin corresponding to the VCC1 signal of the second digital isolator is connected to the output terminal of the second power supply module, and is also connected to the ground of the signal layer via a decoupling capacitor; the pin corresponding to the VCC2 signal of the second digital isolator is connected to the output terminal of the first power supply module, and is also connected to the ground of the power supply layer via a decoupling capacitor.

9. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, Both the first power supply module and the second power supply module use the TP6327GS6 DC-DC power chip; The first reference power supply is converted from DC to DC by the first power supply module to form the first power supply, and then output to the MCU control module; The second reference power supply is converted from DC to DC by the second power supply module to form a second power supply, which is then output to the external IO module. The voltage values ​​of the first reference power supply and the second reference power supply are both 12V, and the voltage values ​​of the first power supply and the second power supply are both 3.3V.

10. The EtherCAT communication circuit based on a digital isolator according to claim 2, characterized in that, The Ethernet connector uses the HR911205C chip; The pin corresponding to the A_1P / RXP signal of the ABCC_B40 chip is connected to the pin corresponding to the A_1P / RXP signal of the HR911205C chip. The pin corresponding to the A_1CEN / SDA signal of the ABCC_B40 chip is connected to the pin corresponding to the A_1CEN / SDA signal of the HR911205C chip, and then connected to the ground of the signal layer through a decoupling capacitor. The pin corresponding to the A_1N / RXN signal of the ABCC_B40 chip is connected to the pin corresponding to the A_1N / RXN signal of the HR911205C chip. The pin corresponding to the A_2P / SDP signal of the ABCC_B40 chip is connected to the pin corresponding to the A_2P / SDP signal of the HR911205C chip. The pin corresponding to the A_2CEN / SCL signal of the ABCC_B40 chip is connected to the pin corresponding to the A_2CEN / SCL signal of the HR911205C chip, and then connected to the ground of the signal layer through a decoupling capacitor. The pin corresponding to the A_2N / SDN signal of the ABCC_B40 chip is connected to the pin corresponding to the A_2N / SDN signal of the HR911205C chip. The pin corresponding to the B_1P / RXP signal of the ABCC_B40 chip is connected to the pin corresponding to the B_1P / RXP signal of the HR911205C chip. The pin corresponding to the B_1CEN / SDA signal of the ABCC_B40 chip is connected to the pin corresponding to the B_1CEN / SDA signal of the HR911205C chip, and then connected to the ground of the signal layer through a decoupling capacitor. The pin corresponding to the B_1N / RXN signal of the ABCC_B40 chip is connected to the pin corresponding to the B_1N / RXN signal of the HR911205C chip. The pin corresponding to the B_2P / SDP signal of the ABCC_B40 chip is connected to the pin corresponding to the B_2P / SDP signal of the HR911205C chip. The pin corresponding to the B_2CEN / SCL signal of the ABCC_B40 chip is connected to the pin corresponding to the B_2CEN / SCL signal of the HR911205C chip, and then connected to the ground of the signal layer through a decoupling capacitor. The pin corresponding to the B_2N / SDN signal of the ABCC_B40 chip is connected to the pin corresponding to the B_2N / SDN signal of the HR911205C chip.

11. The EtherCAT communication circuit based on a digital isolator according to claim 8, characterized in that, The circuit includes a multilayer PCB board, with the ground of the signal layer and the ground of the power layer located in different layers of the PCB board to achieve separation of the signal layer and the power layer.

12. The EtherCAT communication circuit based on a digital isolator according to claim 10, characterized in that, The pin pairs corresponding to the A_1P / RXP signals of the ABCC_B40 chip and the pin pairs corresponding to the A_1N / RXN signals of the HR911205C chip are wired with equal length and equal spacing. The pin pairs corresponding to the A_2P / SDP signals of the ABCC_B40 chip and the pin pairs corresponding to the A_2N / SDN signals of the HR911205C chip are wired with equal length and equal spacing. The pin pairs corresponding to the B_1P / RXP signals and the pin pairs corresponding to the B_1N / RXN signals of the ABCC_B40 chip and the HR911205C chip are wired with equal length and equal spacing. The pin pairs corresponding to the B_1N / RXN signals and the pin pairs corresponding to the B_2N / SDN signals of the ABCC_B40 chip and the HR911205C chip are wired with equal length and equal spacing. The error in the trace length is less than 5mm.

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