Intelligent switch based on sense arithmetic position SOC chip

Abstract

The utility model discloses an intelligent switch based on feeling and calculating position SOC chip, include: SOC chip, power unit, current sampling circuit, voltage sampling circuit, open and close mechanism, first frequency selection filter circuit, RS485 circuit, HPLC analog front end peripheral circuit and HRF radio frequency front end peripheral circuit, the SOC chip is connected with power unit, current sampling circuit, voltage sampling circuit, open and close mechanism, first frequency selection filter circuit, RS485 circuit, HPLC analog front end peripheral circuit and HRF radio frequency front end peripheral circuit respectively. The utility model solves the technical problem that the internal circuit structure of existing intelligent switch is complex, leads to poor heat dissipation and big communication delay and low reliability.

Description

Technical Field

[0001] This utility model relates to the field of intelligent power equipment technology, and in particular to an intelligent switch based on a sensing and computing SOC chip. Background Technology

[0002] In modern power systems, medium- and low-voltage distribution networks serve as crucial links in power transmission and distribution, and the intelligent upgrading of their equipment has become an industry trend. Intelligent switches, as core control devices in medium- and low-voltage distribution systems, undertake important functions such as circuit on / off control, energy metering, and status monitoring. With the increasing demands of smart grids on power equipment functions, intelligent switches not only need to possess traditional mechanical switching functions but also need to integrate multiple intelligent functions such as energy metering, communication, positioning, and management.

[0003] However, the current development of smart switch technology faces many challenges. From a hardware perspective, the installation location and specifications of existing smart switches are mostly still designed based on the needs of traditional mechanical switches, and the internal space layout does not fully consider the circuit expansion requirements after intelligent upgrades. When a large number of circuit modules are added to achieve intelligent functions, the internal space of the switch becomes extremely crowded. Taking traditional smart switches as an example, after adding modules such as power metering, HPLC, and HRF communication, the density of internal circuit components more than doubles. This space congestion directly leads to a decrease in heat dissipation performance. Due to the tight arrangement of circuit components, heat is difficult to dissipate effectively, causing the internal operating temperature of the switch to rise. This not only affects the service life of circuit components but may also cause circuit failures and even safety hazards. Inter-chip communication is susceptible to external interference, resulting in poor overall operational stability. At the same time, the crowded circuit layout also makes it difficult to achieve effective electrical isolation, and electromagnetic interference is easily generated between different functional circuits, reducing the stability and reliability of switch operation.

[0004] In terms of functional implementation, most of the current smart switches' functions such as power metering, communication (HPLC and HRF), positioning, and management are implemented using discrete chips. While this discrete device solution meets the functional requirements to some extent, it has obvious drawbacks. On the one hand, the use of multiple discrete chips increases the complexity and size of the circuit, further exacerbating the problem of limited internal space in the switch. On the other hand, the discrete chip solution has high power consumption, and the power consumption generated by multiple chips operating independently is superimposed, leading to an increase in overall energy consumption. In addition, the increased number of connection lines between discrete chips also increases signal transmission loss and the risk of interference. In particular, the HPLC communication management chip and the HRF communication management chip use off-chip low-speed interfaces for communication with the main control chip. In addition to being susceptible to interference, the communication speed between chips is as low as 1kbps to 5Mbps, which seriously affects the success rate in high-frequency communication scenarios.

[0005] Therefore, there is an urgent need to propose a smart switch based on a sensing and computing SOC chip to solve the technical problems of complex internal circuit structure of existing smart switches, which leads to poor heat dissipation, large communication delay and low reliability. Utility Model Content

[0006] The main purpose of this invention is to propose an intelligent switch based on a sensing and communication SOC chip, which aims to solve the technical problems of existing intelligent switches having complex internal circuit structures, resulting in poor heat dissipation, large communication delays, and low reliability.

[0007] To achieve the above objectives, this utility model provides an intelligent switch based on a sensing-computing-pass-position SOC chip, wherein the intelligent switch based on the sensing-computing-pass-position SOC chip includes:

[0008] The system includes a SOC chip, a power supply unit, a current sampling circuit, a voltage sampling circuit, a circuit breaker mechanism, a first frequency selective filter circuit, an RS485 circuit, an HPLC analog front-end peripheral circuit, and an HRF radio frequency front-end peripheral circuit. The SOC chip is connected to the power supply unit, the current sampling circuit, the voltage sampling circuit, the circuit breaker mechanism, the first frequency selective filter circuit, the RS485 circuit, the HPLC analog front-end peripheral circuit, and the HRF radio frequency front-end peripheral circuit, respectively.

[0009] The power supply unit is used to convert the high-voltage AC power of the power distribution line into low-voltage DC power.

[0010] The current sampling unit is used to convert the current of the three-phase line and the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip.

[0011] The voltage sampling unit is used to convert the voltage of the three-phase line relative to the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip.

[0012] The opening and closing mechanism is used to perform the opening / closing operation of the SOC chip on the power distribution line, and to feed back the opening / closing status of the opening and closing mechanism to the SOC chip.

[0013] The first frequency-selective filtering circuit is used to filter the signals transmitted by the BeiDou satellites received by the antenna;

[0014] The RS485 circuit is used to enable communication with external devices equipped with an RS485 interface.

[0015] The peripheral circuit of the HPLC simulation front end is used to filter out the HPLC communication frequency band signal from the power line signal and input it into the SOC chip, or to amplify the weak HPLC communication signal output by the SOC chip, couple it to the power line and amplify the signal.

[0016] The HRF radio frequency front-end peripheral circuit is used for rapid switching of radio frequency transmit / receive modes, amplifies the weak HRF communication signal output by the SOC chip, converts the electrical signal into electromagnetic wave radiation through the antenna, or receives spatial electromagnetic waves and converts them into electrical signals, and filters the HRF operating frequency band signal input to the SOC chip.

[0017] In one preferred embodiment, the SOC chip includes a processing core, a storage unit, a power management unit, a clock unit, and a DMA controller; the processing core is connected to the storage unit, the power management unit, the clock unit, and the DMA controller via a system bus.

[0018] In one preferred embodiment, the SOC chip includes an ASIC unit for power metering and power quality analysis; the ASIC unit consists of a programmable gain amplifier, a digital signal processor, a power calculation engine, and a harmonic analysis module.

[0019] In one preferred embodiment, the SOC chip includes a BeiDou baseband processing unit, which is connected to a first frequency selective filtering circuit.

[0020] In one preferred embodiment, the SOC chip includes an HRF baseband processing unit, which is connected to the HRF radio frequency front-end peripheral circuit.

[0021] In one preferred embodiment, the SOC chip includes an HPLC baseband processing unit, which is connected to the peripheral circuitry of the HPLC simulation front end.

[0022] In one preferred embodiment, the peripheral circuit of the HPLC simulation front end includes a second frequency-selective filter circuit, a first power amplifier circuit, and a signal coupling circuit; one end of the signal coupling circuit is connected to a power line, and the other end of the signal coupling circuit is connected to the second frequency-selective filter circuit and the first power amplifier circuit respectively, and both the second frequency-selective filter circuit and the first power amplifier circuit are connected to the SOC chip.

[0023] In one preferred embodiment, the HRF radio frequency front-end peripheral circuit includes a transmit / receive switching circuit, a third frequency selective filtering circuit, a second power amplifier circuit, and an antenna; the antenna is connected to the third frequency selective filtering circuit and the second power amplifier circuit respectively, the third frequency selective filtering circuit and the second power amplifier circuit are both connected to the transmit / receive switching circuit, and the transmit / receive switching circuit is connected to the SOC chip.

[0024] In the above technical solution of this utility model, the intelligent switch based on the sensing-computing SOC chip includes: an SOC chip, a power supply unit, a current sampling circuit, a voltage sampling circuit, a switching mechanism, a first frequency selection filter circuit, an RS485 circuit, an HPLC analog front-end peripheral circuit, and an HRF radio frequency front-end peripheral circuit; the SOC chip is connected to the power supply unit, the current sampling circuit, the voltage sampling circuit, the switching mechanism, the first frequency selection filter circuit, the RS485 circuit, the HPLC analog front-end peripheral circuit, and the HRF radio frequency front-end peripheral circuit respectively; the power supply unit is used to convert the high-voltage AC power of the distribution line into low-voltage DC power; the current sampling unit is used to convert the current of the three-phase lines and the neutral line into voltage signals that the SOC chip can recognize, and connect the voltage signals to the ADC input interface of the SOC chip; the voltage sampling unit is used to convert the voltage of the three-phase lines relative to the neutral line into voltage signals that the SOC chip can recognize, and connect the voltage signals to the ADC input interface of the SOC chip. The signal is input to the ADC input interface of the SOC chip; the opening / closing mechanism is used to execute the opening / closing operation of the power distribution line by the SOC chip, and to feed back the opening / closing status of the opening / closing mechanism to the SOC chip; the first frequency selection filter circuit is used to filter the signal transmitted by the Beidou satellite received by the antenna; the RS485 circuit is used to realize communication with external devices equipped with RS485 interfaces; the HPLC analog front-end peripheral circuit is used to filter out the HPLC communication frequency band signal from the power line signal and input it into the SOC chip, or to amplify the weak HPLC communication signal output by the SOC chip and couple it to the power line; the HRF radio frequency front-end peripheral circuit is used for rapid switching of radio frequency transmission / reception mode, amplifying the weak HRF communication signal output by the SOC chip, converting the electrical signal into electromagnetic wave radiation through the antenna, or receiving space electromagnetic waves and converting them into electrical signals, and filtering the HRF operating frequency band signal to input to the SOC chip. This utility model solves the technical problems of the complex internal circuit structure of existing intelligent switches, resulting in poor heat dissipation, large communication delay, and low reliability.

[0025] In this invention, a highly integrated SOC chip with an integrated multi-functional module is used to replace the multiple discrete chips used in traditional smart switches to realize functions such as power metering, HPLC communication, HRF communication, positioning, and management. This integrated design fundamentally simplifies the circuit structure of the smart switch and solves the problems of poor signal integrity, slow communication speed between chips, high power consumption, space congestion, poor heat dissipation, and insufficient electrical isolation that exist in discrete device solutions.

[0026] In this invention, the intelligent switch integrates three communication modules—HPLC, HRF, and RS485—to construct a triple communication redundancy system. The three communication channels communicate within the SOC via an on-chip bus, reducing latency by two orders of magnitude compared to the low-speed inter-chip interface communication of discrete chip solutions. Simultaneously, through adaptive switching, the three channels automatically switch or simultaneously maintain two or three channels online, ensuring fast and reliable data transmission. Compared to the original communication method, communication reliability is improved by more than 90%.

[0027] This invention incorporates positioning and timing functions to facilitate daily inspections, maintenance, management, and fault location; determining the accurate location of smart switches optimizes operation and maintenance plans and resource allocation, improving operation and maintenance efficiency; and the introduction of BeiDou precise time synchronization ensures that the operation time of each switch is accurately synchronized, improving fault location and isolation efficiency. At the same time, it provides a unified time reference for power grid operation status analysis, ensuring power supply reliability.

[0028] In this invention, the SOC chip integrates SRAM and OTP storage and features scalable storage. By reserving expansion interfaces or employing specific storage expansion technologies, users can expand the data storage capacity of the smart switch according to actual needs, thereby meeting the demand for large amounts of power data storage in different application scenarios. This scalable storage design improves the adaptability and flexibility of the smart switch. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of an intelligent switch based on a sensing and computing SOC chip according to an embodiment of the present invention;

[0031] Figure 2 This is a schematic diagram of the SOC chip according to an embodiment of the present invention.

[0032] The realization of the purpose, functional features and advantages of this utility model will be further explained in conjunction with the implementation methods and with reference to the accompanying drawings. Detailed Implementation

[0033] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0034] Furthermore, in this utility model, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of those features.

[0035] Furthermore, the technical solutions of the various embodiments of this utility model can be combined with each other, but only if they are based on the ability of a person skilled in the art to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this utility model.

[0036] See Figures 1-2 According to one aspect of this utility model, this utility model provides an intelligent switch based on a sensing-computing-position SOC chip, wherein the intelligent switch based on the sensing-computing-position SOC chip includes:

[0037] The system includes a SOC chip, a power supply unit, a current sampling circuit, a voltage sampling circuit, a circuit breaker mechanism, a first frequency selective filter circuit, an RS485 circuit, an HPLC analog front-end peripheral circuit, and an HRF radio frequency front-end peripheral circuit. The SOC chip is connected to the power supply unit, the current sampling circuit, the voltage sampling circuit, the circuit breaker mechanism, the first frequency selective filter circuit, the RS485 circuit, the HPLC analog front-end peripheral circuit, and the HRF radio frequency front-end peripheral circuit, respectively.

[0038] The power supply unit is used to convert the high-voltage AC power of the power distribution line into low-voltage DC power.

[0039] The current sampling unit is used to convert the current of the three-phase line and the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip.

[0040] The voltage sampling unit is used to convert the voltage of the three-phase line relative to the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip.

[0041] The opening and closing mechanism is used to perform the opening / closing operation of the SOC chip on the power distribution line, and to feed back the opening / closing status of the opening and closing mechanism to the SOC chip.

[0042] The first frequency-selective filtering circuit is used to filter the signals transmitted by the BeiDou satellites received by the antenna;

[0043] The RS485 circuit is used to enable communication with external devices equipped with an RS485 interface.

[0044] The peripheral circuit of the HPLC simulation front end is used to filter out the HPLC communication frequency band signal from the power line signal and input it into the SOC chip, or to amplify the weak HPLC communication signal output by the SOC chip, couple it to the power line and amplify the signal.

[0045] The HRF radio frequency front-end peripheral circuit is used for rapid switching of radio frequency transmit / receive modes, amplifies the weak HRF communication signal output by the SOC chip, converts the electrical signal into electromagnetic wave radiation through the antenna, or receives spatial electromagnetic waves and converts them into electrical signals, and filters the HRF operating frequency band signal input to the SOC chip.

[0046] Specifically, in this embodiment, the SOC chip includes a processing core, a storage unit, a power management unit, a clock unit, and a DMA controller. The processing core is connected to the storage unit, power management unit, clock unit, and DMA controller via a system bus. The processing core is responsible for executing instructions, performing logical operations, and scheduling tasks. It includes a general-purpose computing core, an instruction cache (I-Cache), and a data cache (D-Cache). It interacts with memory, an ASIC unit for power metering and quality analysis, a Beidou baseband processing unit, an HPLC baseband processing unit, peripherals, and an HRF baseband processing unit via the system bus. The processing core uses a dual-core Cortex A7 processor with a 1GHz clock speed, a 64kB L1 instruction cache, a 64kB L1 data cache, and a 256kB L2 cache. The storage unit uses 256MB of DDR3 memory and 2kB of... OTP storage space; the storage unit provides high-speed temporary and persistent data storage, reducing external storage access latency; it includes volatile SRAM for temporary storage of runtime program variables, stack data, and intermediate calculation results, a key resource for ensuring efficient CPU operation and real-time response; non-volatile OTP stores startup code, with cache synchronized with main memory via the system bus, and the DMA controller directly moves data, reducing CPU intervention; the power management unit manages the SOC's internal power supply, including power monitoring, linear voltage regulation, and an ADC reference source; the linear voltage regulator is used for internal power regulation and distribution, and the ADC reference source is the reference voltage for the ADC, ensuring ADC accuracy, with a 3.3V input, a built-in LDO generating 0.9V for the computing core, 1.5V for the DDR power supply, and 1.2V for the ADC reference source; the clock unit provides a synchronous clock signal and accurate... Timing control includes timers, pulse width modulation signals, and a real-time clock (RTC). The clock unit includes one 64-bit timer, two 32-bit timers, one dedicated watchdog timer, eight PWM channels, and one RTC clock. The DMA controller supports memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers, reducing CPU load. The watchdog timer (WDT) prevents software deadlocks, and its reset time is programmable. The reset system consists of modules such as power-on reset (POR), undervoltage detection (BOR), and the watchdog timer (WDT). Its function is to ensure reliable reset of the chip in the event of power failure, program crashes, or external interference, returning each module to its initial state and ensuring stable system operation. The DMA controller is a 16-channel DMA, supporting 8 / 16 / 32 / 64-bit data widths and supporting peripheral-to-peripheral, memory-to-memory, memory-to-peripheral, and peripheral-to-memory data transfers.

[0047] Specifically, in this embodiment, the SOC chip includes an ASIC unit for power metering and power quality analysis. The ASIC unit consists of a programmable gain amplifier (PGA), a digital signal processor (DSP), a power calculation engine (such as a hardware multiplier), and a harmonic analysis module. The ASIC unit is used to acquire voltage and current signals in real time, accurately measure active / reactive power, and analyze power quality parameters such as harmonics and voltage sags, providing key data support for the smart grid. The ASIC unit includes 7 high-precision ADCs, which are 18-bit Σ-Δ ADCs with ENOB ≥ 16 bits, a sampling rate of 38.4kHz, and support for synchronous sampling. The ASIC unit acquires real-time voltage and current data from the ADCs, accurately measures active / reactive power, meets 0.5S-level metering accuracy, has a dynamic range of 12000:1, and can analyze power quality parameters such as the 52nd harmonic and voltage sag. The calculation core only needs simple configuration during the startup phase, and subsequent control is not required; the calculation results can be obtained through shared memory.

[0048] Specifically, in this embodiment, the SOC unit includes a BeiDou baseband processing unit, which is connected to a first frequency selective filtering circuit. The first frequency selective filtering circuit amplifies, filters, and down-converts the weak radio frequency signal received by the antenna, converting it into an intermediate frequency signal or digital signal suitable for processing by the BeiDou baseband processing unit in the SOC chip. The BeiDou baseband processing unit further processes the intermediate frequency signal or digital signal output by the first frequency selective filtering circuit, including signal acquisition, tracking, demodulation and decoding of navigation messages, and extracts information such as position, velocity, and time from the satellite signal. The first frequency selective filtering circuit supports B1I / B3I / GPS L1 / GLONASS L1, with a positioning accuracy of <2.5 meters.

[0049] Specifically, in this embodiment, the SOC chip includes an HPLC baseband processing unit, which is connected to the peripheral circuitry of the HPLC simulation front end. The peripheral circuitry of the HPLC simulation front end includes a second frequency-selective filter circuit, a first power amplifier circuit, and a signal coupling circuit. One end of the signal coupling circuit is connected to the electric field line, and the other end is connected to both the second frequency-selective filter circuit and the first power amplifier circuit. Both the second frequency-selective filter circuit and the first power amplifier circuit are connected to the SOC chip. When the simulation front end receives data, the HPLC data in the electric field line is extracted through the second frequency-selective filter circuit. The frequency band signal is amplified and conditioned before being converted into a digital signal. During transmission, the baseband-processed signal is converted into a frequency signal, which is then amplified by the first power amplifier circuit and injected into the power line through a signal coupling circuit. The baseband section is responsible for signal processing. During reception, it demodulates and decodes the digital signal output from the analog front end to restore the data. During transmission, it encodes and modulates the raw data to generate a signal adapted to the analog front end and coordinates the working timing of the peripheral circuits to ensure reliable communication in the complex environment of the power line. The HPLC baseband supports OFDM modulation, a physical layer rate of 10Mbps, and supports G3-PLC / PRIME / Q / GDW 1376.2.

[0050] Specifically, in this embodiment, the SOC chip includes an HRF baseband processing unit, which is connected to the HRF radio frequency front-end peripheral circuit. The HRF radio frequency front-end peripheral circuit includes a transmit / receive switching circuit, a third frequency selective filtering circuit, a second power amplifier circuit, and an antenna. The antenna is connected to the third frequency selective filtering circuit and the second power amplifier circuit, both of which are connected to the transmit / receive switching circuit, which is connected to the SOC chip. The radio frequency front-end is responsible for signal conversion and conditioning. During reception, it performs frequency selective filtering on the weak radio frequency signal captured by the antenna to remove interference noise, then amplifies it through a low-noise amplifier, and subsequently down-converts it to an intermediate frequency or baseband signal. During transmission, the baseband signal from the baseband front-end is up-converted to the radio frequency band, and the power is increased by a power amplifier circuit to meet the requirements of long-distance transmission. Finally, it is radiated out through the antenna. The baseband front-end focuses on signal processing and protocol parsing. During reception, it demodulates, decodes, and filters the signal output from the radio frequency front-end to recover the original data. During transmission, the data to be transmitted is encoded and modulated to be converted into a baseband signal suitable for processing by the radio frequency front-end. The transmit / receive switching circuit accurately switches the transmit and receive states under the coordinated control of the baseband and radio frequency front-ends to avoid transmit and receive signal conflicts and ensure smooth communication. The HRF radio frequency supports the 470MHz to 510MHz frequency band, with a single frequency transmit power of 20dBm (adjustable) and a receive sensitivity of -110dBm.

[0051] Specifically, the various module circuits in the SOC chip are connected via a system bus or a peripheral bus. The system bus clock is 400MHz, and the peripheral bus clock is 100MHz, supporting 8 / 16 / 32-bit wide transmission. The system bus serves as a high-speed backbone for rapid data transfer between the processing core, internal storage, power management, clock, system control, Beidou baseband processing unit, HPLC baseband processing unit, HRF baseband processing unit, ASIC unit, and peripheral bus. The peripheral bus connects to external memory, USB, UART, SPI, and I... 2 Low-speed interfaces such as C and GPIO are interconnected through a bridge to achieve layered collaboration between internal high-speed, high-bandwidth data exchange and external low-speed, low-bandwidth data interaction.

[0052] Specifically, in this embodiment, the power supply unit provides a stable and reliable power supply for the SOC chip and peripheral devices. It adopts a multi-stage conversion architecture and includes functional circuits such as surge protection, EMI filter, rectifier bridge, PFC circuit, DC-DC converter, overcurrent protection, and overvoltage protection. The surge protection uses an MOV varistor and a gas discharge tube. The EMI filter uses a common-mode choke and an X2 safety capacitor. The rectifier bridge uses a GBU1006 rectifier bridge (10A / 600V) with a surge current withstand capability >200A. The PFC circuit uses a Boost topology, and the controller is an 8240SNE with an efficiency >92%. The main power supply for the DC-DC converter is a TPS54339 power supply with 28V input, 3.3V / 3A output, and an efficiency >90%. The isolation power supply for the DC-DC converter is a JWQ3510 power supply. Overcurrent protection uses a resettable fuse, and overvoltage protection uses a TL431 precision reference source and a MOSFET switching circuit with a response time <10μs.

[0053] Specifically, in this embodiment, the current sampling circuit uses a current transformer as its core to convert the current flowing through the three-phase lines and the neutral line into a voltage signal that the SOC can recognize. The converted voltage signal is then connected to the ADC input interface of the SOC chip. The current sampling circuit consists of a current transformer, a load circuit, and a filter network. The current transformer is an electromagnetic current transformer with a transformation ratio of 8000:1 and a rated current of 400A. The load resistor is a 10Ω±0.1% precision resistor that converts the current signal into a voltage signal. The filter network is a second-order Sallen-Key low-pass filter with a cutoff frequency of 10kHz and a stopband attenuation of >40dB / dec.

[0054] Specifically, in this embodiment, the voltage sampling circuit uses a voltage transformer as its core to convert the voltage of the three phase lines relative to the neutral line into a voltage signal that the SOC chip can recognize. The converted voltage signal is then connected to the ADC input interface of the SOC chip. The voltage sampling circuit consists of a voltage transformer, a voltage divider network, and a protection network. The voltage transformer is a TCSPT204 transformer with a transformation ratio of 2mA:2mA. The voltage divider network is composed of high-precision resistor voltage dividers. The protection circuit includes a bidirectional diode BAV99 and a series LC low-pass filter circuit. The bidirectional diode is used to limit the input voltage range to ±1.4V. The series LC low-pass filter circuit is used to filter out high-frequency interference signals above 100kHz.

[0055] Specifically, in this embodiment, the HPLC simulation front-end peripheral circuit is used to receive and transmit power line signals; the transmitting channel consists of a power amplifier, an impedance matching network, and a signal coupling circuit. The power amplifier is a PA42 high-voltage operational amplifier, powered by ±15V, with an output power of 2W. The impedance matching network is a π-type network with L = 22μH, C1 = 470pF, C2 = 1nF, and a matching impedance of 50Ω. The signal coupling circuit uses an ETD29 / 15 / 9 ferrite core high-frequency transformer with a primary-to-secondary ratio of 1:5, a resonant frequency of 13.56MHz, and an AC withstand voltage >4kV between the primary and secondary sides. The receiving and transmitting channels share the same circuit. The receiving channel consists of a signal coupling circuit, a preamplifier, and a programmable... The system includes a programmable gain amplifier, a bandpass filter, and an automatic gain control circuit. The preamplifier is an AD8099, a low-noise, high-speed operational amplifier with a noise density of 1.2 nV / √Hz. The programmable gain amplifier is an MCP6S26, an 8-channel, programmable gain amplifier with a gain range of 1-64. The bandpass filter is an 8th-order Chebyshev filter with a passband of 1.6-30MHz and ripple <0.5dB. The automatic gain control circuit is based on the AD8367 AGC circuit, with a dynamic range >70dB. The signal coupling circuit includes a coupling transformer and a surge protection circuit. The surge protection circuit shares an MOV varistor and a gas discharge tube with the power supply unit for surge protection.

[0056] Specifically, in this embodiment, the HRF radio frequency front-end peripheral circuit is used to realize the transmission and reception of wireless signals at a frequency of 470MHz. The second power amplifier circuit adopts an RF5110 amplifier, a dedicated 470MHz PA, a three-stage amplification architecture, a gain of 30dB, a saturated output power of +30dBm, a linearity OIP3 > 40dBm, and an efficiency > 50%. The transmit / receive switching circuit adopts an HMC1047 single-pole double-throw switch, operating in the 470MHz band, with a switching time < 300ns, an insertion loss < 0.3dB, and an isolation > 45dB. The antenna frequency range is 470–486MHz, the input impedance is 50 ohms, the VSWR is < 2.0, and the gain is > 2dBi. If the smart switch is installed in an unshielded environment, a short rod antenna can be used, with the antenna body fixed to the smart switch housing. If installed in a shielded environment (e.g., inside a sealed metal box), a long feeder antenna is required, with the antenna body placed outside the shielded environment.

[0057] Specifically, in this embodiment, the first frequency-selective filtering circuit is connected to the antenna, which is responsible for receiving signals transmitted by BeiDou satellites. The RF filter suppresses out-of-band interference (such as spurious signals and noise) and improves receiving sensitivity. The filtered signal is input to the RF front-end of the BeiDou positioning unit of the SOC chip. The first frequency-selective filtering circuit includes an RF front-end circuit, a bandpass filter, and a matching network circuit. The RF front-end uses a MAX2769 multi-band GNSS RF front-end, integrating an LNA, mixer, and IF amplifier. The bandpass filter uses a ceramic filter with a center frequency of 1575.42MHz, a bandwidth of 20MHz, and an insertion loss of <2dB. The matching network circuit uses a π-type network, composed of inductors, capacitors, and resistors. The antenna has a frequency range of 1561-1576MHz, an input impedance of 50Ω, a VSWR of <2.0, and a gain of >32dBi. If the smart switch is installed in an unshielded environment, an active patch antenna can be used. If it is installed in a shielded environment (e.g., inside a sealed metal box), a long feeder antenna must be used, placing the antenna body outside the shielded environment.

[0058] Specifically, in this embodiment, the intelligent switch based on the sensing-computing SOC chip further includes an RS485 circuit; the RS485 circuit is connected to the SOC chip and is used to communicate with external devices equipped with an RS485 interface; the RS485 circuit includes an isolation drive circuit, an RS485 transceiver, and an interface protection circuit; the isolation drive circuit uses a DS-HK816D optocoupler with an isolation voltage of 5kV AC and supports a conversion speed of 1Mbps; the RS485 transceiver uses a TPT485E transceiver, meets the EIA-485 standard, supports a rate of 500kbps, and has built-in ±18kV HBM electrostatic protection; the interface protection circuit uses an SMBJ5.0CA transient suppressor with an operating voltage of 6.5V and transient power dissipation >600W.

[0059] Specifically, in this embodiment, the smart switch based on the sensing and computing SOC chip further includes a Bluetooth communication circuit, which is connected to the SOC chip. The Bluetooth communication circuit is used to communicate with external devices equipped with Bluetooth interfaces. The Bluetooth communication circuit includes a Bluetooth chip and an antenna. The Bluetooth chip is an nRF52832 model, which supports Bluetooth 5.0 and Bluetooth Low Energy protocols, has excellent power consumption advantages, and a UART interface. The antenna structure is formed on the PCB by etching metal layers, which has high integration, low cost, and is compatible with Bluetooth frequency bands. Signal transmission and reception are achieved by optimizing the shape (such as inverted F type or monopole type).

[0060] Specifically, in this embodiment, the smart switch based on the sensing-computing SOC chip further includes a remote signaling circuit, a button circuit, and an indicator light circuit. The remote signaling circuit, button circuit, and indicator light circuit are all connected to the SOC chip. The remote signaling circuit is used to monitor whether the external switch is closed. The remote signaling circuit uses a DS-HK816D optocoupler with an isolation voltage of 5kV AC. The button circuit converts the pressed / released state of the button on the smart switch into a high or low level that the SOC chip can recognize. The indicator light circuit converts the high or low level output by the SOC chip into the on / off state of the indicator light on the smart switch body.

[0061] Specifically, in this embodiment, the SOC chip includes an external storage interface and an external communication interface. The external storage interface is used for connecting to external memory to expand external storage when the internal memory capacity is insufficient. The external communication interface includes a USB interface, a UART interface, an SPI interface, and an I / O interface. 2 The C interface and GPIO interface are used to communicate with external devices, collect information, and control external devices.

[0062] Specifically, in this embodiment, the smart switch based on the sensing and computing SOC chip also includes an external interface, which provides corresponding external connectivity capabilities. For example, RS485 is used for networking and communication with other local devices; Bluetooth supports near-field configuration and debugging via a mobile APP, facilitating on-site maintenance and communication with nearby Bluetooth-enabled devices; USB is used for program upgrades and big data export; GPIO connects to the remote signaling circuit, providing monitoring of the external switch status of the smart switch; GPIO connects to buttons and indicator lights, providing local human-machine interaction functions, supporting parameter setting and status display, etc.

[0063] Specifically, in this embodiment, the SOC chip is combined with the hardware circuit of the smart switch, providing a hardware foundation for the realization of the smart switch's functions. For example, in measurement functions, the SOC's internal processing core, internal storage, high-precision ADC, and ASIC unit for power metering and quality analysis, combined with external power supply, current sampling circuit, and voltage sampling circuit, acquire voltage / current signals in real time, accurately measure active / reactive energy, and analyze power quality parameters such as harmonics and voltage sags, providing key data support for the smart grid. In data freezing functions, the SOC chip's internal processing core and internal storage, combined with external power supply and external memory, freeze and store electrical parameters such as voltage, current, energy, and power quality based on the measurement functions. In positioning and time synchronization functions, by receiving signals from the BeiDou satellite, the smart switch's latitude, longitude, and altitude information are monitored in real time, maintaining precise synchronization between the smart switch's RTC clock and BeiDou time synchronization. In event recognition and recording functions, the SOC chip's internal processing core and internal storage, combined with external power supply, external memory, and opening / closing mechanism, record events such as power outages, opening / closing, overcurrent, overvoltage, current imbalance, undervoltage, voltage imbalance, phase loss, and zeroing, as well as the time, cause, and phase of each event. Features include: data acquisition, event reporting, remote control, and status monitoring; uplink communication via HPLC, HRF, or RS485 with upper-level devices (transformer terminals, concentrators, fusion terminals, etc.); built-in uplink communication management with HPLC, HRF, and RS485 channels acting as backups, allowing two or three channels to be online simultaneously to ensure communication stability and bandwidth; local communication via RS485, Bluetooth, etc., with local meters, sensors, maintenance terminals, etc., for data acquisition, status monitoring, and maintenance functions; line opening / closing control and status monitoring via the SOC chip through external interfaces and the opening / closing mechanism, and monitoring of the opening / closing status of the mechanism; user interaction via uplink, local, or button input, and access to device status information via uplink, local, or indicator lights; and maintenance and upgrade functions via uplink, local, or USB interfaces.

[0064] Specifically, in this embodiment, the operation of the smart switch based on the sensing and computing SOC chip includes the following steps: Powering on the system, starting the main thread, configuring the operating parameters of each unit circuit, initializing the shared database, and monitoring the sub-thread status; constructing the first sub-thread: BeiDou positioning and timing; periodically acquiring current latitude, longitude, altitude information, and clock information; reading positioning information from the device's shared database and determining whether the latitude, longitude, and altitude information in the current database are consistent with BeiDou positioning; if inconsistent, reporting an event and updating the shared database; reading the device's RTC clock and determining whether the current RTC clock is consistent with BeiDou timing; if inconsistent, synchronizing the device's RTC clock with the clock information; constructing the second sub-thread: power metering and quality analysis; periodically reading ASIC unit metering and power... The system performs the following steps: 1. Analyzes quality data and updates the shared database; 2. Determines if any events need to be reported, and if so, reports the events and updates the shared database; 3. Determines if the circuit breaker's open / close status needs to be changed, and if so, performs the open / close operation and updates the shared database; 4. Constructs a third sub-thread: uplink communication; 5. Detects the quality of the HPLC, HRF, and RS485 uplink channels, selects one or more optimal channels based on the service type to establish a communication channel with the upper-layer equipment, and responds to upper-layer equipment communication in real time; 6. Determines if the shared database needs to be updated, and if so, updates the shared database; 7. Constructs a fourth sub-thread: local communication, status monitoring, and indication; 8. Responds to external interface communication in real time, monitors the status acquisition interface, outputs status indications; 9. Determines if the shared database needs to be updated, and if so, updates the shared database.

[0065] Specifically, in this embodiment, uplink communication includes: initializing channel parameters, configuring hardware parameters and initializing the protocol stack for the HPLC, HRF, and RS485 channels, establishing a basic communication link, and loading preset service priorities and weighting coefficients for the health of each channel; real-time monitoring of channel status, real-time acquisition of physical layer and link layer parameters for the HPLC, HRF, and RS485 channels, and calculation of the health of each channel; dynamically deciding on the priority channel based on service type, classifying service levels according to data type, and selecting the optimal transmission channel based on channel health and service requirements; and information transmission and result verification, completing data transmission based on the optimal transmission channel. Encapsulation, transmission, acknowledgment, and retransmission control; triggering a self-healing mechanism in case of anomalies; if any channel fails to transmit N times consecutively, it is marked as a suspicious fault and triggers deep detection; after confirming the fault, the channel is added to the blacklist and a blacklist timer is set, during which selection is prohibited, and detection is automatically resumed after the timeout; in case of emergency service failure, HPLC, HRF, and RS485 channels are forcibly enabled for polling transmission to ensure information reporting; decision parameters are optimized by learning from historical data, parameter optimization is performed, the success rate of each channel under different time periods and different service types is statistically analyzed, the weight coefficient of health is updated, and the switching sensitivity is automatically reduced for frequently switching stations.

[0066] Specifically, in this embodiment, by employing the aforementioned highly integrated SOC chip, the intelligent switch of this invention can replace the original circuit system composed of multiple discrete chips, significantly reducing the number of peripheral circuits. Correspondingly, the low-speed inter-chip connections (1kbps~5Mbps) of the original discrete chip solution are replaced by on-chip bus connections (200Mbps~400Mbps). This design greatly improves signal integrity and signal transmission speed, reduces the overall power consumption of the intelligent switch, lowers material and manufacturing costs, and simplifies product development. Because the on-chip signal anti-interference capability is significantly improved compared to off-chip interconnection, and the reduction in components and power consumption significantly improves the inherent reliability of the intelligent switch, a large amount of internal space is freed up, making the internal layout of the switch more reasonable, effectively improving heat dissipation performance, strengthening electrical isolation, and improving the operational stability and reliability of the intelligent switch.

[0067] The above are merely preferred embodiments of this utility model and do not limit the patent scope of this utility model. Any equivalent structural transformations made based on the inventive concept of this utility model and the contents of this utility model specification and drawings, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this utility model.

Claims

1. A smart switch based on a sensing-computing SOC chip, characterized in that, include: The system includes a SOC chip, a power supply unit, a current sampling circuit, a voltage sampling circuit, a circuit breaker mechanism, a first frequency-selective filter circuit, an RS485 circuit, an HPLC analog front-end peripheral circuit, and an HRF radio frequency front-end peripheral circuit. The SOC chip is connected to the power supply unit, the current sampling circuit, the voltage sampling circuit, the circuit breaker mechanism, the first frequency-selective filter circuit, the RS485 circuit, the HPLC analog front-end peripheral circuit, and the HRF radio frequency front-end peripheral circuit, respectively. The power supply unit is used to convert the high-voltage AC power of the power distribution line into low-voltage DC power. The current sampling unit is used to convert the current of the three-phase line and the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip. The voltage sampling unit is used to convert the voltage of the three-phase line relative to the neutral line into a voltage signal that the SOC chip can recognize, and to connect the voltage signal to the ADC input interface of the SOC chip. The opening and closing mechanism is used to perform the opening / closing operation of the SOC chip on the power distribution line, and to feed back the opening / closing status of the opening and closing mechanism to the SOC chip. The first frequency-selective filtering circuit is used to filter the signals transmitted by the BeiDou satellites received by the antenna; The RS485 circuit is used to enable communication with external devices equipped with an RS485 interface. The peripheral circuit of the HPLC simulation front end is used to filter out the HPLC communication frequency band signal from the power line signal and input it into the SOC chip, or to amplify the weak HPLC communication signal output by the SOC chip, couple it to the power line and amplify the signal. The HRF radio frequency front-end peripheral circuit is used for rapid switching of radio frequency transmit / receive modes, amplifies the weak HRF communication signal output by the SOC chip, converts the electrical signal into electromagnetic wave radiation through the antenna, or receives spatial electromagnetic waves and converts them into electrical signals, and filters the HRF operating frequency band signal input to the SOC chip.

2. The intelligent switch based on a sensing-computing SOC chip according to claim 1, characterized in that, The SOC chip includes a processing core, a memory unit, a power management unit, a clock unit, and a DMA controller; the processing core is connected to the memory unit, the power management unit, the clock unit, and the DMA controller via a system bus.

3. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The SOC chip includes an ASIC unit for power metering and power quality analysis; the ASIC unit consists of a programmable gain amplifier, a digital signal processor, a power calculation engine, and a harmonic analysis module.

4. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The SOC chip includes a BeiDou baseband processing unit, which is connected to a first frequency selective filter circuit.

5. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The SOC chip includes an HRF baseband processing unit, which is connected to the HRF radio frequency front-end peripheral circuit.

6. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The SOC chip includes an HPLC baseband processing unit, which is connected to the peripheral circuitry of the HPLC simulation front end.

7. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The peripheral circuit of the HPLC simulation front end includes a second frequency selective filter circuit, a first power amplifier circuit, and a signal coupling circuit; one end of the signal coupling circuit is connected to the power line, and the other end of the signal coupling circuit is connected to the second frequency selective filter circuit and the first power amplifier circuit respectively. Both the second frequency selective filter circuit and the first power amplifier circuit are connected to the SOC chip.

8. A smart switch based on a sensing-computing SOC chip according to any one of claims 1-2, characterized in that, The HRF radio frequency front-end peripheral circuit includes a transmit / receive switching circuit, a third frequency selective filtering circuit, a second power amplifier circuit, and an antenna; the antenna is connected to the third frequency selective filtering circuit and the second power amplifier circuit respectively, and both the third frequency selective filtering circuit and the second power amplifier circuit are connected to the transmit / receive switching circuit, which is connected to the SOC chip.

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