State detection system and vehicle

Abstract

Disclosed are a state detection system and a vehicle comprising the same. The state detection system comprises: at least one set of sampling circuits, each of the at least one set of sampling circuits being electrically connected to a corresponding one of the plurality of components and configured to output a first signal when the corresponding one of the plurality of components is working normally and output a second signal when the corresponding one of the plurality of components is not working normally; a plurality of sub-processing circuits in parallel with each other and each of the plurality of sub-processing circuits being electrically connected to a corresponding set of sampling circuits; and one main processing circuit connected to the plurality of sub-processing circuits in a single-line communication manner and configured to send a query command to the plurality of sub-processing circuits at the beginning of each query period, so that the plurality of sub-processing circuits respectively asynchronously send the first signal and / or the second signal to the one main processing circuit after synchronously receiving the query command.

Description

Technical Field

[0001] This utility model relates to the field of mechatronics, and more specifically to a condition detection system and a vehicle including the condition detection system. Background Technology

[0002] As vehicles become increasingly intelligent, when a malfunction occurs, the vehicle or its sub-components need to report the fault status, which is then displayed on the dashboard in some form. This allows maintenance personnel to quickly identify the problematic component and its location, facilitating rapid troubleshooting. For example, intelligent central electrical boxes utilize fuses and relays. When a fuse or relay fails, a detection circuit is used to identify and report which fuse or relay is faulty, enabling maintenance personnel to replace it.

[0003] To enhance condition detection capabilities, it is necessary to set up as many sampling circuits as possible. However, in existing detection schemes, communication data transmission conflicts can occur when there are many sampling circuits. Furthermore, existing sampling circuits occupy a certain amount of space on the printed circuit board, and the space reserved for sampling circuits on the printed circuit board is limited. This not only restricts the number of sampling circuits that can be set up simultaneously, but also increases the cost of condition detection.

[0004] Therefore, there is an urgent need to improve existing state detection schemes to provide a state detection system that can resolve communication data transmission conflicts and reduce overall space occupation. Utility Model Content

[0005] This utility model aims to solve at least one aspect of the above-mentioned problems.

[0006] According to one aspect of the present invention, a state detection system is provided for detecting multiple components in a vehicle, comprising: at least one set of sampling circuits, each sampling circuit in the at least one set of sampling circuits being electrically connected to a corresponding component among the multiple components and configured to output a first signal when the corresponding component is working normally and to output a second signal when the corresponding component is not working normally; multiple sub-processing circuits connected in parallel to each other, each of the multiple sub-processing circuits being electrically connected to a corresponding set of sampling circuits; and a main processing circuit connected to the multiple sub-processing circuits via single-wire communication and configured to send a query command to the multiple sub-processing circuits at the beginning of each query cycle, such that after synchronously receiving the query command, the multiple sub-processing circuits asynchronously send the first signal and / or the second signal to the main processing circuit, respectively.

[0007] According to one aspect of the present invention, each sub-processing circuit is configured to send a first signal and / or a second signal after a delay time following the receipt of the query command and before the delay time of the next sub-processing circuit, and satisfying: T dN = (N-1)×A, where T dN Let A be the delay time of the Nth sub-processing circuit, where N is the identifier of the Nth sub-processing circuit and is ≥1, and A is the time constant.

[0008] According to one aspect of the present invention, the state detection system further includes: a plurality of sub-driving circuits, each of the plurality of sub-driving circuits being operatively connected to and driving a corresponding sub-processing circuit; and a main driving circuit being operatively connected to and driving the main processing circuit, and communicatively connected to the plurality of sub-driving circuits to transmit a first signal and / or a second signal received from the plurality of sub-driving circuits to the main processing circuit.

[0009] According to one aspect of the present invention, each sub-processing circuit is provided with a sub-processing transmitting port for transmitting a first signal and / or a second signal and a sub-processing receiving port for receiving the query command; and each sub-driving circuit is provided with a sub-driving transmitting port for transmitting the query command to the sub-processing receiving port of the corresponding sub-processing circuit and a sub-driving receiving port for receiving the first signal and / or the second signal from the sub-processing transmitting port of the corresponding sub-processing circuit.

[0010] According to one aspect of the present invention, the main processing circuit is provided with a main processing sending port for sending the query command and a main processing receiving port for receiving the first signal and / or the second signal; and the main driving circuit is provided with a main driving sending port for sending the first signal and / or the second signal to the main processing receiving port and a main driving receiving port for receiving the query command from the main processing sending port.

[0011] According to one aspect of the present invention, the main drive circuit is provided with a main drive bus port for communication connection; and the plurality of sub-drive circuits are each provided with a sub-drive bus port for communication connection with the main drive bus port.

[0012] According to one aspect of the present invention, each sub-processing circuit is configured to generate a check value upon receiving the query command, and to compress a first signal and / or a second signal from the corresponding set of sampling circuits, the check value, and the identifier of each sub-processing circuit into a data packet for transmission to the main processing circuit.

[0013] According to one aspect of the present invention, the main processing circuit is configured to check the check value after receiving the data packet, and after determining that the check value is correct, confirm the sending of the data packet according to the identification code of the secondary processing circuit and obtain the first signal or the second signal of each sampling circuit in the corresponding set of sampling circuits.

[0014] According to one aspect of the present invention, each sub-processing circuit includes a plurality of pull-up resistors, each of the plurality of pull-up resistors being electrically connected to a corresponding sampling circuit in the corresponding set of sampling circuits to pull the first signal high to a high level, while the second signal is at a low level.

[0015] According to one aspect of the present invention, each sampling circuit includes a switching component, the output terminal of which is electrically connected to a corresponding pull-up resistor among the plurality of pull-up resistors.

[0016] According to one aspect of the present invention, the switching component includes at least one of the following: a diode, a bipolar junction transistor, a field-effect transistor, and an insulated gate bipolar transistor.

[0017] According to one aspect of the present invention, a portion of the plurality of components is located in a central electrical box, and another portion of the plurality of components is located in other equipment of the vehicle.

[0018] According to one aspect of the present invention, the plurality of components include a fuse and / or a relay.

[0019] According to another aspect of the present invention, a vehicle is provided, including a condition detection system according to any of the foregoing aspects. Attached Figure Description

[0020] The accompanying drawings, which are incorporated herein and form a part of this specification, illustrate the present invention and, together with the description, further serve to explain the principles of the present invention and enable those skilled in the art to make and use the embodiments described herein.

[0021] Figure 1 This is a schematic diagram of a resistance wire, a sampling circuit and a secondary processing circuit connected together in a state detection system according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic diagram of a state detection system according to an embodiment of the present invention;

[0023] Figure 3 This is a schematic diagram illustrating the timing of communication between a plurality of sub-processing circuits and a main processing circuit according to an embodiment of the present invention;

[0024] Figure 4 This is a flowchart illustrating a first operation performed on the main processing circuit according to an embodiment of the present invention;

[0025] Figure 5 This is a flowchart illustrating a second operation performed on the sub-processing circuit according to an embodiment of the present invention; and

[0026] Figure 6 This is a block diagram of an electronic device that uses a state detection system according to an embodiment of the present invention to implement a detection method for detecting multiple components in a vehicle.

[0027] The features of this utility model will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, wherein similar reference numerals always identify corresponding elements. In the drawings, similar reference numerals generally denote identical, functionally similar, and / or structurally similar elements. Unless otherwise stated, the drawings provided throughout this application should not be construed as being drawn to scale. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0029] However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present invention. In the following detailed description, numerous specific details are set forth to provide a comprehensive understanding of the embodiments of the present invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present invention.

[0030] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of the invention. The term "comprising" as used herein indicates the presence of features, steps, or operations, but does not exclude the presence or addition of one or more other features.

[0031] When using expressions such as "at least one of A, B, and C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, and C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.). When using expressions such as "at least one of A, B, or C," the expression should generally be interpreted in accordance with the meaning commonly understood by a person skilled in the art (e.g., "a system having at least one of A, B, or C" should include, but is not limited to, systems having A alone, having B alone, having C alone, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0032] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0033] This utility model discloses a state detection system 1000 for detecting multiple components 2000 in a vehicle (not shown in the figure), a vehicle including the state detection system 1000, a detection method for detecting multiple components 2000 in the vehicle using the state detection system 1000, a computer program product for performing the detection method, and a computer-readable medium.

[0034] See Figures 1 to 2 The state detection system 1000 includes: at least one set of sampling circuits 100, and multiple secondary processing circuits C1, C2, ..., C1. N A main processing circuit 200. Chips of the same or different types can be used as secondary processing circuits C1, C2, ..., C1. N And the main processing circuit 200. Sub-processing circuits C1, C2, ..., C N It is also known as the "secondary chip", and the main processing circuit 200 is also known as the "main chip".

[0035] Each of the at least one set of sampling circuits 100 is electrically connected to a corresponding component 2000 among the plurality of components 2000 and is configured to output a first signal when the corresponding component 2000 is operating normally and a second signal when the corresponding component 2000 is not operating normally. The first signal corresponds to a first state in which the component 2000 is operating normally, and the second signal corresponds to a second state in which the component 2000 is not operating normally. By detecting whether the sampling circuit 100 outputs the first signal or the second signal, it is possible to determine whether the corresponding component 2000 is in the first state or the second state. The plurality of components 2000 includes, but is not limited to, fuses and / or relays. The sampling circuit 100 includes a switching member 110. The switching member 110 includes, but is not limited to, at least one of the following: a diode, a bipolar junction transistor, a field-effect transistor, and an insulated-gate bipolar transistor. See also Figure 2 Multiple secondary processing circuits C1, C2, ..., C N The multiple sub-processing circuits C1, C2, ..., C are connected in parallel and are... N Each sub-processing circuit is electrically connected to a corresponding set of sampling circuits 100. Each sub-processing circuit C1, C2, ..., C... N It includes multiple pull-up resistors (not shown in the figure), each of which is electrically connected to a corresponding sampling circuit 100 in a set of sampling circuits 100 to pull the first signal high and the second signal low. This makes it easy to distinguish the first signal and the second signal, and thus easy to determine whether the component 2000 is in the first state or the second state.

[0036] For ease of description, Figure 1 A simple example is shown in which a component 2000, configured as a fuse, is electrically connected to the input terminal 111 of a sampling circuit 100. Figure 1 In one embodiment, an N-channel enhancement-mode metal-oxide-semiconductor field-effect transistor (MOSFET) is used as the switching component 110. The sampling circuit 100 includes only the switching component 110 (this invention is not limited to this; other embodiments of the sampling circuit 100 may also include other electronic components such as resistors and capacitors). Therefore, the input terminal 111 of the sampling circuit 100 is also the input terminal of the switching component 110 (i.e., the gate of the N-channel enhancement-mode MOSFET). The output terminal 112 of the switching component 110 (i.e., the drain of the N-channel enhancement-mode MOSFET) is electrically connected to a corresponding pull-up resistor among the plurality of pull-up resistors. Sub-processing circuit C N Includes k connection ports P1, P2...P k See also Figure 1 In the direction of the middle, the secondary processing circuit C NThere are n connection ports P1, P2...P on the left side. n Sub-processing circuit C N The lower side has mn connection ports P n+1 P n+2 ...P m Sub-processing circuit C N There are jm connection ports P on the right side. m+1 P m+2 ...P j Sub-processing circuit C N The upper side has kj connection ports P j+1 P j+2 ...P k Each connection port P1, P2...P K Electrically connected to a corresponding pull-up resistor, allowing a sampling circuit 100 to pass through a corresponding connection port P1, P2...P K The circuit is electrically connected to a corresponding pull-up resistor, enabling a secondary processing circuit C to... N It can simultaneously detect the status of k fuses. The larger the value of k, the more powerful the secondary processing circuit C becomes. N Therefore, the stronger the detection capability of the state detection system 1000, the better. Those skilled in the art should understand that although only the fuse is shown here for ease of description, the secondary processing circuit C... N The system can simultaneously detect the status of different types of components 2000 (i.e., electronic components such as fuses and relays). Since the sub-processing circuit has k pull-up resistors (i.e., pull-up resistors are not included in the sampling circuit 100), the status detection system 1000 includes N sub-processing circuits. Therefore, the status detection system 1000 according to the embodiment of this invention can save space on the printed circuit board (PCB) for N×k pull-up resistors. The saved space can be used to arrange more sub-processing circuits, sampling circuits, or other desired functional components, thereby improving the overall performance of the printed circuit board and reducing the cost of status detection.

[0037] Furthermore, it should be noted that the multiple components 2000 are not limited to being located in one device of the vehicle, but can be distributed in multiple devices of the vehicle. For example, a portion of the multiple components 2000 may be located in the central electrical box, and another portion of the multiple components 2000 may be located in other devices of the vehicle, thereby enabling the condition detection system 1000 to expand its detection range.

[0038] See Figure 2 A main processing circuit 200 is connected to the plurality of secondary processing circuits C1, C2, ..., C3 via single-wire communication. N This makes the multiple sub-processing circuits C1, C2, ..., C NData communication is established with the main processing circuit 200 via a bus. The main processing circuit 200 is configured to perform data communication in each query cycle P. q (See) Figure 3 Initially, the multiple sub-processing circuits C1, C2, ..., C... are fed... N Sending a query command causes the multiple sub-processing circuits C1, C2, ..., C to... N After receiving the query command synchronously via this bus, the first signal and / or the second signal are asynchronously sent to the main processing circuit 200 respectively, so as to avoid the multiple sub-processing circuits C1, C2, ..., C N The data communication conflicts between them improved the state detection capability of the state detection system 1000.

[0039] See also Figure 2 Each of the sub-processing circuits C1, C2, ..., C N Configured to send a first signal and / or a second signal after a delay period following the receipt of the query command and before the delay period of the next sub-processing circuit, and satisfying the following:

[0040] T dN = (N-1) × A (1)

[0041] Among them, T dN Let A be the delay time of the Nth sub-processing circuit, where N is the identifier of the Nth sub-processing circuit and is ≥1, and A is the time constant. The unit of A can be s (seconds), ms (milliseconds), μs (microseconds), etc., depending on the actual needs.

[0042] For example, in Figure 3 In the timing diagram, the query command from the main processing circuit 200 takes a response time T. r Transmitted to each secondary processing circuit C1, C2, ..., C N Multiple secondary processing circuits C1, C2, ..., C N Data is transmitted in ascending order according to its own identifier codes 1, 2, ..., N. Because the secondary processing circuit C1 needs to perform a series of operations and the data volume is large, it needs a certain amount of time to generate a data packet upon receiving a query command, as described in detail below. Therefore, the secondary processing circuit C1... d1 =0 to T d2 =A transmits the first signal and / or the second signal to the main processing circuit 200 via this bus. Similarly, the secondary processing circuit C2 transmits the signal to the main processing circuit 200 via this bus. d2 =A to T d3 Between =2A, the first signal and / or the second signal are transmitted to the main processing circuit 200 via this bus, and the auxiliary processing circuit C3 transmits the first signal and / or the second signal to the main processing circuit 200 via T. d3 =2A to Td4 Between signals =3A, the first signal and / or the second signal are transmitted to the main processing circuit 200 via this bus, and so on. Two adjacent query cycles P q The time interval between them is ≥0ms.

[0043] See Figure 2 The status detection system 1000 also includes: multiple sub-drive circuits D1, D2, ..., D N A main drive circuit 300. Multiple secondary drive circuits D1, D2, ..., D... N Each of the sub-driving circuits is operably connected to and drives a corresponding sub-processing circuit C1, C2, ..., C N The main drive circuit 300 is operatively connected to and drives the main processing circuit 200, and communicatively connected to the plurality of sub-drive circuits D1, D2, ..., D... N This will be achieved by driving the multiple sub-drive circuits D1, D2, ..., D N The first signal and / or the second signal received from the sampling circuit 100 are sent to the main processing circuit 200.

[0044] See also Figure 2 Each of the sub-processing circuits C1, C2, ..., C N A secondary processing transmission port S is provided for transmitting the first signal and / or the second signal. C1 S C2 S CN and the secondary processing receive port R used to receive the query command C1 R C2 ..., R CN Each of the secondary drive circuits D1, D2, ..., D... N A corresponding sub-processing circuit C1, C2, ..., C is provided. N Secondary processing receiver port R C1 R C2 ..., R CN The secondary driver sending port S sends the query command. D1 S D2 S DN and used to receive from a corresponding secondary processing circuit C1, C2, ..., C N Secondary processing send port S C1 S C2 S CN The secondary drive receiving port R of the first signal and / or the second signal D1 R D2 ..., R DN The main processing circuit 200 is equipped with a main processing transmission port S for sending the query command. 200and the main processing receiving port R used to receive the first signal and / or the second signal 200 The main drive circuit 300 is configured to receive signals from the main processing port R. 200 The main driver transmit port S sends the first signal and / or the second signal. 300 and used to receive data from the main processing transmit port S 200 The main driver receiving port R of this query command 300 The main drive circuit 300 is equipped with a main drive bus port B for communication connection. 300 The multiple secondary drive circuits D1, D2, ..., D N Each is equipped with a port B for communication with the main drive bus. 300 A secondary drive bus port B for communication connection D1 B D2 B DN This enables a main processing circuit 200 to interact with multiple sub-processing circuits C1, C2, ..., C1. N A single-line communication connection between them.

[0045] Each of the sub-processing circuits C1, C2, ..., C N Configured to generate a checksum upon receiving the query command, and to combine the first and / or second signals from the corresponding set of sampling circuits 100, the checksum, and each sub-processing circuit C1, C2, ..., C N The identifiers 1, 2, ..., N are compressed into data packets and sent to the main processing circuit 200. As is known to those skilled in the art, the checksum is a fixed-length "data fingerprint" calculated based on the original data using a specific algorithm. Its core function is to verify whether errors (such as bit flips, loss, or tampering) have occurred during data transmission, storage, or processing, ensuring data integrity. The main processing circuit 200 is configured to check the checksum after receiving the data packet, and after determining that the checksum is correct, confirm the sub-processing circuit that sent the data packet based on the identifiers 1, 2, ..., N (i.e., confirm that the data packet was sent from sub-processing circuits C1, C2, ..., C...). N (Which one of them sent the data packet) and obtain the first signal or the second signal of each of the set of sampling circuits 100 corresponding to the sub-processing circuit that sent the data packet, and send the first signal or the second signal to the instrument panel to display on the instrument panel whether the corresponding component 2000 is in the first state or the second state.

[0046] The following describes in detail a detection method using a condition detection system 1000 to detect multiple components 2000 in a vehicle. This detection method includes a first operation S3100 performed on a main processing circuit 200, the first operation S3100 including:

[0047] First initialization step S3110: Initialize the main processing circuit 200 to enter a stable initial state;

[0048] Waiting step S3120: The main processing circuit 200 waits for the query cycle P. q If the query cycle P is not started, proceed to query step S3130; otherwise, proceed to receiving step S3140, so that regardless of the query cycle P... q Whether it starts, that is, regardless of the multiple sub-processing circuits C1, C2, ..., C N Whether to send data packets, the main processing circuit 200 is in the state of receiving data from the multiple sub-processing circuits C1, C2, ..., C N The reason for configuring this main processing circuit 200 in this way is that: two adjacent query cycles P q The time intervals between them are short, and it is unnecessary to put the main processing circuit 200 into a dormant state during these intervals, even if the multiple sub-processing circuits C1, C2, ..., C N In special cases where a data packet is sent without receiving a query command (e.g., the multiple sub-processing circuits C1, C2, ..., C...), N (If an operational error occurs) This main processing circuit 200 can also receive data packets, and if the main processing circuit 200 fails to receive data packets when it enters the receiving step S3140, according to the settings of the receiving step S3140 below, the main processing circuit 200 will also return to the waiting step S3120.

[0049] Query step S3130: The main processing circuit 200 sends a request to the multiple sub-processing circuits C1, C2, ..., C N Sending a query command causes the multiple sub-processing circuits C1, C2, ..., C to... N Upon receiving a query command simultaneously, it is activated and begins to send data packets sequentially to the main processing circuit 200.

[0050] Receiving step S3140: The main processing circuit 200 determines whether the data packet has been received. If not, it returns to the waiting step S3120; if yes, it proceeds to the next step.

[0051] Confirmation step S3160: Confirm the secondary processing circuits C1, C2, ..., C3 that sent the data packet based on the identifier codes 1, 2, ..., N. N It obtains the first or second signal of each sampling circuit 100 in the corresponding set of sampling circuits 100, and returns to the waiting step S3120 to start the next round of querying.

[0052] Operation S3100 also includes a checking step S3150 located between the receiving step S3140 and the confirmation step S3160: after receiving the data packet, the main processing circuit 200 checks the check value and determines whether the check value is correct. If it is, it proceeds to the confirmation step S3160; otherwise, it returns to the waiting step S3120.

[0053] The detection method also includes separately testing the multiple sub-processing circuits C1, C2, ..., C... N The second operation S3200 is performed, which includes:

[0054] Second initialization step S3210: Initialize the multiple sub-processing circuits C1, C2, ..., C... respectively. N Perform initialization to enter a stable initial state;

[0055] Reading step S3220: The multiple sub-processing circuits C1, C2, ..., C N Read and store the first signal and / or the second signal respectively;

[0056] Judgment step S3230: Determine the multiple sub-processing circuits C1, C2, ..., C N Whether the query command has been received separately; if so, then the sub-processing circuits C1, C2, ..., C that received the query command... N Proceed to the sending step S3240 (It should be noted that the sub-processing circuits C1, C2, ..., C... N (Usually, the query command is received simultaneously); otherwise, the sub-processing circuit that did not receive the query command returns to the reading step S3220; and

[0057] Sending step S3240: Sub-processing circuits C1, C2, ..., C1 that received the query command N The check value is generated, and the first and / or second signals from the corresponding set of sampling circuits 100, the check value, and the identifiers 1, 2, ..., N of each sub-processing circuit are compressed into a data packet after a delay time T. d1 T d2 ... T dN Then, during the delay time T of the next sub-processing circuit d2 T d3 ... T dN+1 Previously, it was sent to the main processing circuit 200 and returned to the read step S3220.

[0058] Figure 6A schematic block diagram of an example electronic device 60 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0059] like Figure 6 As shown, the electronic device 60 includes a computing unit 61, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 62 or a computer program loaded from a storage unit 68 into a random access memory (RAM) 63. The RAM 63 may also store various programs and data required for the operation of the electronic device 60. The computing unit 61, ROM 62, and RAM 63 are interconnected via a bus 64. An input / output (I / O) interface 65 is also connected to the bus 64.

[0060] Multiple components in electronic device 60 are connected to I / O interface 65, including: input unit 66, such as keyboard, mouse, etc.; output unit 67, such as various types of displays, speakers, etc.; storage unit 68, such as disk, optical disk, etc.; and communication unit 69, such as network card, modem, wireless transceiver, etc. Communication unit 69 allows electronic device 60 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0061] The computing unit 61 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 61 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 61 performs the various methods and processes described above, such as performing a detection method for detecting multiple components in a vehicle using the state detection system. For example, in some embodiments, the detection method for detecting multiple components in a vehicle using the state detection system can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 68. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 60 via ROM 62 and / or communication unit 69. When the computer program is loaded into RAM 63 and executed by the computing unit 61, one or more steps of the detection method for detecting multiple components in a vehicle using the state detection system described above can be performed. Alternatively, in other embodiments, the computing unit 61 may be configured by any other suitable means (e.g., by means of firmware) to perform a detection method that utilizes the state detection system to detect multiple components in the vehicle.

[0062] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this utility model can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this utility model can be achieved, and no limitation is imposed herein.

[0063] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transferring data and instructions to the storage system, the at least one input device, and the at least one output device.

[0064] The program code used to implement the methods of this utility model can be written in any combination of one or more programming languages. This program code can be provided to the processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0065] In the context of this invention, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0066] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0067] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0068] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0069] The embodiments of this utility model have been described in detail above with reference to the accompanying drawings. It should be noted that implementations not illustrated or described in the drawings or the main text of the specification are forms known to those skilled in the art and have not been described in detail. Furthermore, the definitions of the components described above are not limited to the various specific structures, shapes, or methods mentioned in the embodiments, and those skilled in the art can easily modify or substitute them.

[0070] It should also be noted that, in the specific embodiments of this utility model, unless otherwise stated otherwise, the numerical parameters in this specification and the appended claims are approximate values ​​and can be changed according to the desired characteristics obtained from the content of this utility model. Specifically, all numbers used in the specification and claims to indicate dimensions, range conditions, etc., of the composition should be understood to be modified by the term "about" in all cases. Generally, it means that there is a variation of ±10% in some embodiments, ±5% in some embodiments, ±1% in some embodiments, and ±0.5% in some embodiments.

[0071] Those skilled in the art will understand that the features described in the various embodiments and / or claims of this utility model can be combined or combined in various ways, even if such combinations or combinations are not explicitly described in this utility model. In particular, the features described in the various embodiments and / or claims of this utility model can be combined or combined in various ways without departing from the spirit and teachings of this utility model. All such combinations and / or combinations fall within the scope of this utility model.

[0072] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this utility model. It should be understood that the above description is only a specific embodiment of this utility model and is not intended to limit this utility model. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this utility model should be included within the protection scope of this utility model.

Claims

1. A condition detection system for detecting multiple components in a vehicle, characterized in that, include: At least one set of sampling circuits, each of the at least one set of sampling circuits being electrically connected to a corresponding component among the plurality of components and configured to output a first signal when the corresponding component is working normally and to output a second signal when the corresponding component is not working normally; Multiple sub-processing circuits are connected in parallel with each other, and each of the multiple sub-processing circuits is electrically connected to a corresponding set of sampling circuits; and A main processing circuit is connected to the plurality of sub-processing circuits via single-wire communication and is configured to send a query command to the plurality of sub-processing circuits at the beginning of each query cycle, such that after receiving the query command synchronously, the plurality of sub-processing circuits asynchronously send a first signal and / or a second signal to the main processing circuit, respectively.

2. The state detection system according to claim 1, characterized in that, Each sub-processing circuit is configured to send a first signal and / or a second signal after a delay time following the receipt of the query command and before the delay time of the next sub-processing circuit, satisfying the following: T dN =(N-1)×A, Among them, T dN Let A be the delay time of the Nth sub-processing circuit, where N is the identifier of the Nth sub-processing circuit and is ≥1, and A is the time constant.

3. The state detection system according to claim 2, characterized in that, Also includes: Multiple sub-driving circuits, each of which is operatively connected to and drives a corresponding sub-processing circuit; A main drive circuit is operatively connected to and drives the main processing circuit, and communicatively connected to the plurality of sub-drive circuits to transmit a first signal and / or a second signal received from the plurality of sub-drive circuits to the main processing circuit.

4. The state detection system according to claim 3, characterized in that, Each of the sub-processing circuits is provided with a sub-processing transmitting port for transmitting a first signal and / or a second signal and a sub-processing receiving port for receiving the query command; and Each sub-driving circuit is provided with a sub-driving sending port for sending the query command to the sub-processing receiving port of the corresponding sub-processing circuit and a sub-driving receiving port for receiving a first signal and / or a second signal from the sub-processing sending port of the corresponding sub-processing circuit.

5. The state detection system according to claim 4, characterized in that, The main processing circuit is provided with a main processing sending port for sending the query command and a main processing receiving port for receiving the first signal and / or the second signal. and The main drive circuit is provided with a main drive sending port for sending the first signal and / or the second signal to the main processing receiving port and a main drive receiving port for receiving the query command from the main processing sending port.

6. The state detection system according to any one of claims 3 to 5, characterized in that, The main drive circuit is provided with a main drive bus port for communication connection; and Each of the plurality of sub-drive circuits is provided with a sub-drive bus port for communication connection with the main drive bus port.

7. The state detection system according to claim 6, characterized in that, Each sub-processing circuit is configured to generate a check value upon receiving the query command, and to compress the first and / or second signals from the corresponding set of sampling circuits, the check value, and the identifier of each sub-processing circuit into a data packet for transmission to the main processing circuit.

8. The state detection system according to claim 7, characterized in that, The main processing circuit is configured to check the check value after receiving the data packet, and after determining that the check value is correct, confirm the sending of the data packet according to the identification code of the secondary processing circuit and obtain the first signal or the second signal of each sampling circuit in the corresponding set of sampling circuits.

9. The state detection system according to any one of claims 1 to 5 and 7 to 8, characterized in that, Each of the sub-processing circuits includes a plurality of pull-up resistors, each of which is electrically connected to a corresponding sampling circuit in the corresponding set of sampling circuits to pull the first signal high and the second signal low.

10. The state detection system according to claim 9, characterized in that, Each sampling circuit includes a switching component, the output of which is electrically connected to a corresponding pull-up resistor among the plurality of pull-up resistors.

11. The state detection system according to claim 10, characterized in that, The switching component includes at least one of the following: Diodes, bipolar junction transistors, field-effect transistors, and insulated-gate bipolar transistors.

12. The state detection system according to any one of claims 1 to 5, 7, 8, 10 and 11, characterized in that, A portion of the plurality of components is located in the central electrical box, and another portion of the plurality of components is located in other equipment of the vehicle.

13. The state detection system according to claim 12, characterized in that, The components include fuses and / or relays.

14. A vehicle, characterized in that, Includes the state detection system according to any one of claims 1 to 13.

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