A memory cell, a memory array, a chip, a detection device, an electronic device

Abstract

The application provides a storage unit, a storage array, a chip, a detection device and an electronic device. The storage unit comprises at least three fuse sub-units, each of which is provided with a readout end; a processing module is electrically connected with the readout ends of the at least three fuse sub-units respectively, configured to acquire readout signals from the at least three fuse sub-units, and process the readout signals according to a predetermined rule to generate an output result representing a corresponding logic bit of the storage unit. The storage array, the chip, the detection device and the electronic device adopting the storage unit can reliably read out a target logic bit when part of the fuse sub-units fail, thereby improving storage reliability and reducing data error probability.

Description

Technical Field

[0001] This application relates to the field of storage device technology, and in particular to storage cells, storage arrays, chips, detection devices, and electronic devices. Background Technology

[0002] In existing technologies, electrically programmed fuses are a commonly used type of non-volatile storage device, widely used in chip configuration parameter storage, calibration, chip serial numbers, and security keys—all scenarios requiring one-time writing. Efuses typically use polysilicon or metal wires as the storage structure. By applying a short, large pulse current across the fuse cell, the electromigration (EM) effect causes a partial melting of the conductive path, resulting in a transition in the fuse cell's resistance from a low-resistance state to a high-resistance state, thus achieving data "programming" and retention. During the read-out phase, the high-resistance state after programming is generally defined as logic "1," and the unprogrammed low-resistance state is defined as logic "0," thereby achieving non-volatile information storage.

[0003] However, in practical applications, fuse cells are susceptible to process deviations and reliability issues during manufacturing and use. For example, due to process defects or long-term stress, the fuse resistance value, which has been programmed to a high resistance state, may slowly decrease over time, drifting towards a low resistance state. Alternatively, during programming, unstable pulse current amplitude, pulse width, or temperature control may prevent the fuse resistance from reaching the expected threshold, resulting in failure modes such as "incomplete burning" or "insufficient resistance rise." To reduce the risk of data errors caused by the failure of a single fuse cell, existing technologies have proposed a dual-redundancy backup scheme. This scheme uses two fuse cells to store the same data, simultaneously reading two bits of data and performing logical operations. The two bits are then synthesized using a preset truth table. The output is only considered erroneous when both bits of data fail simultaneously. Even if only one bit of data is faulty, the correct result can still be recovered, thereby improving overall storage reliability to some extent.

[0004] However, due to current technological limitations, the long-term reliability of the fuse structure and its material system remains highly uncertain, and the consistency and accuracy of the programming process cannot fully meet the requirements of high-reliability applications. Against this backdrop, even with a dual-redundancy backup scheme, there is still a probability that two fuses in the same position may fail simultaneously during the manufacturing process or lifespan. For example, both fuses may experience a high resistance drop, or neither fuse may reach the target resistance level during the programming stage. This results in a relatively high overall error probability for the dual-redundancy scheme, failing to fully meet the requirements of applications with high safety and reliability demands, and posing a potential risk to the long-term stable operation of the chip. Utility Model Content

[0005] To overcome the problems of easy failure and high error probability of storage units in related technologies, this application provides storage units, storage arrays, chips, detection devices, and electronic devices.

[0006] According to a first aspect of the embodiments of this application, a storage unit is provided, comprising: At least three fuse sub-units, each of which is provided with a readout terminal; The processing module is electrically connected to the readout terminals of at least three fuse sub-units, and is configured to acquire readout signals from the at least three fuse sub-units and process the readout signals according to a predetermined rule to generate an output result representing the corresponding logic bit of the memory cell.

[0007] In some embodiments of this disclosure, the predetermined rules include at least: When at least one of the read signals from the at least three fuse subunits is a first logic value, the output result is set to the first logic value; When all of the read signals are the second logic value, the output result is set to the second logic value; The first logic value indicates that the corresponding fuse sub-unit is in a normal state, and the second logic value indicates that the corresponding fuse sub-unit is in an abnormal state.

[0008] In some embodiments of this disclosure, the storage unit includes at least two redundant unit groups; Each of the redundant unit groups includes at least two fuse sub-units, and the readout signal of the redundant unit group is determined by all the fuse sub-units in the redundant unit group. The processing module is configured to acquire read signals from the redundant unit group and process the read signals according to a predetermined rule to generate an output result representing the corresponding logical bit of the storage unit.

[0009] In some embodiments of this disclosure, the processing module includes: The initial judgment submodule, which is set in correspondence with the redundant unit group, is configured to read the readout signal of the fuse subunit in the corresponding redundant unit group and output the intermediate judgment result according to the group combination rules. The final judgment submodule, electrically connected to multiple initial judgment submodules, is configured to perform logical processing on the intermediate judgment results to generate the final output result of the storage unit.

[0010] In some embodiments of this disclosure, the processing module is further configured to acquire the readout signal of the target fuse subunit and output a diagnostic result characterizing the current state of the target fuse subunit, wherein the target fuse subunit is any one of the fuse subunits.

[0011] In some embodiments of this disclosure, the storage unit further includes: An interface module is electrically connected to the fuse subunit; wherein the interface module has a first port; the first port is configured to apply a preset voltage to the target fuse subunit based on an external enable signal to cause the fuse subunit to blow; and the first port is also configured to maintain a safe potential when the fuse subunit outputs a readout signal; the target fuse subunit is any one of the fuse subunits.

[0012] In some embodiments of this disclosure, the interface module further includes a second port; The second port is configured to allow access to the fuse sub-unit when it is in a first state, and to prohibit access to the fuse sub-unit when the second port is in a second state. The first state is different from the second state.

[0013] In some embodiments of this disclosure, the interface module further includes a third port; The third port is configured to select the access channel corresponding to the fuse subunit within a predetermined time slot; the access channel includes a first channel and a second channel; wherein, when the fuse subunit outputs a read signal, the third port selects the first channel; when the fuse subunit receives a preset voltage applied by the first port, the third port selects the second channel.

[0014] In some embodiments of this disclosure, the interface module further includes a fourth port; The fourth port is configured to receive an address signal, and when the second port is in the first state and the third port is triggered, the address signal is latched to select the fuse sub-unit corresponding to the address signal.

[0015] According to a second aspect of the embodiments of this application, a storage array is provided, including a plurality of the aforementioned storage cells.

[0016] According to a third aspect of the embodiments of this application, a chip is provided, including a plurality of the aforementioned memory arrays.

[0017] In some embodiments of this disclosure, at least three fuse sub-cells used to characterize the same logic bit are distributed in at least two different memory arrays.

[0018] In some embodiments of this disclosure, at least three fuse sub-units used to characterize the same logic bit are located at different memory addresses in the same memory array, and at least one of the word line and bit line electrically connected to any two fuse sub-units is not shared.

[0019] According to a fourth aspect of the embodiments of this application, a detection device is provided, including the chip as described in claim 1.

[0020] According to a fifth aspect of the embodiments of this application, an electronic device is provided, including the aforementioned chip or including the aforementioned detection device.

[0021] Beneficial effects: In a memory cell, at least three fuse sub-units collectively represent the same logic bit. During the programming stage, each fuse sub-unit is either blown or retained based on the target logic state. During the read-out stage, the processing module is electrically connected to the read-out terminals of each fuse sub-unit, applies read-out conditions to acquire at least three read-out signals, and performs logical processing on the read-out signals according to predetermined rules to obtain and output the final output result representing the corresponding logic bit of the memory cell. By redundantly storing the same logic bit using at least three fuse sub-units and making a comprehensive judgment by the processing module according to predetermined rules, the correct result can still be output even when some fuse sub-units fail due to process fluctuations or reliability issues. Read-out errors only occur in the extreme case of simultaneous failure of multiple sub-units, thereby significantly reducing the single logic bit failure rate and enhancing the fault tolerance capability for programming deviations.

[0022] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments consistent with this application and, together with the application, serve to explain the principles of this application.

[0024] Figure 1 This is a schematic diagram of a storage unit in related technologies.

[0025] Figure 2 This is a table for determining storage units in related technologies.

[0026] Figure 3 This is a circuit diagram of a storage unit in one embodiment of related technologies.

[0027] Figure 4 This is a circuit diagram of a storage unit in another embodiment of the related technology.

[0028] Figure 5 This is a schematic diagram of a storage unit in one embodiment of this application.

[0029] Figure 6 This is a circuit diagram of a storage unit in one embodiment of this application.

[0030] Figure 7 This is a determination table for a storage unit in one embodiment of this application.

[0031] Figure 8 This is a schematic diagram of a storage unit in another embodiment of this application.

[0032] Figure 9 This is a determination table for a storage unit in another embodiment of this application.

[0033] Figure 10 This is a schematic diagram illustrating the steps of the storage cell failure detection method in this application.

[0034] Explanation of reference numerals in the attached figures: 1. Storage unit; 11. Fuse sub-unit; 111. First fuse sub-unit; 112. Second fuse sub-unit; 113. Third fuse sub-unit; 12. Processing module; 121. Preliminary judgment sub-module; 122. Final judgment sub-module; 13. Redundancy unit group; 14. Logic combination module; 15. Input module; 2. Interface module; 21. First port; 22. Second port; 23. Third port; 24. Fourth port; M1. First transistor; M2. Second transistor; M3. Third transistor; M4. Fourth transistor; M5. Fifth transistor; M6. Sixth transistor; EF1. First fuse structure; EF2. Second fuse structure; EF3. Third fuse structure; WL. Word line; BL1. First bit line; BL2. Second bit line; BL3. Third bit line; RD. Readout strobe signal; RDC. Readout discharge control signal; SA. Sensing terminal; SA1. First sensing terminal; SA2. Second sensing terminal; SA3. Third sensing terminal. Detailed Implementation

[0035] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0036] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0037] Figure 1This is a schematic diagram of the structure of storage unit 1 in related technologies. See also... Figure 1 In related technologies, fuse redundancy design typically employs a dual-backup structure. Specifically, the circuit includes two functionally identical fuse sub-units 11 (e.g., a first fuse sub-unit 111 and a second fuse sub-unit 112) for storing the same set of configuration information. When this storage unit 1 is read, the corresponding read results from the first fuse sub-unit 111 and the second fuse sub-unit 112 are respectively input to the logic combination module 14. The logic combination module 14 performs logical operations on the two bits of data according to a preset truth table and outputs the results. The output is only considered erroneous when both corresponding bits of data fail simultaneously. Even when only one bit of data is erroneous, the correct result can still be read, thereby improving the reliability of the storage in the fuse sub-unit 11 to a certain extent.

[0038] Figure 2 This refers to a logical operation table used in related technologies. See also... Figure 2 In the existing scheme, the first fuse sub-unit 111 and the second fuse sub-unit 112 jointly represent the same logic bit when storing the same logic bit. In the table, A is the read result of the first fuse sub-unit 111, B is the read result of the second fuse sub-unit 112, and Out is the final output result after logical operation. "1" indicates that the corresponding fuse sub-unit 11 is programmed normally and is in a high-resistance state, and "0" indicates that the corresponding fuse sub-unit 11 is faulty (e.g., not fully burned or the high resistance drops to a low resistance). Figure 2 The truth table shows that when at least one of the first fuse sub-unit 111 and the second fuse sub-unit 112 is 1, the output of storage unit 1 is 1, which can still correctly represent the target logic bit; only when both the first fuse sub-unit 111 and the second fuse sub-unit 112 are 0, the output of storage unit 1 is judged as 0, which does not match the expected value, and this is an output error. In other words, the existing dual-bit redundancy scheme will only cause a read result error when both the first fuse sub-unit 111 and the second fuse sub-unit 112 fail simultaneously.

[0039] Figure 3 This is a circuit diagram of the first fuse subunit 111 and the second fuse subunit 112 in the related technology. See also... Figure 3 The circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first fuse structure EF1, a second fuse structure EF2, a word line WL, a first bit line BL1, a second bit line BL2, a readout strobe signal RD, a first sensing terminal SA1, and a second sensing terminal SA2.

[0040] In this configuration, one end of the first fuse structure EF1 is connected to the first bit line BL1, and the other end of EF1 is connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded, and its gate is connected to the word line WL. One end of the second fuse structure EF2 is connected to the second bit line BL2, and the other end of EF2 is connected to the drain of the second transistor M2. The source of the second transistor M2 is grounded, and its gate is also connected to the word line WL. The source of the third transistor M3 is connected to the first bit line BL1, and its drain is connected to the first sensing terminal SA1. Its gate receives the readout strobe signal RD. The source of the fourth transistor M4 is connected to the second bit line BL2, and its drain is connected to the second sensing terminal SA2. Its gate also receives the readout strobe signal RD. The readout strobe signal RD is generated by the external circuitry during the readout cycle and applied to the gates of the third transistor M3 and the fourth transistor M4. Thus, the first fuse structure EF1 and the first transistor M1 are connected in series to form the conduction branch of the first fuse subunit 111, and the second fuse structure EF2 and the second transistor M2 are connected in series to form the conduction branch of the second fuse subunit 112. The two branches are respectively connected to the corresponding sensing terminals SA via the third transistor M3 and the fourth transistor M4.

[0041] In this circuit, during the programming phase, the first transistor M1 and the second transistor M2 are turned on via the word line WL, forming conduction loops between the first fuse structure EF1 and ground, and between the second fuse structure EF2 and ground, respectively. At this time, a predetermined programming voltage or current pulse is applied to the first bit line BL1 and the second bit line BL2, causing the corresponding fuse structure to break down or its resistance to change significantly, thus writing the target data. Meanwhile, the readout strobe signal RD remains at an invalid level, turning off the third transistor M3 and the fourth transistor M4. During the readout phase, the peripheral circuit outputs a valid readout strobe signal RD, turning on the third transistor M3 and the fourth transistor M4. Simultaneously, the first transistor M1 and the second transistor M2 are turned on via the word line WL, forming readout current paths between the first sensing terminal SA1 and ground, and between the second sensing terminal SA2 and ground, respectively, for the first fuse subunit 111 and the second fuse subunit 112. Based on the difference in resistance between the first fuse structure EF1 and the second fuse structure EF2, the current flowing through their respective branches or the voltage at the branch nodes will differ. The sensing circuit will amplify and compare this difference at the first sensing terminal SA1 and the second sensing terminal SA2, thereby determining the logic state stored in the first fuse subunit 111 and the second fuse subunit 112 respectively.

[0042] Figure 4 This is a circuit diagram of the first fuse subunit 111 and the second fuse subunit 112 in another related technology. See also... Figure 4The circuit includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first fuse structure EF1, a second fuse structure EF2, a word line WL, a first bit line BL1, a second bit line BL2, a readout strobe signal RD, a readout discharge control signal RDC, and a sensing terminal SA.

[0043] In this configuration, one end of the first fuse structure EF1 is connected to the first bit line BL1, and the other end of EF1 is connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded, and its gate is connected to the word line WL. One end of the second fuse structure EF2 is connected to the second bit line BL2, and the other end of EF2 is connected to the drain of the second transistor M2. The source of the second transistor M2 is grounded, and its gate is also connected to the word line WL. One terminal of the third transistor M3 is connected to the first bit line BL1, and the other terminal is connected to the sensing terminal SA. Its gate receives the readout strobe signal RD. One terminal of the fourth transistor M4 is connected to the sensing terminal SA, and the other terminal is connected to the second bit line BL2. Its gate receives the readout discharge control signal RDC. The sensing terminal SA is the common node of the third transistor M3 and the fourth transistor M4. Thus, the first fuse structure EF1 and the first transistor M1 are connected in series to form the conduction branch of the first fuse subunit 111, and the second fuse structure EF2 and the second transistor M2 are connected in series to form the conduction branch of the second fuse subunit 112. The two conduction branches are electrically connected to the common sensing terminal SA through the third transistor M3 and the fourth transistor M4, respectively.

[0044] During the programming phase, the first transistor M1 and the second transistor M2 are turned on through the word line WL, and a predetermined programming voltage or current pulse is applied to the first bit line BL1 and the second bit line BL2 to cause the first fuse structure EF1 and the second fuse structure EF2 to break down or change their resistance significantly, so as to write the target data. At this time, the read strobe signal RD and the read discharge control signal RDC are both kept at an invalid level, the third transistor M3 and the fourth transistor M4 are turned off, and the sensing terminal SA does not participate in the programming circuit.

[0045] During the readout phase, the word line WL is set to an active level to select the target fuse sub-unit. Simultaneously, the readout selection signal RD and the readout discharge control signal RDC are controlled to flip in a predetermined sequence: when the readout selection signal RD is active, the third transistor M3 is turned on, forming a controlled conduction path between the first bit line BL1 and the sensing terminal SA; when the readout discharge control signal RDC is active, the fourth transistor M4 is turned on, forming a controlled conduction path between the sensing terminal SA and the second bit line BL2. Based on the different resistance states of the first fuse structure EF1 and the second fuse structure EF2, different currents or node voltages are generated at the sensing terminal SA via the conduction branch on the first bit line BL1 side and the conduction branch on the second bit line BL2 side. The sensing circuit amplifies and compares this difference at the sensing terminal SA to determine the logic states stored in the first fuse sub-unit 111 and the second fuse sub-unit 112, respectively. By allowing the two fuse sub-units 11 to share the same sensing terminal SA, and by using the readout gating signal RD and the readout discharge control signal RDC to perform timing control on the conduction of the third transistor M3 and the fourth transistor M4, the comparison readout of the two fuse sub-units 11 can be achieved while reducing the circuit area. This provides a basis for building a redundant decision mechanism for the upper-level circuit and is conducive to improving the data storage reliability based on the fuse sub-units 11.

[0046] However, due to limitations in processing and programming techniques, the reliability of the above-mentioned technologies remains limited, and there is still a certain probability of read errors for storage unit 1.

[0047] Based on this, see Figure 5 , Figure 8 The first aspect of this disclosure provides a storage unit 1. The storage unit 1 includes a processing module 12 and at least three fuse sub-units 11, each fuse sub-unit 11 having a read terminal; the processing module 12 is electrically connected to the read terminals of the at least three fuse sub-units 11 respectively, and is configured to acquire read signals from the at least three fuse sub-units 11, and process the read signals according to a predetermined rule to generate an output result representing the corresponding logic bit of the storage unit 1.

[0048] In this embodiment of the present disclosure, at least three fuse sub-units 11 within the same storage unit 1 collectively represent a logic bit. During the programming stage, each fuse sub-unit 11 is electrically programmed according to the target logic state to form a corresponding high-resistance or low-resistance state. During the read-out stage, the processing module 12 is electrically connected to the read-out terminals of the at least three fuse sub-units 11, and sequentially or simultaneously acquires the read-out signals of each fuse sub-unit 11. The multiple read-out signals are then logically processed according to predetermined rules to finally generate an output result representing the corresponding logic bit of the storage unit 1. By introducing at least three fuse sub-units 11 within the same storage unit 1 to store the same logic bit, and having the processing module 12 make a comprehensive judgment on multiple read signals according to predetermined rules, the correct logic result can still be output by relying on the remaining normal fuse sub-units 11 when some fuse sub-units 11 fail due to process fluctuations, insufficient programming, or high resistance drop. Read errors will only occur in the extreme case where multiple fuse sub-units 11 fail simultaneously, thereby significantly improving the overall reliability of data storage in storage unit 1, reducing the probability of read errors in storage unit 1, and helping to meet the requirements of non-volatile storage in high-reliability application scenarios.

[0049] As an example, see Figure 5 The storage unit 1 may include three fuse sub-units 11, specifically, a first fuse sub-unit 111, a second fuse sub-unit 112, and a third fuse sub-unit 113; the first fuse sub-unit 111, the second fuse sub-unit 112, and the third fuse sub-unit 113 collectively represent the same logic bit. During the programming stage, the control circuit performs the same electrical programming operation on the first fuse sub-unit 111, the second fuse sub-unit 112, and the third fuse sub-unit 113, so that they are all programmed to the state representing the target logic bit (e.g., programmed as a high resistance representing logic "1"). During the read-out stage, the processing module 12 obtains three read-out signals from the read-out terminals of the first fuse sub-unit 111, the second fuse sub-unit 112, and the third fuse sub-unit 113, respectively, and performs logical processing according to predetermined rules to obtain the final read-out result of the corresponding logic bit of the storage unit 1. In the case where storage cell 1 includes three fuse sub-cells 11, the same logic bit is represented by three redundant data streams. Even if one or two fuse sub-cells 11 output abnormal readings due to incomplete burning, high resistance drop, or other reliability issues, as long as at least one fuse sub-cell 11 remains in a normal state, the processing module 12 can output the correct result according to predetermined rules. Read errors only occur in the extreme case where all three fuse sub-cells 11 fail simultaneously. Compared to a single-fuse structure and a dual-redundancy scheme using only two fuse sub-cells 11, this significantly reduces the failure probability of the entire bit, further improving the reliability of storage in storage cell 1 and helping to meet the requirements of non-volatile storage in high-reliability application scenarios.

[0050] Furthermore, Figure 6 A circuit diagram of a memory cell 1 including three fuse sub-units 11 is shown. See also Figure 6 The storage unit 1 contains a first fuse subunit 111, a second fuse subunit 112, and a third fuse subunit 113 arranged in parallel. Taking the first fuse subunit 111 as an example, the first fuse subunit 111 includes a first fuse structure EF1, a first transistor M1, a first bit line BL1, a second transistor M2, and a word line WL. One end of the first fuse structure EF1 is connected to the first bit line BL1, and the other end of the first fuse structure EF1 is connected to the drain of the first transistor M1. The source of the first transistor M1 is grounded, and its gate is connected to the word line WL. The first bit line BL1 is also connected to the source of the second transistor M2. The drain of the second transistor M2 is connected to the first sensing terminal SA1 (the input terminal of the processing module 12), and the gate of the second transistor M2 receives the readout strobe signal RD. The second fuse subunit 112 has a structure that is basically the same as that of the first fuse subunit 111. The second fuse subunit 112 includes a second fuse structure EF2, a third transistor M3, a second bit line BL2, a fourth transistor M4, a word line WL, and a second bit line BL2. One end of the second fuse structure EF2 is connected to the second bit line BL2, and the other end of the second fuse structure EF2 is connected to the drain of the third transistor M3. The source of the third transistor M3 is grounded, and its gate is also connected to the word line WL. The second bit line BL2 is connected to the source of the fourth transistor M4, and the drain of the fourth transistor M4 is connected to the second sensing terminal SA2 (the input terminal of the processing module 12). The gate of the fourth transistor M4 receives the readout strobe signal RD. The third fuse subunit 113 includes a third fuse structure EF3, a fifth transistor M5, a third bit line BL3, a word line WL, and a sixth transistor M6. One end of the third fuse structure EF3 is connected to the third bit line BL3, and the other end of the third fuse structure EF3 is connected to the drain of the fifth transistor M5. The source of the fifth transistor M5 is grounded, and its gate is also connected to the word line WL. The third bit line BL3 is connected to the source of the sixth transistor M6, and the drain of the sixth transistor M6 is connected to the third sensing terminal SA3 (the input terminal of the processing module 12). The gate of the sixth transistor M6 receives the readout strobe signal RD. The first bit line BL1 is electrically connected to the first sensing terminal SA1, the second bit line BL2 is electrically connected to the second sensing terminal SA2, and the third bit line BL3 is electrically connected to the third sensing terminal SA3.

[0051] When a logic bit of memory cell 1 needs to be read, the control circuit activates the word line WL to select the first transistor M1, the third transistor M3, and the fifth transistor, causing the three fuse structures (first fuse structure EF1, second fuse structure EF2, and third fuse structure) to be connected to their respective bit line circuits. Simultaneously, the readout selection signal RD is activated, turning on the second transistor M2, the fourth transistor M4, and the sixth transistor M6, causing the first bit line BL1, the second bit line BL2, and the third bit line to be connected to the first sensing terminal SA1, the second sensing terminal SA2, and the third sensing terminal SA3 (input terminals of processing module 12), respectively. At this time, a readout voltage is applied to the bit lines or a readout current path is established. Depending on the resistance of the first fuse structure EF1, the second fuse structure EF2, and the third fuse structure EF3, the current or node voltage on each branch is different. The processing module 12 acquires three readout signals at the three sensing terminals SA and performs a comprehensive judgment according to predetermined rules to obtain the final output result of the logic bit corresponding to memory cell 1. In this application, the same logical bit is stored by three fuse sub-units 11, and the reading error will only occur in the extreme case that all three fail at the same time, thereby significantly improving the data storage reliability of the storage unit 1 and reducing the probability of reading error.

[0052] It should be noted that, Figure 6 The circuit structure shown is merely a specific example for illustrative purposes, used to visually demonstrate the typical connection relationship between the three fuse sub-units 11 and the word line WL, bit line, and sensing terminal SA in the same memory cell 1, and does not constitute a limitation of this application. In other embodiments, the number of fuse sub-units 11 can be three or more, and the connection method between each fuse sub-unit 11 and the word line WL, bit line, and sensing terminal SA can also be adjusted according to the layout, readout architecture, or interface requirements. For example, some fuse sub-units 11 may share the same word line WL or sensing terminal SA, some bit lines may be multiplexed through a switch network, and readout control signals may be controlled by grouping or multi-level gating. The transistors used to implement conduction control can be selected from different types or structures according to process conditions, and their source and drain wiring can also be appropriately changed. As long as at least three fuse sub-units 11 jointly represent the same logic bit, and the processing module 12 can obtain the read signal of each fuse sub-unit 11 and generate the output result of the storage unit 1 according to the predetermined rules, it should be considered to fall within the protection scope of this application. All possible equivalent modifications will not be described in detail here.

[0053] In some embodiments of this disclosure, the predetermined rule includes at least the following: when at least one of the read signals from at least three fuse subunits 11 is a first logic value, the output result is set to the first logic value; when all read signals are second logic values, the output result is set to the second logic value; wherein the first logic value indicates that the corresponding fuse subunit 11 is in a normal state, and the second logic value indicates that the corresponding fuse subunit 11 is in an abnormal state.

[0054] For example, taking a storage cell 1 containing three fuse sub-units 11 (namely, the first fuse sub-unit 111, the second fuse sub-unit 112, and the third fuse sub-unit 113), if all three are in a normal state, and the target logic bit should be the first logic value, then the read signals of the first fuse sub-unit 111, the second fuse sub-unit 112, and the third fuse sub-unit 113 are all the first logic value, and the output result is set to the first logic value. If any one of the fuse sub-units 11 is in an abnormal state, for example, the first fuse sub-unit 111 outputs the second logic value, while the second fuse sub-unit 112 and the third fuse sub-unit 113 still output the first logic value, then since there is still at least one first logic value in the read signal, the output result is still set to the first logic value, thus ensuring that the read of the storage cell 1 is correct. Similarly, even if two fuse sub-units 11 are in an abnormal state, as long as the remaining fuse sub-unit 11 is in a normal state, the output result is still determined to be the first logic value. Only in the extreme case where the first fuse subunit 111, the second fuse subunit 112, and the third fuse subunit 113 are all in an abnormal state, and all three read signals are at the second logic value, will the output result be set to the second logic value. In this case, the memory cell 1 can be determined to have failed. Therefore, by using the above predetermined rules, a correct result can still be output while at least one fuse subunit 11 remains normal. An error is only determined when all fuse subunits 11 are simultaneously abnormal, significantly reducing the probability of memory cell 1 failure and improving the reliability of data storage.

[0055] More specifically, taking a storage cell 1 comprising three fuse sub-cells 11 as an example (namely, the first fuse sub-cell 111, the second fuse sub-cell 112, and the third fuse sub-cell 113), the truth relationships corresponding to its predetermined rules are as follows: Figure 7 As shown. Figure 7The document lists all eight combinations of the three read signals of the first fuse subunit 111, the second fuse subunit 112, and the third fuse subunit 113 when the target logic bit should be the first logic value, along with the output results generated by the processing module 12 and whether they are judged as errors. It can be seen that when all three read signals are the first logic value, it indicates that all three fuse subunits 11 are in a normal state, and the output result is set to the first logic value. When only one fuse subunit 11 has a read signal of the second logic value and the other two have the first logic value, corresponding to the scenario of "single fuse subunit failure," the processing module 12 still sets the output result to the first logic value. When two fuse subunits 11 have read signals of the second logic value and only one fuse subunit 11 has a read signal of the first logic value, corresponding to the scenario of "multiple fuse subunit failures but one remaining normal," the output result is also judged to be the first logic value. Only in the extreme case where the read signals of the first fuse subunit 111, the second fuse subunit 112, and the third fuse subunit 113 are all the second logic value, i.e., all three fuse subunits 11 are simultaneously in an abnormal state, will the processing module 12 set the output result to the second logic value, and in... Figure 7 The code is marked as "output error" to indicate that the logic bit corresponding to memory cell 1 is invalid.

[0056] In the above Figure 7 In the description, the first logic value is used to characterize that the corresponding fuse subunit 11 is in a normal working state, such as the fuse has been programmed into the target resistance range as expected, and the read result meets the judgment threshold requirements; the second logic value is used to characterize that the corresponding fuse subunit 11 is in an abnormal state, such as insufficient fuse programming, abnormal burn-through, or high resistance falling back over time, causing the read result to be lower than the judgment threshold, which should be considered as failure. It should be noted that in this embodiment, the first logic value and the second logic value can correspond to logic "1" and logic "0" respectively, or they can correspond to high level and low level respectively, or they can correspond to "normal" flag and "failure" flag respectively, as long as they can be distinguished during the read decision. In other embodiments, the specific values ​​and level definitions of the first logic value and the second logic value can be adjusted according to the actual circuit design and system protocol. This application does not limit this and will not elaborate further.

[0057] Furthermore, in some embodiments, the processing module 12 can also be used to locate the faulty fuse sub-unit 11. Specifically, while processing the read signals of at least three fuse sub-units 11 according to predetermined rules and generating the final output result of the storage unit 1, the processing module 12 can also retain the read results corresponding to each fuse sub-unit 11, and generate status flag information for each fuse sub-unit 11 based on its respective read results; for example, when the read signal of a fuse sub-unit 11 is a first logic value, its status flag is set to normal state, and when its read signal is a second logic value, its status flag is set to abnormal state. In this way, while outputting the overall judgment result of the storage unit 1, the processing module 12 can also output at least one diagnostic result characterizing the current state of the fuse sub-unit 11, indicating which one or more fuse sub-units 11 are abnormal, thereby facilitating subsequent recording, statistics, or further fault analysis of the failed fuse sub-units 11, and improving the convenience of fault diagnosis and maintenance.

[0058] In some embodiments of this disclosure, see Figure 8 The storage unit 1 includes at least two redundant unit groups 13; each redundant unit group 13 includes at least two fuse sub-units 11, and the read signal of the same redundant unit group 13 is jointly determined by all fuse sub-units 11 within the redundant unit group 13; the processing module 12 is configured to acquire the read signals from the redundant unit groups 13 and process the read signals according to predetermined rules to generate an output result representing the corresponding logic bit of the storage unit 1. During operation, the processing module 12 acquires the read signals from all fuse sub-units 11 within each redundant unit group 13, processes these read signals uniformly according to predetermined rules, such as comprehensively considering the read results of each fuse sub-unit 11 within the same redundant unit group 13 and the relationship between read results between different redundant unit groups 13, and finally generates an output result representing the corresponding logic bit of the storage unit 1, realizing redundant readout and comprehensive determination of the logic bit.

[0059] In this embodiment, by setting at least two redundant unit groups 13 on the same logical bit, and arranging multiple fuse sub-units 11 within each redundant unit group 13, on the one hand, even if individual fuse sub-units 11 in a certain redundant unit group 13 fail, the processing module 12 can still use the read results of the remaining normal fuse sub-units 11 in the group to participate in the judgment according to predetermined rules; on the other hand, even if a certain redundant unit group 13 as a whole is affected by process fluctuations or local failures, the processing module 12 can still make a correct judgment by comprehensively considering the read results of other redundant unit groups 13. In this way, without changing the basic structure of a single fuse sub-unit 11, the probability of the entire same logical bit failing is effectively reduced, and the data storage reliability and resistance to process deviations of the storage unit 1 are significantly improved.

[0060] It should be noted that the above configuration of "storage unit 1 including at least two redundant unit groups 13, and each redundant unit group 13 including at least two fuse sub-units 11" is only an example of a preferred implementation of this disclosure, used to illustrate the basic idea of ​​achieving redundancy through multiple groups and multiple fuse sub-units 11. In other embodiments, the number of redundant unit groups 13 can be two or more, such as three or more; the number of fuse sub-units 11 in each redundant unit group 13 can also be adjusted according to design constraints such as reliability targets, layout area, and power consumption, as long as it includes at least two fuse sub-units 11. This disclosure is not limited to a specific number of groups or the specific number of fuse sub-units 11 within a group.

[0061] In this disclosure, "fuse sub-units 11 within the same redundant unit group 13 represent the same logical bit" means that multiple fuse sub-units 11 within the same redundant unit group 13 are configured during design and use to jointly store the content of the same logical information bit. Specifically, during the programming stage, for a certain target logical value (e.g., logical "1" or logical "0"), a consistent electrical programming operation is performed on all fuse sub-units 11 within the redundant unit group 13, so that their physical states jointly correspond to the logical bit; during the read-out stage, the processing module 12 treats the read signals of each fuse sub-unit 11 within the redundant unit group 13 as multiple redundant readings of the same logical bit, and processes them uniformly according to predetermined rules, rather than using different fuse sub-units 11 within the group as data bits with different addresses or different meanings independently. In other words, multiple fuse sub-units 11 within the group are logically related as "multiple physical units redundantly representing one bit of data".

[0062] More specifically, taking any redundant unit group 13 in storage unit 1 as an example, this redundant unit group 13 includes two fuse sub-units 11, which generate two read signals respectively during the read phase. Corresponding to the predetermined rule adopted in this embodiment, its truth relationship is as follows: Figure 9 As shown. Figure 9The document lists all four combinations of the two read signals from the two fuse subunits 11 within the redundant unit group 13, assuming the target logic bit should be the first logic value. It also lists the output of the processing module 12 and whether the result is considered an error. It can be seen that when both read signals are the first logic value, it indicates that both fuse subunits 11 within the redundant unit group 13 are in normal working condition, and the output is set to the first logic value. When only one of the two read signals is the second logic value and the other is still the first logic value, corresponding to the scenario of "one fuse subunit 11 failing while the other fuse subunit 11 remains normal," the processing module 12 still sets the output to the first logic value and does not consider it an error. Only in the extreme case where both read signals are simultaneously the second logic value, i.e., both fuse subunits 11 within the redundant unit group 13 are simultaneously in an abnormal state, does the processing module 12 set the output to the second logic value and... Figure 9 The error is marked as "output error," indicating that the logic bit corresponding to the redundant unit group 13 has failed. Therefore, by following the predetermined rules, as long as at least one fuse sub-unit 11 within the redundant unit group 13 is in a normal state, the logic bit can be read correctly. An error judgment will only occur when both fuse sub-units 11 fail simultaneously, thus significantly reducing the probability of logic bit failure and improving the data storage reliability of storage unit 1.

[0063] In the above Figure 9 In the related descriptions, the first logic value is used to characterize that the corresponding fuse subunit 11 is in a normal working state, such as the fuse resistance meeting a predetermined threshold requirement or the readout result falling within the "qualified" range; the second logic value is used to characterize that the corresponding fuse subunit 11 is in an abnormal or failed state, such as insufficient fuse programming, abnormal burn-through, or high resistance decreasing over time, resulting in the readout result not meeting the judgment threshold. It should be noted that in this embodiment, the first logic value and the second logic value can correspond to logic "1" and logic "0" respectively, or they can correspond to high level and low level respectively, or they can correspond to "normal" flag and "failure" flag respectively, as long as the two can be distinguished in the decision process. In other embodiments, the specific level, encoding form, and correspondence of the first logic value and the second logic value can be adjusted according to the actual circuit design and system protocol. This application does not limit this and will not elaborate further.

[0064] In some embodiments of this disclosure, see Figure 8The processing module 12 includes a preliminary judgment submodule 121 and a final judgment submodule 122. The preliminary judgment submodule 121 is configured to correspond to the redundant unit group 13 and read the read signal of the fuse subunit 11 in the corresponding redundant unit group 13 and output the intermediate judgment result according to the group combination rules. The final judgment submodule 122 is electrically connected to multiple preliminary judgment submodules 121 and is configured to perform logical processing on the intermediate judgment result to generate the final output result of the storage unit 1. For example, when at least one of the read signals in the redundant unit group 13 is a first logical value, the intermediate judgment result corresponding to the redundant unit group 13 is set to the first logical value. Only when all read signals in the redundant unit group 13 are second logical values ​​is the intermediate judgment result set to the second logical value. The final judgment submodule 122 is electrically connected to multiple initial judgment submodules 121 and is configured to obtain intermediate judgment results of multiple redundant unit groups 13 and perform logical processing on these intermediate judgment results, such as generating the final output result representing the logical bit corresponding to the storage unit 1 according to predetermined inter-group logical rules (such as "if any group is normal, the whole is normal").

[0065] By dividing the storage content of the same logical bit into multiple redundant unit groups 13, and setting multiple fuse sub-units 11 within each redundant unit group 13, the processing module 12 comprehensively judges the read results of different redundant unit groups 13. This allows for fault tolerance to the failure of a single fuse sub-unit 11 within a group, and fault tolerance to the overall failure of a certain redundant unit group 13 between groups: a decision error will only occur when multiple redundant unit groups 13 fail simultaneously, thus significantly reducing the overall failure probability of the same logical bit. Simultaneously, different redundant unit groups 13 can be spatially distributed on the layout, reducing the simultaneous impact of local process defects, thermal stress concentration, or local electromigration on all redundant units. This improves the resilience of the storage unit 1 to process fluctuations and local failures, and provides a basis for the processing module 12 to adopt flexible decision-making strategies such as majority voting, which is beneficial to improving the overall reliability of data storage.

[0066] In this embodiment, the processing is divided into two levels: intra-group initial judgment and inter-group final judgment. On the one hand, the initial judgment submodule 121 uses the redundancy relationship of multiple fuse subunits 11 within each redundant unit group 13 to make group-wide error judgments, effectively shielding the failure of individual fuse subunits 11 within the group. On the other hand, the final judgment submodule 122 performs a comprehensive judgment on the intermediate judgment results of each redundant unit group 13 again between groups. When a redundant unit group 13 as a whole is affected by process defects or local failures, the correctness of the final output result can still be maintained by relying on the intermediate judgment results of other redundant unit groups 13. Compared with the scheme that only performs redundancy at a single level, this two-level judgment structure further reduces the probability of the same logic bit failing as a whole, significantly improves the data storage reliability of the storage unit 1, and is conducive to meeting the usage requirements of high-reliability application scenarios.

[0067] It should be noted that the intra-group combination rules adopted by the initial judgment submodule 121 and the inter-group logic rules adopted by the final judgment submodule 122 can be flexibly configured according to different application scenarios, and are not limited to the above-mentioned exemplary rules such as "the existence of the first logic value is judged as normal" or "all are judged as abnormal". As long as the intermediate judgment result generated by the initial judgment submodule 121 can reflect the state of each redundant unit group 13, and the final output result generated by the final judgment submodule 122 based on the intermediate judgment result can correctly characterize the state of the corresponding logic bit of the storage unit 1, it can be regarded as falling within the protection scope of this disclosure.

[0068] In some embodiments of this disclosure, the processing module 12 is further configured to acquire the readout signal of the target fuse subunit 11 and output a diagnostic result characterizing the current state of the target fuse subunit; the target fuse subunit is any one of the fuse subunits 11.

[0069] It is understandable that the processing module 12 can not only combine and process the read signals from multiple fuse sub-units 11 to generate the final output result of the storage unit 1, but also analyze the read signal of any fuse sub-unit 11 as needed to give an independent state determination of the fuse sub-unit 11 for fault diagnosis and health monitoring of the fuse sub-unit 11.

[0070] In some embodiments of this disclosure, see Figure 5 , Figure 8 The storage unit 1 also includes an interface module 2; the interface module 2 is electrically connected to the fuse sub-unit 11; wherein the interface module 2 has a first port 21; the first port 21 is configured to apply a preset voltage to the target fuse sub-unit based on an external enable signal to cause the fuse sub-unit 11 to blow; and the first port 21 is also configured to maintain a safe potential when the fuse sub-unit 11 outputs a read signal; the target fuse sub-unit is any one of the fuse sub-units 11.

[0071] Specifically, during the programming phase, the external circuit provides an enable signal to the first port 21. The interface module 2 responds to this enable signal by applying a preset high voltage or pulse voltage to the corresponding fuse sub-unit 11 via the first port 21. This applies sufficient electrical stress to the fuse sub-unit 11, causing it to melt or significantly increase its resistance, thus completing the programming of the fuse sub-unit 11. During the readout phase, the first port 21 no longer outputs a programming voltage. Instead, it is controlled at a preset safe potential (e.g., ground, power supply potential, or a high-resistance state, which will not cause additional stress to the fuse sub-unit 11). This avoids interfering with the readout process of the fuse sub-unit 11 or introducing additional voltage stress, ensuring that the fuse sub-unit 11 outputs a readout signal under normal and stable bias conditions, thereby improving the safety and reliability of the programming and readout processes.

[0072] In some embodiments of this disclosure, see Figure 5 , Figure 8 The interface module 2 also includes a second port 22; the second port 22 is configured to allow access to the fuse sub-unit 11 when it is in a first state; and to prohibit access to the fuse sub-unit 11 when the second port 22 is in a second state; wherein the first state and the second state are different.

[0073] Specifically, in the first state, the second port 22 is in the "enabled" state, and the access path between the interface module 2 and the fuse sub-unit 11 is opened. External signals can be transmitted to the fuse sub-unit 11 through the interface module 2, thereby allowing programming or reading operations to be performed on the fuse sub-unit 11. When the second port 22 is in the second state, the second port 22 is in the "disabled" state, and the access path between it and the fuse sub-unit 11 is closed. External signals can no longer directly act on the fuse sub-unit 11. If necessary, the relevant nodes can also be clamped to a preset safety potential to prevent misprogramming, illegal access or abnormal interference.

[0074] In this circuit, the first state can be an enable level (e.g., a high level or a low level, determined by the specific implementation), indicating that access to the fuse sub-unit 11 is allowed; the second state can be a disable level (the opposite level to the first state or a high-impedance state), indicating that access to the fuse sub-unit 11 is prohibited. In other words, the first state corresponds to "access enabled" and the second state corresponds to "access disabled". The specific electrical values ​​of the first and second states can be flexibly set according to the actual circuit design, and this disclosure does not limit them.

[0075] In some embodiments of this disclosure, see Figure 5 , Figure 8The interface module 2 also includes a third port 23; the third port 23 is configured to select the access channel corresponding to the fuse subunit 11 within a predetermined time slot; the access channel includes a first channel and a second channel; wherein, when the fuse subunit 11 outputs a read signal, the third port 23 selects the first channel; when the fuse subunit 11 receives a preset voltage applied by the first port 21, the third port 23 selects the second channel.

[0076] The function of the third port 23 can be understood as a time-controlled channel switching of the access path of the fuse sub-unit 11 between the read-out stage and the programming stage. Specifically, within the system's predetermined read-out time slot, the third port 23 is controlled to select the first channel, allowing the fuse sub-unit 11 to be electrically connected to the processing module 12 through the first channel. At this time, the first channel is on and the second channel is off, and the fuse sub-unit 11 outputs a read-out signal for the processing module 12 to determine. During the system's predetermined programming time slot, the third port 23 is controlled to select the second channel, allowing the fuse sub-unit 11 to be electrically connected to the first port 21 through the second channel, receiving a preset voltage from the first port 21 to complete the programming operation. At this time, the second channel is on and the first channel is off, limiting the high voltage within the programming path and avoiding impact on the read-out path and subsequent circuits. By using the third port 23 to mutually exclude the first and second channels in different predetermined time slots, time-division multiplexing and electrical isolation of the read-out path and programming path of the fuse sub-unit 11 are achieved, which is beneficial to improving programming security and read-out stability.

[0077] In some embodiments of this disclosure, see Figure 5 , Figure 8 The interface module 2 also includes a fourth port 24; the fourth port 24 is configured to receive an address signal and latch the address signal when the second port 22 is in the first state and the third port 23 is triggered, so as to select the fuse sub-unit 11 corresponding to the address signal.

[0078] Specifically, the external circuit provides an address signal on the bus to identify the location of the target fuse sub-unit. When the second port 22 is in the first state and the third port 23 is triggered in the corresponding programming or read time slot, the fourth port 24 latches the address signal at this moment and sends the latch result to the decoding circuit inside the interface module 2. The decoding circuit selects the fuse sub-unit 11 corresponding to the address, so that the programming voltage provided by the first port 21 or the read bias provided by the read path only applies to the selected target fuse sub-unit. At the same time, after the address is latched, even if the external address bus changes, the selected fuse sub-unit 11 remains unchanged, thereby avoiding misselection of units caused by timing jitter or bus interference.

[0079] The address signal can be understood as encoded information used to uniquely identify the logical location of the fuse sub-unit 11. For example, it may include row address, column address, word line WL number, bit line number or index number in macro cell, etc. Its specific bit width and encoding method can be flexibly set according to the size of the storage array and the actual implementation. This disclosure does not limit it.

[0080] Secondly, this disclosure also provides a storage array comprising a plurality of the aforementioned storage cells 1.

[0081] Thirdly, this disclosure also provides a chip. The chip includes the aforementioned memory array. This chip can be used as an on-chip configuration storage, tuning parameter storage, or failure flag storage module in various high-reliability electronic systems, such as general-purpose processor chips, application-specific integrated circuits, memory chips, automotive-grade control chips, and safety-related controllers, to store key information such as product characteristic parameters, redundancy repair information, keys, or security configuration bits. Based on the aforementioned multi-fuse subunit 11, multi-redundancy unit group 13, and decision mechanism, this chip significantly reduces the overall failure probability of memory bits without changing the existing process system, improves fault tolerance due to process fluctuations, and can cooperate with the processing module 12 to output diagnostic results, enabling the location and monitoring of abnormal fuse subunits 11, thereby improving the overall chip configuration reliability and security. It is suitable for application scenarios with high requirements for non-volatile memory reliability.

[0082] In some embodiments of this disclosure, at least three fuse sub-units 11 representing the same logic bit are located at different memory addresses in the same memory array, and at least one of the word line WL and bit line electrically connected to any two fuse sub-units 11 is not shared. This configuration allows these fuse sub-units 11 to be independent on the layout and interconnects, preventing short circuits, open circuits, electromigration, or noise interference from the same word line WL or bit line from simultaneously affecting all fuse sub-units 11. This reduces the probability of common-cause failures of data at the same bit, making the failure of each fuse sub-unit 11 more independent, and further improving the overall reliability of redundant memory.

[0083] In some embodiments of this disclosure, at least three fuse sub-units 11 used to characterize the same logic bit are distributed in at least two different memory arrays. This arrangement can reduce the probability of common-cause failure of co-occurring data, and compared to redundancy within a single memory array, can significantly improve the overall reliability and security of the logic bit at the chip level.

[0084] Fourthly, this disclosure also provides a detection device. This detection device includes the chip described above.

[0085] Its working principle can be understood as follows: an external detection device sends read or self-test commands to the memory array inside the chip through a control interface. The processing module 12 inside the chip obtains the read signals of multiple fuse sub-units 11, generates output results representing the logic bit status of memory unit 1 according to predetermined rules, and outputs corresponding diagnostic information (such as indicating which one or more fuse sub-units 11 are in an abnormal state). Based on these status results and diagnostic information returned by the chip, the detection device determines whether the corresponding memory unit 1, memory array, or even the entire chip has failed or degraded, thereby realizing online detection and health monitoring of the fuse storage status.

[0086] Fifthly, this disclosure also provides an electronic device that may include the aforementioned chip and / or the aforementioned detection device. This electronic device may be a smartphone, tablet computer, laptop computer, server, network communication equipment, wearable device, vehicle control unit, industrial control equipment, home appliance control board, etc. In these devices, the aforementioned chip can be used to store critical information such as factory configuration parameters, redundancy repair information, security keys, function enable bits, or calibration data. Through the redundant fuse storage structure and failure detection mechanism inside the chip, the electronic device can continuously maintain reliable storage and interpretation of the aforementioned critical information during long-term service. When necessary, it can cooperate with the detection device to diagnose and mark abnormal fuse subunits 11, thereby improving the reliability and security of the entire device in scenarios such as safe startup, function configuration, fault self-testing, and remote upgrades. This is suitable for various electronic systems with high requirements for non-volatile storage stability.

[0087] Sixth aspect, see Figure 10 This disclosure also provides a method for detecting the failure of the storage unit 1. The detection method includes: S1: Obtain the readout signal of fuse subunit 11.

[0088] S2: The processing module 12 receives the read signal, processes the read signal, and outputs the output result of the corresponding storage unit 1.

[0089] Specifically, after receiving read signals from at least three fuse sub-units 11 of the target storage cell 1, the processing module 12 first compares each read signal with a preset reference level or threshold. Read signals that meet the first preset condition are normalized to a first logic value, and read signals that do not meet the first preset condition but meet the second preset condition are normalized to a second logic value, thus obtaining a standardized multi-channel logic reading. Subsequently, the processing module 12 performs combination operations on the multi-channel logic readings according to the aforementioned predetermined rules: for example, in some embodiments, when at least one of the read signals is a first logic value, the output result is set to the first logic value; only when all read signals are second logic values ​​is the output result set to the second logic value. In embodiments employing a redundant unit group 13 structure, the processing module 12 can also use the initial judgment sub-module 121 to perform intra-group combination operations on the read signals within each redundant unit group 13 to obtain intermediate decision results, and then the final judgment sub-module 122 performs inter-group logic processing on multiple intermediate decision results to finally generate an output result representing the corresponding logic bit of the target storage cell 1. The output can be latched into an internal register or returned to an external control circuit via a bus.

[0090] S3: Determine the state of storage unit 1 by judging the output result.

[0091] Specifically, the judgment unit in the upper-level control circuit or processing module 12 reads the output result obtained in step S2 and maps the output result to a pre-defined meaning: for example, the first logic value is mapped to the state of "storage unit 1 is normal", and the second logic value is mapped to the state of "storage unit 1 is faulty". When the output result is the first logic value, it is determined that the target storage unit 1 is in a normal working state under the current detection conditions and can continue to be used for storage and configuration; when the output result is the second logic value, it is determined that the target storage unit 1 has failed or has serious degradation, and its corresponding address and related flag information can be recorded in the fault table, or reported to the system through the detection device, so that subsequent redundant replacement, masking or other fault-tolerant strategies can be executed. In some embodiments, the original read signals of each fuse sub-unit 11 in step S1 can also be combined to generate diagnostic results for each fuse sub-unit 11 participating in the storage of the same logic bit, so as to finely locate which one or several fuse sub-units 11 are in an abnormal state, thereby further improving the accuracy of failure detection and fault analysis.

[0092] In summary, the storage unit 1 provided in this application introduces at least three fuse sub-units 11 on the same logical bit, which can be further organized into multiple redundant unit groups 13. Combined with the predetermined decision rules of the processing module 12, it achieves fault tolerance for the failure of a single fuse sub-unit 11 or even a single redundant unit group 13, effectively reducing the failure probability of the entire bit and significantly improving the reliability of fuse data storage. The storage array and chip constructed based on this storage unit 1 can mitigate the risk of common-cause failures by rationally distributing the fuse sub-units 11 within and between arrays, making it suitable for application scenarios with high reliability requirements for on-chip configuration, parameter adjustment, and security information. Furthermore, by utilizing the detection device composed of the aforementioned chip and the electronic device integrating the chip or detection device, online detection and anomaly location of the fuse storage status can be achieved, improving system-level security and maintainability. At the same time, the storage cell 1 failure detection method proposed in this application, combined with the multi-fuse redundancy structure and the decision mechanism of the processing module 12, provides a unified software and hardware execution path for quickly judging the health status of the storage cell 1, giving this application comprehensive advantages in reliable storage, fault diagnosis, and engineering feasibility.

[0093] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the application and practice of the invention described herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not claimed herein. The application and embodiments are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0094] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0095] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A storage unit, characterized in that: include: At least three fuse sub-units, each of which is provided with a readout terminal; The processing module is electrically connected to the readout terminals of at least three fuse sub-units, and is configured to acquire readout signals from the at least three fuse sub-units and process the readout signals according to a predetermined rule to generate an output result representing the corresponding logic bit of the memory cell.

2. The storage unit according to claim 1, characterized in that: The predetermined rules include at least the following: When at least one of the read signals from the at least three fuse subunits is a first logic value, the output result is set to the first logic value; When all of the read signals are the second logic value, the output result is set to the second logic value; The first logic value indicates that the corresponding fuse sub-unit is in a normal state, and the second logic value indicates that the corresponding fuse sub-unit is in an abnormal state.

3. The storage unit according to claim 1, characterized in that: The storage unit includes at least two redundant unit groups; Each of the redundant unit groups includes at least two fuse sub-units, and the readout signal of the redundant unit group is determined by all the fuse sub-units in the redundant unit group. The processing module is configured to acquire read signals from the redundant unit group and process the read signals according to a predetermined rule to generate an output result representing the corresponding logical bit of the storage unit.

4. The storage unit according to claim 3, characterized in that: The processing module includes: The initial judgment submodule, which is set in correspondence with the redundant unit group, is configured to read the readout signal of the fuse subunit in the corresponding redundant unit group and output the intermediate judgment result according to the group combination rules. The final judgment submodule, electrically connected to multiple initial judgment submodules, is configured to perform logical processing on the intermediate judgment results to generate the final output result of the storage unit.

5. The storage unit according to any one of claims 1 to 4, characterized in that: The processing module is further configured to acquire the readout signal of the target fuse subunit and output a diagnostic result characterizing the current state of the target fuse subunit, wherein the target fuse subunit is any one of the fuse subunits.

6. The storage unit according to claim 1, characterized in that: The storage unit further includes: An interface module is electrically connected to the fuse subunit; wherein the interface module has a first port; the first port is configured to apply a preset voltage to the target fuse subunit based on an external enable signal to cause the fuse subunit to blow; and the first port is also configured to maintain a safe potential when the fuse subunit outputs a readout signal; the target fuse subunit is any one of the fuse subunits.

7. The storage unit according to claim 6, characterized in that: The interface module also includes a second port; The second port is configured to allow access to the fuse sub-unit when it is in a first state, and to prohibit access to the fuse sub-unit when the second port is in a second state. The first state is different from the second state.

8. The storage unit according to claim 6, characterized in that: The interface module also includes a third port; The third port is configured to select the access channel corresponding to the fuse subunit within a predetermined time slot; the access channel includes a first channel and a second channel; wherein, when the fuse subunit outputs a read signal, the third port selects the first channel; when the fuse subunit receives a preset voltage applied by the first port, the third port selects the second channel.

9. The storage unit according to claim 7, characterized in that: The interface module also includes a third port; The third port is configured to select an access channel corresponding to the fuse subunit within a predetermined time slot; the access channel includes a first channel and a second channel; wherein, when the fuse subunit outputs a read signal, the third port selects the first channel; when the fuse subunit receives a preset voltage applied by the first port, the third port selects the second channel. The interface module also includes a fourth port; The fourth port is configured to receive an address signal, and when the second port is in the first state and the third port is triggered, the address signal is latched to select the fuse sub-unit corresponding to the address signal.

10. A storage array, characterized in that: It includes a plurality of storage units as described in any one of claims 1 to 9.

11. A chip, characterized in that: It includes multiple storage arrays as described in claim 10.

12. The chip according to claim 11, characterized in that: At least three fuse sub-cells used to characterize the same logic bit are distributed in at least two different memory arrays.

13. The chip according to claim 11, characterized in that: At least three fuse sub-units used to represent the same logic bit are located at different memory addresses in the same memory array, and at least one of the word line and bit line electrically connected to any two fuse sub-units is not shared.

14. A detection device, characterized in that: Includes the chip as described in any one of claims 11 to 13.

15. An electronic device, characterized in that: Includes the chip as described in any one of claims 11 to 13 or includes the detection device as described in claim 14.

Images