A battery pack

Abstract

The utility model discloses a battery pack belongs to battery technical field, the battery pack at least includes: the electric core group, the electric core group includes at least 20 series connection's electric core, single analog front end chip, analog front end chip respectively with a plurality of electric core in electric core group electric connection, for monitoring a plurality of the state of electric core, the power input of analog front end chip electric connection in the positive pole of electric core group, main control chip, main control chip electric connection in analog front end chip, for according to analog front end chip's monitoring result control the battery pack's charge, discharge and power supply circuit, power supply circuit connects between the power input of analog front end chip and the power input of main control chip, for to main control chip power supply. Through the battery pack provided by the utility model, the battery pack life can be increased and the cost is reduced.

Description

Technical Field

[0001] This utility model belongs to the field of battery technology, and specifically relates to a battery pack. Background Technology

[0002] The battery pack is a core component of electric devices such as outdoor power tools, electric vehicles, and household appliances. It comprises multiple battery cells and a Battery Management System (BMS). The battery cells are connected in series and parallel to output the voltage required by the electric device. The BMS is the core control unit of the battery pack, responsible for ensuring the safe, efficient, and reliable operation of the battery.

[0003] As power tools and garden tools become increasingly specialized, the demand for high-voltage battery packs is growing. High-voltage battery packs typically refer to those with a voltage of 80V or higher, generally consisting of 20 or more cells connected in series. When the number of cells in the BMS reaches 20 or more series, two or more cascaded analog front-end (AFE) chips are used to acquire and preprocess analog signal data for each cell. However, multiple AFE chips have significant drawbacks: First, the power consumption of each chip is inconsistent, leading to voltage imbalances in the cell group after charging and discharging, affecting the battery pack's lifespan. Second, to reduce power consumption differences, the main control chip requires an external power supply instead of using the low dropout regulator (LDO) within the AFE chip, increasing costs. Third, during mass production, the high-side AFE chip may be abnormally awakened, causing leakage in the high-series cell group, which can render the battery unusable in severe cases. Utility Model Content

[0004] The purpose of this utility model is to provide a battery pack that can solve the problems of uneven cell voltage affecting battery pack life and high cost caused by external power supply.

[0005] To solve the above-mentioned technical problems, this utility model is achieved through the following technical solution:

[0006] This utility model provides a battery pack, the battery pack comprising at least:

[0007] A battery cell assembly, the battery cell assembly comprising at least 20 battery cells connected in series;

[0008] A single analog front-end chip, which is electrically connected to multiple cells in the cell group to monitor the status of the multiple cells, and the power input terminal of the analog front-end chip is electrically connected to the positive terminal of the cell group;

[0009] A main control chip, electrically connected to the analog front-end chip, is used to control the charging and discharging of the battery pack based on the monitoring results of the analog front-end chip; and

[0010] A power supply circuit is connected between the power input terminal of the analog front-end chip and the power input terminal of the main control chip, and is used to supply power to the main control chip.

[0011] In one embodiment of this utility model, the number of battery cells in the battery cell group is ≤24.

[0012] In one embodiment of this utility model, the voltage of the battery cell assembly is ≥72V.

[0013] In one embodiment of this utility model, the power supply circuit includes:

[0014] A current-limiting resistor, one end of which is electrically connected to the power input terminal of the analog front-end chip; and

[0015] A control transistor, one controlled terminal of which is electrically connected to the other end of the current-limiting resistor, the other controlled terminal of which is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip, and the control terminal of which is electrically connected to the drive output terminal of the analog front-end chip;

[0016] The current-limiting resistor, the control transistor, and the internal circuitry of the analog front-end chip form a low-dropout linear regulator to power the main control chip.

[0017] In one embodiment of the present invention, the battery pack further includes a breakpoint pad, which is connected in series between the power input terminal of the analog front-end chip and the positive terminal of the battery cell assembly. After production assembly is completed and the test is passed, the breakpoint pad will be connected by welding.

[0018] In one embodiment of this utility model, the control transistor is an NPN transistor or an NMOS transistor;

[0019] When the control transistor is an NPN transistor, the base of the NPN transistor is electrically connected to the drive output terminal of the analog front-end chip, the emitter is electrically connected to the other end of the current-limiting resistor, and the collector is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip.

[0020] When the control transistor is an NMOS transistor, the gate of the NMOS transistor is electrically connected to the drive output terminal of the analog front-end chip, the drain is electrically connected to the other end of the current limiting resistor, and the source is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip.

[0021] In one embodiment of the present invention, the battery pack further includes a current sensing resistor, which is connected in series between the negative terminal and the negative discharge terminal of the battery cell group, and the two ends of the current sensing resistor are electrically connected to the analog front-end chip. The analog front-end chip detects the voltage across the current sensing resistor and calculates the current flowing through the current sensing resistor.

[0022] In one embodiment of the present invention, the battery pack further includes a high-voltage drive module, which is controlled by the main control chip, and the high-voltage drive module outputs a drive signal to the control terminals of two transistors in the cell charging circuit.

[0023] In one embodiment of this utility model, the analog front-end chip integrates a high-voltage drive module, and the analog front-end chip outputs a high-side drive signal to the control terminals of two transistors in the battery cell charging circuit.

[0024] In one embodiment of the present invention, the battery pack includes a wake-up circuit, the input terminal of which receives an external wake-up signal, and the output terminal of which is electrically connected to the analog front-end chip.

[0025] In summary, the battery pack provided by this utility model uses an analog front-end chip to collect analog signal data from 20 to 24 cells in the battery pack and directly powers the main control chip through the analog front-end chip. On the one hand, it eliminates the need for an additional low-dropout linear regulator, effectively controlling costs. On the other hand, it avoids the problem of voltage imbalance in the cell group caused by inconsistent power consumption of two or more analog front-end chips after long-term charging and discharging, which can damage the battery pack's lifespan, thus strongly ensuring the stable operation and long-term use of the battery pack. Furthermore, it solves the problem of the main control chip and the high-voltage analog front-end chip being unable to communicate directly due to different reference grounds when using two or more analog front-end chips, requiring an additional isolation communication chip, further reducing the cost of the battery management circuit and improving the convenience and stability of system communication.

[0026] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this utility model, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1This is a circuit diagram of a battery management circuit for a battery pack with two analog front-end chips in the prior art.

[0029] Figure 2 This is a circuit diagram of the battery management circuit of a battery pack in one embodiment of this application.

[0030] Figure 3 This is a circuit diagram of the battery management circuit of the battery pack in another embodiment of this application.

[0031] Label Explanation:

[0032] 101. Breakpoint pad; 102. Wake-up circuit; 103. External communication circuit; 104. Power indicator light; 105. High-side driver module. Detailed Implementation

[0033] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model.

[0034] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this utility model. Therefore, the drawings only show the components related to this utility model and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0035] In this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0036] In the prior art, please refer to Figure 1When the number of battery cells in the BMS reaches 20 or more, two or more AFE chips are cascaded to collect and preprocess analog signal data for each cell. However, multiple AFE chips have significant drawbacks: First, the power consumption of each chip is inconsistent, which can lead to voltage imbalance in the cell group after charging and discharging, affecting the battery pack life; second, to reduce power consumption differences, the main control chip needs an external power supply instead of using the LDO inside the AFE chip, increasing costs; third, during mass production, the high-side AFE chip may be abnormally woken up, causing leakage in the high-series cell group, which can render the battery unusable in severe cases.

[0037] Please see Figure 2 and Figure 3 This application provides a battery pack that solves the problems of uneven cell voltage affecting battery pack life and high cost due to external power supply. The battery pack includes a battery management circuit as provided in this application and multiple battery cells. The multiple battery cells supply power to the battery management circuit, and the charging and discharging processes of the battery cells are controlled by the battery management circuit. In some optional embodiments, the battery pack may further include a housing, within which the battery management circuit and battery cells can be housed.

[0038] Please see Figure 2 In one embodiment of this invention, multiple battery cells are connected in series and / or in parallel to form a battery cell group. The voltage across the battery cell group meets the voltage and current requirements of the battery pack. In this embodiment, multiple battery cells are connected in series, with the number of cells being greater than or equal to 20. In this case, multiple battery cells can be used in conjunction with a single analog front-end chip. This simplifies circuit design and reduces hardware costs. Furthermore, it improves monitoring synchronization and data consistency, while reducing software complexity and communication risks.

[0039] In some alternative embodiments, the number of battery cells is specifically, for example, 20 to 24 cells in series. In this case, a single analog front-end chip can be used to detect the status of all battery cells, and the voltage of all battery cells matches the chip's power consumption, thus avoiding an increase in chip power consumption.

[0040] In some specific implementations, the voltage across each cell is greater than or equal to, for example, 3.6V, and the output voltage of the battery pack is greater than or equal to, for example, 72V.

[0041] The following example uses 20 battery cells, including cells C1, C2, C3... and C18, C19 through C20. Each cell has a voltage of, for example, 3.6V, so the total voltage of the cell group is 72V. It should be noted that 3.6V is the rated voltage of a single cell; the actual voltage of a cell may differ from its rated voltage depending on its condition and degree of aging.

[0042] Please see Figure 2 In one embodiment of this utility model, the positive terminal BAT+ of the battery cell assembly is electrically connected to the positive discharge terminal P+ of the battery pack, and the negative terminal BAT- of the battery cell assembly is electrically connected to the negative discharge terminal P- of the battery pack. The battery pack supplies power to the outside through the positive discharge terminal P+ and the negative discharge terminal P-. In this application, the positive charging terminal CH+ of the battery is separately set from the positive discharge terminal P+ of the battery pack. The positive charging terminal CH+ of the battery charges the battery cell assembly through the cell charging circuit. A fuse F1 is provided between the positive terminal BAT+ of the battery cell assembly and the positive discharge terminal P+ of the battery pack. At the same time, one end of the fuse F1 is electrically connected to the positive terminal BAT+ of the battery cell assembly, and the other end is electrically connected to the common terminal BMS of the positive discharge terminal P+ of the battery pack and the cell charging circuit, so that the fuse F1 can prevent excessive current during the charging and discharging processes of the battery pack. The negative charging terminal of the battery and the negative discharging terminal P- of the battery pack are set together, that is, the negative charging terminal of the battery and the negative discharging terminal P- of the battery pack use the same terminal.

[0043] Please see Figure 2 In one embodiment of this invention, the battery management circuit includes a single analog front-end chip (AFE), a main control chip (MCU), and a power supply circuit. The AFE collects analog signal data from multiple battery cells, converts this data into digital signal data, and transmits it to the MCU. The MCU receives the digital signal data from the AFE, processes it, and controls the battery cells. Furthermore, the MCU is powered by the AFE.

[0044] Please see Figure 2 In one embodiment of this invention, the battery management circuit includes only one analog front-end chip, namely a single analog front-end chip (AFE). Multiple signal acquisition terminals of the AFE are electrically connected to each cell in the battery pack to collect analog signal data from all cells in the battery pack and monitor the status of multiple cells. The analog signal data of the cells includes analog signal data such as voltage, temperature, and current. After the AFE collects the analog signal data from all cells in the battery pack, it converts the analog signal data into digital signal data for processing by the main control chip (MCU).

[0045] Please see Figure 2In one embodiment of this invention, the analog front-end chip (AFE) is powered by a battery cell. In this embodiment, the power input terminal BAT of the analog front-end chip AFE is electrically connected to the positive terminal BAT+ of the battery cell assembly, enabling the battery cell assembly to power the analog front-end chip AFE. In this application, a breakpoint pad 101 is connected in series between the power input terminal BAT of the analog front-end chip AFE and the positive terminal BAT+ of the battery cell assembly. After production and assembly are completed, the breakpoint pad 101 is soldered, thereby connecting the power input terminal BAT of the analog front-end chip AFE and the positive terminal BAT+ of the battery cell assembly, enabling the battery cell to power the analog front-end chip AFE. Connecting the breakpoint pad 101 by soldering after production and assembly are completed and testing is passed prevents the system from being abnormally woken up during assembly.

[0046] Please see Figure 2 In one embodiment of this invention, the negative terminal BAT- of the battery cell assembly is grounded, and a current sensing resistor R1 is connected in series between the negative terminal BAT- and the negative discharge terminal P- of the battery cell assembly. The two ends of the current sensing resistor R1 are electrically connected to the analog front-end chip AFE. At this time, the analog front-end chip AFE can detect the voltage across the current sensing resistor R1, and calculate the current flowing through the current sensing resistor R1, i.e., the charging current or the discharging current. During the charging and discharging process of the battery cell, if the current flowing through the current sensing resistor R1 is too large, the analog front-end chip AFE transmits the data signal of the charging current or discharging current to the main control chip MCU, which can then terminate the charging or discharging process.

[0047] Please see Figure 2 In one embodiment of this invention, the main control chip (MCU) can receive digital signal data from the battery cells collected by the analog front-end chip (AFE), and control the charging and discharging of the battery pack based on the monitoring results of the AFE. In this embodiment, the main control chip (MCU) and the analog front-end chip (AFE) communicate via an inter-integrated circuit (I2C) to achieve data transmission between them. In other embodiments, the main control chip (MCU) and the analog front-end chip (AFE) can also transmit data between them via a serial peripheral interface (SPI) or a universal asynchronous receiver / transmitter (UART).

[0048] Please see Figure 2In one embodiment of this invention, the main control chip (MCU) is powered by the analog front-end chip (AFE). In this case, the power input terminal of the MCU is electrically connected to the power input terminal BAT of the AFE, and a power supply circuit is connected in series between the power input terminals of the MCU and AFE. This power supply circuit includes a current-limiting resistor R2 and a control transistor Q3. Specifically, one end of the current-limiting resistor R2 is electrically connected to the power input terminal BAT of the AFE, and the other end is electrically connected to one controlled terminal of the control transistor Q3. The other controlled terminal of the control transistor Q3 is electrically connected to the power input terminal of the MCU and the voltage output terminal VMCU of the AFE. The control terminal of the control transistor Q3 is electrically connected to the AFE and is controlled by the drive output terminal MDRV of the AFE. At this time, the current-limiting resistor R2, the control transistor Q3, and the internal circuit of the analog front-end chip AFE form a low-dropout linear regulator. While the battery pack supplies power to the analog front-end chip AFE through the breakpoint pad 101, it also supplies power to the main control chip MCU through the low-dropout linear regulator formed by the current-limiting resistor R2, the control transistor Q3, and the internal circuit of the analog front-end chip AFE.

[0049] Please see Figure 2 In one embodiment of this invention, the control transistor Q3 is, for example, a bipolar junction transistor (BJT), a transistor, or another control transistor Q3 with a voltage drop. When the control transistor Q3 is a BJT, it is an NPN BJT. The base of the NPN BJT is electrically connected to the drive output terminal MDRV of the analog front-end chip AFE, the emitter is electrically connected to the other end of the current-limiting resistor R2, and the collector is electrically connected to the power input terminal of the main control chip MCU and the voltage output terminal VMCU of the analog front-end chip AFE. When the control transistor Q3 is a transistor, it is an NMOS transistor. The gate of the NMOS transistor is electrically connected to the drive output terminal MDRV of the analog front-end chip AFE, the drain is electrically connected to the other end of the current-limiting resistor R2, and the source is electrically connected to the power input terminal of the main control chip MCU and the voltage output terminal VMCU of the analog front-end chip AFE. At this point, the current-limiting resistor R2, the control transistor Q3, and the internal circuitry of the analog front-end chip AFE form a low-dropout linear regulator. The power input terminal BAT of the analog front-end chip AFE corresponds to the voltage input terminal of the low-dropout linear regulator, and the other controlled terminal of the control transistor Q3 corresponds to the voltage output terminal of the low-dropout linear regulator. The current-limiting resistor R2 limits the current at the voltage input terminal of the main control chip MCU, and the control transistor Q3 controls the switching of the voltage input to the main control chip MCU. Simultaneously, through the regulation of the analog front-end chip AFE and the control transistor Q3, a voltage reduction can be achieved from the power input terminal BAT of the analog front-end chip AFE to the voltage input terminal of the main control chip MCU, providing, for example, a 3.3V voltage to the main control chip MCU's voltage input terminal.

[0050] Please see Figure 2 In one embodiment of this invention, a wake-up circuit 102 is provided between the main control chip MCU and the analog front-end chip AFE. The wake-up circuit 102 receives the MCU enable signal MCU-EN, external wake-up signals COM and KEY at its input terminals. The output of the wake-up circuit is electrically connected to the analog front-end chip AFE. A diode is provided at the input terminal of each external wake-up signal in the wake-up circuit 102 to prevent signal backflow. Examples include diode D3 at the MCU-EN input terminal, diode D1 at the KEY input terminal, and diode D2 at the COM input terminal. The battery pack is removable. When used alone, it manages low power consumption. When an external charger or tool is connected to the battery pack, the peripheral device pulls the external wake-up signal COM high, which wakes up the analog front-end chip AFE via the wake-up circuit. The external wake-up signal KEY is generated by a button on the battery pack. Pressing the button generates the external wake-up signal KEY to wake up the battery pack and check the remaining power. After the analog front-end chip (AFE) is woken up by an external wake-up signal, the AFE can output, for example, 3.3V power to the main control chip (MCU). After the main control chip (MCU) is initialized, it will pull up the enable signal MCU-EN pin, which in turn will continuously pull up the wake-up pin of the analog front-end chip (AFE).

[0051] Please see Figure 2 In one embodiment of this utility model, the battery management circuit further includes an external communication circuit 103, which is, for example, a COM communication circuit. Through the external communication circuit 103, information exchange between the battery pack and the charger and its tools can be realized.

[0052] Please see Figure 2 In one embodiment of this utility model, the battery management circuit further includes a power indicator light 104. The power indicator light 104 is electrically connected to the main control chip MCU and can display the battery pack's state of charge (SOC). For example, when the battery pack's charge is less than a set threshold, it is displayed in red. When the battery pack's charge is greater than or equal to the set threshold, it is displayed in green.

[0053] Please see Figure 2In one embodiment of this utility model, the battery cell charging circuit includes two transistors arranged opposite each other, specifically two NMOS transistors arranged opposite each other. In this case, the two NMOS transistors are connected with a common drain. The two NMOS transistors are, for example, a first NMOS transistor Q1 and a second NMOS transistor Q2. The source of the first NMOS transistor Q1 is electrically connected to the common terminal BMS of the fuse F1 and the positive discharge terminal P+ of the battery. The drain of the first NMOS transistor Q1 is electrically connected to the drain of the second NMOS transistor Q2, and the source of the second NMOS transistor Q2 is electrically connected to the positive charging terminal CH+ of the battery. The gates of the first NMOS transistor Q1 and the second NMOS transistor Q2 are input to the high-side drive signal of the analog front-end chip AFE or the drive signal of the high-side drive module 105.

[0054] Please see Figure 2 In one embodiment of this invention, the analog front-end chip (AFE) does not integrate a high-side drive module; instead, a high-side drive module 105 is provided in the battery management circuit. In this case, the gates of the first NMOS transistor Q1 and the second NMOS transistor Q2 receive drive signals from the high-side drive module 105, and the high-side drive module 105 is controlled by the main control chip (MCU), receiving control signals CH-DR and DIS-DR from the MCU. The high-side drive module 105 is, for example, composed of a Texas Instruments BQ76200 high-voltage side FET driver. Thus, by controlling the high-side drive module 105 through the MCU, the on / off state of the battery cell charging circuit is controlled.

[0055] Please see Figure 3 In another embodiment of this invention, a high-side drive module is integrated into the analog front-end chip (AFE). In this case, the gates of the first NMOS transistor Q1 and the second NMOS transistor Q2 are input to the high-side drive signals CH-DR and DIS-DR of the analog front-end chip (AFE). The analog front-end chip (AFE) then controls the on / off state of the battery cell charging circuit.

[0056] In summary, this utility model provides a battery pack, which includes the battery management circuit and cell assembly provided in this application. The cell assembly supplies power to the battery management circuit, and the charging and discharging processes of the cells are controlled by the battery management circuit. The cell assembly includes at least 20 cells connected in series. The battery management circuit includes a single analog front-end chip, a main control chip, and a power supply circuit. The single analog front-end chip is electrically connected to multiple cells in the cell assembly to monitor the status of the multiple cells. The power input terminal of the analog front-end chip is electrically connected to the positive terminal of the cell assembly. The main control chip is electrically connected to the analog front-end chip and controls the charging and discharging of the battery pack based on the monitoring results of the analog front-end chip. The power supply circuit is connected between the power input terminal of the analog front-end chip and the power input terminal of the main control chip to supply power to the main control chip.

[0057] The embodiments of this utility model disclosed above are merely illustrative of the present utility model. The embodiments do not exhaustively describe all details, nor do they limit the utility model to the specific implementations described. Obviously, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of this utility model, thereby enabling those skilled in the art to better understand and utilize it. This utility model is limited only by the claims and their full scope and equivalents.

Claims

1. A battery pack, characterized in that, The battery pack includes at least: A battery cell assembly, the battery cell assembly comprising at least 20 battery cells connected in series; A single analog front-end chip, which is electrically connected to multiple cells in the cell group to monitor the status of the multiple cells, and the power input terminal of the analog front-end chip is electrically connected to the positive terminal of the cell group; A main control chip, electrically connected to the analog front-end chip, is used to control the charging and discharging of the battery pack based on the monitoring results of the analog front-end chip; and A power supply circuit is connected between the power input terminal of the analog front-end chip and the power input terminal of the main control chip, and is used to supply power to the main control chip.

2. The battery pack according to claim 1, characterized in that, The number of cells in the cell group is ≤24.

3. The battery pack according to claim 1, characterized in that, The voltage of the battery cell assembly is ≥72V.

4. The battery pack according to claim 1, characterized in that, The power supply circuit includes: A current-limiting resistor, one end of which is electrically connected to the power input terminal of the analog front-end chip; and A control transistor, one controlled terminal of which is electrically connected to the other end of the current-limiting resistor, the other controlled terminal of which is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip, and the control terminal of which is electrically connected to the drive output terminal of the analog front-end chip; The current-limiting resistor, the control transistor, and the internal circuitry of the analog front-end chip form a low-dropout linear regulator to power the main control chip.

5. The battery pack according to claim 4, characterized in that, The battery pack also includes a breakpoint pad, which is connected in series between the power input terminal of the analog front-end chip and the positive terminal of the battery cell assembly. After production assembly is completed and the test is passed, the breakpoint pad will be connected by welding.

6. The battery pack according to claim 4, characterized in that, The control transistor is an NPN transistor or an NMOS transistor; When the control transistor is an NPN transistor, the base of the NPN transistor is electrically connected to the drive output terminal of the analog front-end chip, the emitter is electrically connected to the other end of the current-limiting resistor, and the collector is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip. When the control transistor is an NMOS transistor, the gate of the NMOS transistor is electrically connected to the drive output terminal of the analog front-end chip, the drain is electrically connected to the other end of the current limiting resistor, and the source is electrically connected to the power input terminal of the main control chip and the voltage output terminal of the analog front-end chip.

7. The battery pack according to claim 1, characterized in that, The battery pack also includes a current sensing resistor, which is connected in series between the negative terminal and the negative discharge terminal of the cell group, and the two ends of the current sensing resistor are electrically connected to the analog front-end chip. The analog front-end chip detects the voltage across the current sensing resistor and calculates the current flowing through the current sensing resistor.

8. The battery pack according to claim 1, characterized in that, The battery pack also includes a high-voltage drive module, which is controlled by the main control chip, and the high-voltage drive module outputs drive signals to the control terminals of two transistors in the cell charging circuit.

9. The battery pack according to claim 1, characterized in that, The analog front-end chip integrates a high-voltage drive module, and the analog front-end chip outputs a high-side drive signal to the control terminals of two transistors in the battery cell charging circuit.

10. The battery pack according to claim 1, characterized in that, The battery pack includes a wake-up circuit, the input of which receives an external wake-up signal, and the output of which is electrically connected to the analog front-end chip.

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