System power-down data protection circuit

Abstract

The utility model discloses a kind of system power-off data protection circuit, it is related to power-off protection technical field, including: equipment system, DC input module, power-down detection circuit, super capacitor discharge control circuit, voltage reducing circuit, standby power charging circuit, super capacitor energy storage module;Power-down detection circuit and DC input module and equipment system are electrically connected;Voltage reducing circuit and DC input module and standby power charging system are electrically connected, one end of super capacitor energy storage module and standby power charging system are electrically connected, the other end is connected with super capacitor discharge control circuit, super capacitor discharge control circuit is connected with equipment system, equipment system and DC input module are electrically connected;By using super capacitor energy storage, charge when current is stable, release when power-off, to reach in the case where not increasing battery, when power-off, certain energy can be provided to maintain equipment system processing data save and according to normal power-down timing shutdown.

Description

Technical Field

[0001] This utility model relates to the field of power failure protection technology, specifically to a system power failure data protection circuit. Background Technology

[0002] Most current edge computing terminals and all-in-one machines with screens do not use battery power, but instead use AC power to DC power. When the AC power fails, the entire machine will lose power quickly, and the software system will be unable to handle data saving. This may result in the loss of user data, and in severe cases, system files may be damaged.

[0003] Current hardware designs often address these issues by adding polymer batteries. However, this approach is costly, and the added battery increases certification fees and stringent requirements. Polymer batteries have relatively low discharge rates, necessitating large capacities to maintain high transient currents, further increasing costs.

[0004] In view of this situation, it is necessary to provide a system power failure data protection circuit that uses a supercapacitor as the energy storage carrier and combines it with a comparator circuit to determine the mains power status. If a power failure occurs, a response trigger mechanism will be activated, and the software will immediately switch to the supercapacitor to maintain the system power supply. At the same time, high-power-consuming peripherals will be shut down, and the limited energy will be used to maintain the normal preservation of system response data and the software shutdown action to solve the above problems. Utility Model Content

[0005] To achieve the above objectives, this utility model provides the following technical solution: a system power failure data protection circuit, including a device system and a DC input module electrically connected to the device system, further including a power failure detection circuit, a supercapacitor discharge control circuit, a step-down circuit, a backup power charging circuit, and a supercapacitor energy storage module; the power failure detection circuit is electrically connected to the DC input module and the device system and detects the status of the DC input module; the step-down circuit is electrically connected to the connection line between the DC input module and the backup power charging circuit and reduces the output voltage of the DC input module; the backup power charging circuit is electrically connected to the device system and the supercapacitor energy storage module and charges the supercapacitor energy storage module; the supercapacitor discharge control circuit is electrically connected to the device system, and is also electrically connected to the connection line between the device system and the DC input module, and controls the supercapacitor energy storage module to discharge to supply power to the device system.

[0006] Furthermore, as a preferred embodiment, the power failure detection circuit includes a power conversion module and a voltage comparison and detection module. The power conversion module converts the DC power input into a stable low voltage, and the voltage comparison and detection module detects the output voltage of the power conversion module and outputs a status signal.

[0007] Furthermore, as a preferred embodiment, the power conversion module includes a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first capacitor is electrically connected to the input voltage, and the other end is grounded. The input voltage is connected to the first pin of the power conversion chip. One end of the first resistor is electrically connected to the input voltage, and the other end is electrically connected to the second resistor. The other end of the second resistor is grounded. The common node of the first and second resistors is electrically connected to the third pin of the power conversion chip. The fifth pin of the power conversion chip outputs a first output voltage. One end of the third resistor is electrically connected to the fifth pin of the power conversion chip, and the other end is electrically connected to the fourth resistor. The other end of the fourth resistor is grounded. The common node of the third and fourth resistors is electrically connected to the fourth pin of the power conversion chip. One end of both the second and third capacitors is electrically connected to the fifth pin of the power conversion chip, and the other end of both capacitors is grounded.

[0008] Furthermore, as a preferred embodiment, the voltage comparison and detection module includes a fifth resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a comparison chip, and a fourth capacitor; One end of the fifth resistor is electrically connected to the second input voltage, and the other end is electrically connected to the sixth resistor. The other end of the sixth resistor is grounded. The common node of the fifth and sixth resistors is electrically connected to pin three of the comparator chip. One end of the seventh resistor is electrically connected to pin five of the power conversion chip, and the other end is electrically connected to the eighth resistor. The other end of the eighth resistor is grounded. The common node of the seventh and eighth resistors is electrically connected to pin one of the comparator chip. The fourth capacitor and the ninth resistor form an RC filter circuit. One end of the ninth resistor is electrically connected to the first external voltage, and the other end is electrically connected to pin four of the comparator chip. One end of the fourth capacitor is electrically connected to pin four of the comparator chip, and the other end is grounded. One end of the tenth resistor is electrically connected to pin five of the comparator chip, and the other end is electrically connected to the second input voltage. One end of the eleventh resistor is electrically connected to pin five of the comparator chip.

[0009] Furthermore, as a preferred embodiment, the step-down circuit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a step-down converter chip, a first inductor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. The fifth and sixth capacitors are connected in parallel. One end of each of the fifth and sixth capacitors is electrically connected to the input voltage, and the other end is grounded. The input voltage is electrically connected to pin 5 of the buck converter chip. One end of the twelfth resistor is electrically connected to the input voltage, and the other end is electrically connected to pin 8 of the buck converter chip. One end of the seventh capacitor is electrically connected to pin 7 of the buck converter chip, and the other end is connected to pin 6 of the buck converter chip. One end of each of the eighth, ninth, and tenth capacitors is electrically connected to the first inductor, and the other end is grounded. The other end of the inductor is electrically connected to pin 6 of the buck converter chip. One end of the thirteenth resistor is electrically connected to one end of the first inductor, the eighth capacitor, the ninth capacitor, and the tenth capacitor. The other end of the thirteenth resistor is electrically connected to the fourteenth resistor. The other end of the fourteenth resistor is grounded. The common node of the thirteenth and fourteenth resistors is electrically connected to pin 1 of the buck converter chip. One end of the fifteenth resistor is electrically connected to pin 2 of the buck converter chip, and the other end is grounded. The first inductor outputs a third output voltage by connecting one end of the eighth, ninth, and tenth capacitors.

[0010] Furthermore, as a preferred embodiment, the backup power charging circuit includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a light-emitting diode, and a charging management chip. The third output voltage input circuit comprises the following: one end of the eleventh capacitor is electrically connected to the third output voltage, and the other end is grounded; one end of the fifteenth resistor is electrically connected to the third output voltage, and the other end is electrically connected to the anode of the light-emitting diode and the VIN pin of the charging management chip; the cathode of the light-emitting diode is electrically connected to the PG pin of the charging management chip; the FB pin of the charging management chip is electrically connected to the sixteenth and seventeenth resistors; the other end of the sixteenth resistor is grounded; the other end of the seventeenth resistor is connected to the supercapacitor energy storage module and the TOP pin of the charging management chip; the TOP pin of the charging management chip is electrically connected to the twelfth capacitor; the other end of the twelfth capacitor is connected to the thirteenth capacitor; one end of the thirteenth capacitor connected to the twelfth capacitor is connected to the eighteenth resistor; the other end of the eighteenth resistor is electrically connected to the MID pin of the charging management chip; the ISET pin of the charging management chip is electrically connected to the nineteenth resistor; and the other end of the nineteenth resistor is grounded.

[0011] Furthermore, as a preferred embodiment, the supercapacitor energy storage module includes an energy storage capacitor; the seventeenth resistor is connected to the positive terminal of the energy storage capacitor, and the positive terminal of the energy storage capacitor outputs a second input voltage.

[0012] Furthermore, as a preferred embodiment, the supercapacitor discharge control circuit includes a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a first P-channel MOSFET, a second P-channel MOSFET, a first transistor, and a second transistor. The positive terminal of the energy storage capacitor is electrically connected to the fourteenth capacitor, the fifteenth capacitor, the twentieth resistor, and the source of the first P-channel MOSFET. The other end of the fourteenth capacitor is grounded. The other end of the fifteenth capacitor is electrically connected to the twenty-second resistor. The other end of the twenty-first resistor is electrically connected to the twenty-second resistor. The drain of the first P-channel MOSFET is electrically connected to the drain of the second P-channel MOSFET. The source of the second P-channel MOSFET is connected to the second input voltage. The source of the second P-channel MOSFET is connected to the fifteenth capacitor. The other end of the fifteenth capacitor is grounded. The gates of both the first and second P-channel MOSFETs are connected to... The 22nd resistor is electrically connected, and one end of the 22nd resistor is connected to the gate of the 15th capacitor, the 20th resistor, the first P-channel MOSFET, and the second P-channel MOSFET. The other end of the 22nd resistor is connected to the collector of the first transistor. The base of the first transistor is electrically connected to the 21st resistor. The other end of the 21st resistor is electrically connected to the 23rd resistor and the collector of the second transistor. The other end of the 23rd resistor is connected to the second external power supply. The base of the second transistor is electrically connected to the 24th and 25th resistors. The other end of the 24th resistor is connected to the status signal. The other end of the 25th resistor is grounded.

[0013] Compared with the prior art, this utility model provides a system power failure data protection circuit, which has the following beneficial effects: In this embodiment of the invention, when dealing with a single DC-powered system, the energy required to maintain system operation disappears immediately after a DC power failure. Because this process is irregular and unpredictable, the software cannot handle this anomaly, leading to a risk of data loss. Furthermore, because this abnormal power outage prevents the system from following the required shutdown sequence, there is a risk of system or hardware crashes due to disordered power outage timing. In this case, using a supercapacitor instead of the traditional battery solution saves on battery costs and eliminates the need for additional certification requirements and expenses. Attached Figure Description

[0014] Figure 1 This is a system block diagram of a system power-off data protection circuit; Figure 2 A circuit diagram of a power-off detection circuit for a system power-off data protection circuit provided in this embodiment of the present invention; Figure 3 A step-down circuit diagram of a system power failure data protection circuit provided for an embodiment of this utility model; Figure 4 The present invention provides a circuit diagram of a backup power charging circuit, a supercapacitor energy storage module, and a supercapacitor discharge control circuit for a system power failure data protection circuit. Detailed Implementation

[0015] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the present utility model.

[0016] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in this utility model embodiment are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0017] Furthermore, the use of terms such as "first" and "second" in this utility model is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this utility model.

[0018] Please see Figures 1-4 In this embodiment of the invention, the device system includes a DC input module, a power failure detection circuit, a supercapacitor discharge control circuit, a step-down circuit, a backup power charging circuit, and a supercapacitor energy storage module. The power failure detection circuit is electrically connected to the DC input module and the device system and detects the status of the DC input module. The step-down circuit is electrically connected to the connection line between the DC input module and the backup power charging circuit and reduces the output voltage of the DC input module. The backup power charging circuit is electrically connected to the device system and the supercapacitor energy storage module and charges the supercapacitor energy storage module. The supercapacitor discharge control circuit is electrically connected to the device system and also electrically connected to the connection line between the device system and the DC input module, and controls the supercapacitor energy storage module to discharge to supply power to the device system. In this embodiment, as Figure 2 The power failure detection circuit includes a power conversion module and a voltage comparison and detection module. The power conversion module converts the DC power input into a stable low voltage, and the voltage comparison and detection module detects the output voltage of the power conversion module and outputs a status signal.

[0019] The power conversion module includes a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor. One end of the first capacitor is electrically connected to the input voltage, and the other end is grounded. The input voltage is connected to the first pin (IN) of the power conversion chip. One end of the first resistor is electrically connected to the input voltage, and the other end is electrically connected to the second resistor. The other end of the second resistor is grounded. The common node of the first and second resistors is electrically connected to the third pin (EN) of the power conversion chip. The fifth pin (OUT) of the power conversion chip outputs the first output voltage. One end of the third resistor is electrically connected to the fifth pin (OUT) of the power conversion chip, and the other end is electrically connected to the fourth resistor. The other end of the fourth resistor is grounded. The common node of the third and fourth resistors is electrically connected to the fourth pin (FB) of the power conversion chip. One end of both the second and third capacitors is electrically connected to the fifth pin (OUT) of the power conversion chip, and the other end is grounded.

[0020] The voltage comparison and detection module includes a fifth resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a comparator chip, and a fourth capacitor. One end of the fifth resistor is electrically connected to the second input voltage, and the other end is electrically connected to the sixth resistor. The other end of the sixth resistor is grounded. The common node of the fifth and sixth resistors is electrically connected to pin 3 (IN-) of the comparator chip. One end of the seventh resistor is electrically connected to pin 5 (OUT) of the power conversion chip, and the other end is electrically connected to the eighth resistor. The other end of the eighth resistor is grounded. The common node of the seventh and eighth resistors is electrically connected to pin 1 (IN+) of the comparator chip. The fourth capacitor and the ninth resistor form an RC filter circuit. One end of the ninth resistor is electrically connected to the first external voltage VCC_1V8_S3, and the other end is electrically connected to pin 4 of the comparator chip. One end of the fourth capacitor is electrically connected to pin 4 of the comparator chip, and the other end is grounded. One end of the tenth resistor is electrically connected to pin 5 (V+) of the comparator chip, and the other end is electrically connected to the second input voltage VF_5V5. One end of the eleventh resistor is electrically connected to pin 5 of the comparator chip.

[0021] In this embodiment, as Figure 3The step-down circuit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a step-down converter chip, a first inductor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor. The fifth and sixth capacitors are connected in parallel, with one end electrically connected to the input voltage and the other end grounded. The input voltage is electrically connected to pin 5 (IN) of the step-down converter chip. One end of the twelfth resistor is electrically connected to the input voltage, and the other end is electrically connected to pin 8 (EN) of the step-down converter chip. One end of the seventh capacitor is electrically connected to pin 7 of the step-down converter chip, and the other end is connected to pin 6 of the step-down converter chip. One end of capacitors eight, nine, and ten is electrically connected to the first inductor, and the other end is grounded. The other end of the first inductor is electrically connected to pin 6 (LX) of the buck converter chip. One end of resistor thirteen is electrically connected to one end of the first inductor, the eighth capacitor, the ninth capacitor, and the tenth capacitor. The other end of resistor thirteen is electrically connected to resistor fourteen. The other end of resistor fourteen is grounded. The common node of resistors thirteen and fourteen is electrically connected to pin 1 (FB) of the buck converter chip. One end of resistor fifteen is electrically connected to pin 2 of the buck converter chip, and the other end is grounded. The first inductor is connected to one end of capacitors eight, nine, and ten to output the third output voltage.

[0022] In this embodiment, as Figure 4 The backup power charging circuit includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, an LED, and a charging management chip. The third output voltage input circuit has one end of the eleventh capacitor electrically connected to the third output voltage and the other end grounded. One end of the fifteenth resistor is electrically connected to the third output voltage, and the other end is electrically connected to the anode of the LED and the VIN pin of the charging management chip. The cathode of the LED is electrically connected to the PG pin of the charging management chip. The FB pin of the charging management chip is electrically connected to the sixteenth and seventeenth resistors. The other end of the sixteenth resistor is grounded. The other end of the seventeenth resistor is connected to the supercapacitor energy storage module and the TOP pin of the charging management chip. The TOP pin of the charging management chip is electrically connected to the twelfth capacitor. The other end of the twelfth capacitor is connected to the thirteenth capacitor. One end of the thirteenth capacitor is connected to the twelfth capacitor and the eighteenth resistor. The other end of the eighteenth resistor is electrically connected to the MID pin of the charging management chip. The ISET pin of the charging management chip is electrically connected to the nineteenth resistor, and the other end of the nineteenth resistor is grounded.

[0023] The supercapacitor energy storage module includes an energy storage capacitor; the seventeenth resistor is connected to the positive terminal of the energy storage capacitor, and the positive terminal of the energy storage capacitor outputs the second input voltage VF_5V5.

[0024] The supercapacitor discharge control circuit includes a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a first P-channel MOSFET, a second P-channel MOSFET, a first transistor, and a second transistor. The positive terminal of the energy storage capacitor is electrically connected to the fourteenth capacitor, the fifteenth capacitor, the twentieth resistor, and the source of the first P-channel MOSFET. The other end of the fourteenth capacitor is grounded. The other end of the fifteenth capacitor is electrically connected to the twenty-second resistor. The other end of the twentyth resistor is electrically connected to the twenty-second resistor. The drain of the first P-channel MOSFET is electrically connected to the drain of the second P-channel MOSFET. The source of the second P-channel MOSFET is connected to the second input voltage. The source of the P-channel MOSFET is connected to the fifteenth capacitor, and the other end of the fifteenth capacitor is grounded. The gates of the first P-channel MOSFET and the second P-channel MOSFET are both electrically connected to the twenty-second resistor. One end of the twenty-second resistor is connected to the fifteenth capacitor, the twentieth resistor, and the gates of the first P-channel MOSFET and the second P-channel MOSFET, and the other end is connected to the collector of the first transistor. The base of the first transistor is electrically connected to the twenty-first resistor. The other end of the twenty-first resistor is electrically connected to the twenty-third resistor and the collector of the second transistor. The other end of the twenty-third resistor is connected to the second external power supply. The base of the second transistor is electrically connected to the twenty-fourth resistor and the twenty-fifth resistor. The other end of the twenty-fourth resistor is connected to the status signal, and the other end of the twenty-fifth resistor is grounded.

[0025] Specifically, in the power-down detection circuit, the input voltage is DCIN_24V, which is sent from the DC input module (DC-IN) to the power-down detection circuit. After passing through the power conversion chip, the first output voltage is a stable 10V voltage (LDO_10V). The first capacitor is connected in parallel with the input voltage to filter out high-frequency noise and stabilize the input. The first resistor and the second resistor are connected in series and grounded. The first resistor plays the role of current limiting and voltage division, and together with the first capacitor, it further stabilizes the input voltage. The third resistor and the fourth resistor realize the voltage regulation control of the output 10V voltage. The second capacitor and the third capacitor are used to filter out the ripple of the output voltage.

[0026] The second input voltage is output from the supercapacitor discharge control circuit. After being divided by the fifth resistor, a voltage of 2.2V is obtained and connected to the IN- pin of the comparator chip. The output 10V voltage is divided by the seventh and eighth resistors to obtain a voltage of 2.5V and connected to the IN+ pin of the comparator chip. The power supply terminal of the comparator chip is connected to the supercapacitor energy storage module. The comparator chip outputs the BAT_INT_L signal, which is input to the supercapacitor discharge control circuit to control the energy storage capacitor.

[0027] In the buck converter circuit, the input voltage is DCIN_24V, which is input from the DC input module (DC-IN). The buck converter chip outputs a stable DC voltage after bucking and filtering to power the backup power charging circuit. The fifth and sixth capacitors are input filter capacitors, used to filter out high-frequency noise and ripple in the input voltage, making the voltage input to the chip more stable. The twelfth resistor is connected to the enable terminal of the buck converter chip. The first inductor is an energy storage inductor. The eighth, ninth, and tenth capacitors are used to filter out high-frequency ripple in the output voltage, making the high-frequency characteristics of the output voltage better. The third output voltage VCC_BACK is output to the backup power charging circuit.

[0028] The backup power charging circuit inputs the third output voltage VCC_BACK. The eleventh capacitor is connected in parallel across VCC_BACK to filter and stabilize the input voltage, reducing the impact of voltage fluctuations on subsequent circuits. The fifteenth resistor limits the current and is connected to the LED, which serves as a charging status indicator. The charging management chip converts and regulates the input power to achieve efficient and precise charging of the energy storage capacitor. The sixteenth and seventeenth resistors form a voltage divider circuit to provide feedback voltage to the FB pin of the charging management chip, enabling U3 to adjust the output voltage according to this feedback voltage to ensure that the charging voltage meets the design requirements. The nineteenth resistor is used to set the charging current parameter, and the twelfth and thirteenth capacitors filter and stabilize the voltage.

[0029] The energy storage capacitor is a farad capacitor, and the output second input voltage VF_5V5 is sent to the voltage comparison and detection module of the power failure detection circuit.

[0030] In the supercapacitor discharge control circuit, the fifteenth capacitor filters and regulates the output second input voltage, which is 5V. This second input voltage is connected to the voltage comparison and detection module of the power-down detection circuit. The twenty-fourth resistor is connected to the BAT_INT_L signal output by the power-down detection circuit. The eleventh capacitor is used to filter and regulate the second input voltage VF_5V5. The first P-channel MOSFET, the second P-channel MOSFET, the first transistor, and the second transistor are controlled to open and close by the BAT_INT_L signal output by the power-down detection circuit, and they also supply power to the power-down detection circuit when the mains power is interrupted.

[0031] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A system power failure data protection circuit, comprising a device system and a DC input module electrically connected to the device system, characterized in that, It also includes a power failure detection circuit, a supercapacitor discharge control circuit, a step-down circuit, a backup power charging circuit, and a supercapacitor energy storage module. The power failure detection circuit is electrically connected to the DC input module and the equipment system and detects the status of the DC input module. The step-down circuit is electrically connected to the connection line between the DC input module and the backup power charging circuit and reduces the output voltage of the DC input module. The backup power charging circuit is electrically connected to the equipment system and the supercapacitor energy storage module and charges the supercapacitor energy storage module. The supercapacitor discharge control circuit is electrically connected to the equipment system and is also electrically connected to the connection line between the equipment system and the DC input module, and controls the supercapacitor energy storage module to discharge to supply power to the equipment system.

2. The system power failure data protection circuit according to claim 1, characterized in that: The power failure detection circuit includes a power conversion module and a voltage comparison and detection module. The power conversion module converts the DC input module into a stable low voltage, and the voltage comparison and detection module detects the output voltage of the power conversion module and outputs a status signal.

3. The system power failure data protection circuit according to claim 2, characterized in that: The power conversion module includes a first capacitor, a second capacitor, a third capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first capacitor is electrically connected to the input voltage, and the other end is grounded. The input voltage is connected to the first pin of the power conversion chip. One end of the first resistor is electrically connected to the input voltage, and the other end is electrically connected to the second resistor. The other end of the second resistor is grounded. The common node of the first and second resistors is electrically connected to the third pin of the power conversion chip. The fifth pin of the power conversion chip outputs a first output voltage. One end of the third resistor is electrically connected to the fifth pin of the power conversion chip, and the other end is electrically connected to the fourth resistor. The other end of the fourth resistor is grounded. The common node of the third and fourth resistors is electrically connected to the fourth pin of the power conversion chip. One end of both the second and third capacitors is electrically connected to the fifth pin of the power conversion chip, and the other end of both capacitors is grounded.

4. The system power failure data protection circuit according to claim 3, characterized in that: The voltage comparison and detection module includes a fifth resistor, a sixth resistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, a comparison chip, and a fourth capacitor; One end of the fifth resistor is electrically connected to the second input voltage, and the other end is electrically connected to the sixth resistor. The other end of the sixth resistor is grounded. The common node of the fifth and sixth resistors is electrically connected to pin three of the comparator chip. One end of the seventh resistor is electrically connected to pin five of the power conversion chip, and the other end is electrically connected to the eighth resistor. The other end of the eighth resistor is grounded. The common node of the seventh and eighth resistors is electrically connected to pin one of the comparator chip. The fourth capacitor and the ninth resistor form an RC filter circuit. One end of the ninth resistor is electrically connected to the first external voltage, and the other end is electrically connected to pin four of the comparator chip. One end of the fourth capacitor is electrically connected to pin four of the comparator chip, and the other end is grounded. One end of the tenth resistor is electrically connected to pin five of the comparator chip, and the other end is electrically connected to the second input voltage. One end of the eleventh resistor is electrically connected to pin five of the comparator chip.

5. A system power failure data protection circuit according to claim 3, characterized in that: The step-down circuit includes a fifth capacitor, a sixth capacitor, a seventh capacitor, an eighth capacitor, a ninth capacitor, a tenth capacitor, a step-down converter chip, a first inductor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, and a fifteenth resistor; The fifth and sixth capacitors are connected in parallel. One end of each of the fifth and sixth capacitors is electrically connected to the input voltage, and the other end is grounded. The input voltage is electrically connected to pin 5 of the buck converter chip. One end of the twelfth resistor is electrically connected to the input voltage, and the other end is electrically connected to pin 8 of the buck converter chip. One end of the seventh capacitor is electrically connected to pin 7 of the buck converter chip, and the other end is connected to pin 6 of the buck converter chip. One end of each of the eighth, ninth, and tenth capacitors is electrically connected to the first inductor, and the other end is grounded. The other end of the inductor is electrically connected to pin 6 of the buck converter chip. One end of the thirteenth resistor is electrically connected to one end of the first inductor, the eighth capacitor, the ninth capacitor, and the tenth capacitor. The other end of the thirteenth resistor is electrically connected to the fourteenth resistor. The other end of the fourteenth resistor is grounded. The common node of the thirteenth and fourteenth resistors is electrically connected to pin 1 of the buck converter chip. One end of the fifteenth resistor is electrically connected to pin 2 of the buck converter chip, and the other end is grounded. The first inductor outputs a third output voltage by connecting one end of the eighth, ninth, and tenth capacitors.

6. A system power failure data protection circuit according to claim 5, characterized in that: The backup power charging circuit includes an eleventh capacitor, a twelfth capacitor, a thirteenth capacitor, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor, an eighteenth resistor, a nineteenth resistor, a light-emitting diode, and a charging management chip; In the third output voltage input circuit, one end of the eleventh capacitor is electrically connected to the third output voltage, and the other end is grounded. One end of the fifteenth resistor is electrically connected to the third output voltage, and the other end is electrically connected to the anode of the light-emitting diode and the VIN pin of the charging management chip. The cathode of the light-emitting diode is electrically connected to the PG pin of the charging management chip. The FB pin of the charging management chip is electrically connected to the sixteenth and seventeenth resistors. The other end of the sixteenth resistor is grounded. The other end of the seventeenth resistor is connected to the TOP pin of the charging management chip. The TOP pin of the charging management chip is electrically connected to the twelfth capacitor. The other end of the twelfth capacitor is connected to the thirteenth capacitor. One end of the thirteenth capacitor connected to the twelfth capacitor is connected to the eighteenth resistor. The other end of the eighteenth resistor is electrically connected to the MID pin of the charging management chip. The ISET pin of the charging management chip is electrically connected to the nineteenth resistor, and the other end of the nineteenth resistor is grounded.

7. A system power failure data protection circuit according to claim 6, characterized in that: The supercapacitor energy storage module includes an energy storage capacitor; the seventeenth resistor is connected to the positive terminal of the energy storage capacitor, and the positive terminal of the energy storage capacitor outputs a second input voltage.

8. A system power failure data protection circuit according to claim 7, characterized in that: The supercapacitor discharge control circuit includes a fourteenth capacitor, a fifteenth capacitor, a sixteenth capacitor, a twentieth resistor, a twenty-first resistor, a twenty-second resistor, a twenty-third resistor, a twenty-fourth resistor, a twenty-fifth resistor, a first P-channel MOSFET, a second P-channel MOSFET, a first transistor, and a second transistor. The positive terminal of the energy storage capacitor is electrically connected to the fourteenth capacitor, the fifteenth capacitor, the twentieth resistor, and the source of the first P-channel MOSFET. The other end of the fourteenth capacitor is grounded. The other end of the fifteenth capacitor is electrically connected to the twenty-second resistor. The other end of the twenty-first resistor is electrically connected to the twenty-second resistor. The drain of the first P-channel MOSFET is electrically connected to the drain of the second P-channel MOSFET. The source of the second P-channel MOSFET is connected to the second input voltage. The source of the second P-channel MOSFET is connected to the fifteenth capacitor. The other end of the fifteenth capacitor is grounded. The gates of both the first and second P-channel MOSFETs are connected to... The 22nd resistor is electrically connected, and one end of the 22nd resistor is connected to the gate of the 15th capacitor, the 20th resistor, the first P-channel MOSFET, and the second P-channel MOSFET. The other end of the 22nd resistor is connected to the collector of the first transistor. The base of the first transistor is electrically connected to the 21st resistor. The other end of the 21st resistor is electrically connected to the 23rd resistor and the collector of the second transistor. The other end of the 23rd resistor is connected to the second external power supply. The base of the second transistor is electrically connected to the 24th and 25th resistors. The other end of the 24th resistor is connected to the status signal. The other end of the 25th resistor is grounded.

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