Self-locking circuit, driving circuit and variable frequency system

Abstract

The application is suitable for the technical field of variable frequency driving, and provides a self-locking circuit, a driving circuit and a variable frequency system. The self-locking circuit comprises a first switching module, a second switching module and a third switching module. The first switching module is in an off state under the condition of receiving a fault signal and outputs a first self-locking signal. The second switching module is in a conduction state under the condition of receiving the first self-locking signal at a control end and outputs a second self-locking signal to the control end of the first switching module to maintain the off state of the first switching module. The third switching module is in a conduction state under the condition of receiving a release signal at a control end and outputs a first unlocking signal to the second switching module to make the second switching module enter an off state and stop outputting the second self-locking signal. The technical scheme has the advantages of quick response, reliable latching and controllable unlocking, and improves the safety and reliability of the driving circuit and the power device.

Description

Technical Field

[0001] This application relates to the field of frequency conversion drive technology, and in particular to a self-locking circuit, a drive circuit, and a frequency conversion system. Background Technology

[0002] In the fields of frequency converter drives, air conditioning systems, and power electronics, drive boards typically require reliable protection for power devices (such as IGBTs and MOSFETs). Existing technologies have developed several circuit solutions for signal self-locking. However, these self-locking circuits generally suffer from the following shortcomings: they are structurally complex and lack an effective release mechanism; they cannot promptly restore normal signals after a fault is cleared, easily leading to equipment downtime or requiring manual intervention. Utility Model Content

[0003] This application provides a self-locking circuit, a drive circuit, and a frequency conversion system to solve the problems of complex self-locking circuit structures and lack of effective release mechanisms in traditional frequency conversion systems, which can lead to equipment shutdown or the need for manual intervention when the fault is cleared.

[0004] Firstly, a self-locking circuit is provided, comprising:

[0005] The first switch module is configured to: be in the off state upon receiving a fault signal and output a first self-locking signal;

[0006] The second switch module has its control terminal connected to the output terminal of the first switch module, and its output terminal connected to the control terminal of the first switch module. The second switch module is configured to be in an on state when it receives the first self-locking signal at its control terminal, and to output a second self-locking signal to the control terminal of the first switch module so that the first switch module remains in an off state.

[0007] The third switch module, whose output terminal is connected to the control terminal of the second switch module, is configured to: be in the on state when its control terminal receives a release signal, and output a first unlock signal to the control terminal of the second switch module, so that the second switch module enters the off state and stops outputting the second self-locking signal.

[0008] The self-locking circuit provided in this embodiment can quickly shut down and output a self-locking signal when a fault occurs. Feedback is generated through the second switching module to maintain the lock, ensuring that the protected state remains even after the fault signal disappears. Simultaneously, the third switching module unlocks the circuit upon receiving a release signal, allowing it to safely resume operation after the fault is confirmed to have been cleared. This solution offers rapid response, reliable latching, and controllable unlocking, improving the safety and reliability of the drive circuit and power devices.

[0009] In some embodiments, the first switch module is further configured to be in an ON state when it receives a working signal at its control terminal, and to output a second unlock signal to cause the second switch module to enter an OFF state.

[0010] In this embodiment, the first switch module can switch between self-locking and unlocking according to different input signals (fault signal / working signal), avoiding reliance on the single release path of the third switch module and enhancing circuit flexibility; after the fault is cleared, as long as the working signal is restored, the first switch module can automatically output an unlocking signal to achieve self-recovery and reduce manual intervention.

[0011] In some embodiments, the first switching module includes a first resistor, a first switching transistor, and a first capacitor. One end of the first resistor receives a first voltage, and the other end of the first resistor is connected to the first end of the first switching transistor to form the output terminal of the first switching module. The second end of the first switching transistor and one end of the first capacitor are connected to ground, and the control terminal of the first switching transistor and the other end of the first capacitor are connected to each other to form the control terminal of the first switching module.

[0012] In this embodiment, by introducing a combination structure of a first resistor, a first switching transistor, and a first capacitor into the first switching module, current limiting protection of the input voltage, filtering and stabilization of the control signal, and rapid turn-on / turn-off of the switching transistor are achieved. This enables reliable output of a self-locking signal under fault conditions and rapid output of an unlocking signal when the working state is restored. This technical solution not only improves the anti-interference capability and response speed of the circuit, but also ensures the stability and safety of the self-locking and unlocking process.

[0013] In some embodiments, the output terminal of the first switch module is connected to the input terminal of the first module to be locked, and when the control terminal of the first switch module receives a fault signal, the output terminal of the first switch module outputs a first self-locking signal to the input terminal of the first module to be locked, so as to lock the input terminal of the first module to be locked as a high-level signal.

[0014] In this embodiment, by setting the first self-locking signal to a high level and directly locking the input terminal of the module to be locked, the target module can be quickly and clearly locked in a stable state when a fault occurs, avoiding interference from abnormal signals to the system. This scheme ensures the reliability and determinism of the locking process and improves the system's safety and anti-interference capability under fault conditions.

[0015] In some embodiments, the second switching module includes a second switching transistor, a second capacitor, and a second resistor. The control terminal of the second switching transistor, one end of the second capacitor, and one end of the second resistor are connected together to form the control terminal of the second switching module. The first end of the second switching transistor is the output terminal of the second switching module. The second end of the second switching transistor, the other end of the second capacitor, and the other end of the second resistor are connected to ground.

[0016] In this embodiment, the second switch turns on upon receiving a latching signal, maintaining a high-level output and effectively ensuring continuous circuit locking under fault conditions. The second capacitor filters the control terminal signal to prevent false triggering caused by spikes or glitches; the second resistor provides a pull-down guarantee to avoid uncertain states caused by floating input terminals. When unlocking, the second capacitor discharges rapidly, causing the control terminal potential to quickly return to a low level, thereby enabling the second switch to turn off quickly and ensuring the system promptly returns to normal operating conditions.

[0017] In some embodiments, the output terminal of the second switch module is connected to the input terminal of the second module to be locked, and when the control terminal of the second switch module receives the first self-locking signal, the output terminal of the second switch module outputs the second self-locking signal to the input terminal of the second module to be locked, so as to lock the input terminal of the second module to be locked to a low level signal.

[0018] In some embodiments, the third switching module includes a third switching transistor and a third resistor. The first end of the third switching transistor is the output terminal of the third switching module, the control terminal of the third switching transistor is connected to one end of the third resistor, the other end of the third resistor is the control terminal of the third switching module, and the second end of the third switching transistor is grounded.

[0019] In this embodiment, the third switch is turned on when it receives a release signal, forcibly pulling the control terminal of the second switch module 102 low, thereby realizing the rapid release of the self-locking circuit. It can quickly respond to external release signals and ensure that the system can resume normal operation in a timely manner.

[0020] In a second aspect, a driving circuit is provided, including the self-locking circuit described in the first aspect and a first inverter module. The input terminal of the first inverter module is connected to the output terminal of the second switching module. When the second switching module receives the first self-locking signal at its control terminal, it outputs a second self-locking signal to the input terminal of the first inverter module to lock the first inverter module in an off state.

[0021] Thirdly, a driving circuit is provided, including the self-locking circuit described in the first aspect, a gate driving chip, and a second inverter module. The gate driving chip is connected to the output terminal of the first switching module and the second inverter module respectively. When the control terminal of the first switching module receives a fault signal, it outputs a first self-locking signal to the input terminal of the gate driving chip.

[0022] When the gate driver chip receives the first self-locking signal, it outputs a shutdown signal to the second inverter module, causing the second inverter module to stop working.

[0023] Fourthly, a frequency conversion system is provided, including the drive circuit and controller described in the second or third aspect.

[0024] It is understood that the beneficial effects of the second to fourth aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a self-locking circuit according to one embodiment of the present invention;

[0027] Figure 2 This is a circuit diagram of a self-locking circuit according to one embodiment of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of a driving circuit in one of the two embodiments of this utility model;

[0029] Figure 4 This is a circuit diagram of a driving circuit in one of the two embodiments of this utility model;

[0030] Figure 5 This is a schematic diagram of the structure of a driving circuit in one of the three embodiments of this utility model;

[0031] Figure 6 This is a circuit diagram of one driving circuit in one of the three embodiments of this utility model;

[0032] In the diagram: 101, first switch module; 102, second switch module; 103, third switch module; 201, first inverter module; 202, gate driver chip; 203, second inverter module. Detailed Implementation

[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present utility model.

[0034] It should be understood that, when used in this specification and appended claims, unless otherwise stated, the term " / " means "or," for example, A / B can mean A or B; "and / or" in this document is merely a description of the relationship between related objects, indicating that three relationships can exist, for example, A and / or B can represent: A alone, A and B simultaneously, and B alone. Furthermore, in the description of the embodiments in this application, "multiple" refers to two or more.

[0035] In the description of this utility model specification and the appended claims, the term "comprising" indicates the presence of a described feature, integral, step, operation, element, and / or component, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. It should also be understood that the term "and / or" as used in this utility model specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0036] Furthermore, in the description of this utility model specification and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0037] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of the present invention include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0038] It should be understood that the sequence number of each step in the following embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of this utility model embodiment.

[0039] To illustrate the technical solution of this utility model, specific embodiments are described below.

[0040] To facilitate a further understanding of the technical solutions in some embodiments of this application, the technical solutions of the self-locking circuit, drive circuit, and frequency conversion system, and how these solutions solve the aforementioned technical problems, are described in detail below with reference to specific embodiments and accompanying drawings. The embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this application.

[0041] In some embodiments, such as Figure 1 As shown, a self-locking circuit is provided, comprising:

[0042] The first switch module 101 is configured to: be in the off state when a fault signal is received, and output a first self-locking signal;

[0043] The second switch module 102 has its control terminal connected to the output terminal of the first switch module 101, and its output terminal connected to the control terminal of the first switch module 101. The second switch module 102 is configured to be in the on state when it receives a first self-locking signal at its control terminal, and to output a second self-locking signal to the control terminal of the first switch module 101 so that the first switch module 101 is in the off state.

[0044] The third switch module 103, whose output terminal is connected to the control terminal of the second switch module 102, is configured to be in the on state when it receives a release signal at its control terminal, and to output a first unlock signal to the control terminal of the second switch module 102 so that the second switch module 102 enters the off state and stops outputting the second self-locking signal.

[0045] The first switch module 101 is the core self-locking trigger of the circuit. When its control terminal receives a fault signal, it immediately enters the off state, cutting off the main circuit. Simultaneously, it outputs a first self-locking signal as the starting point for subsequent latching actions; it acts as the first-level protection element for detecting and responding to faults, promptly blocking the circuit and generating the trigger signal required to maintain the off state. After being turned on, it outputs a second self-locking signal to the control terminal of the first switch module 101, forming a feedback holding loop. Once a fault is triggered, the second switch module 102 will continuously output latching signals. Even if the initial fault signal disappears, the first switch module 101 remains off, ensuring the reliability and safety of the protection. The second switch module 102 is the latch-and-hold device of the circuit; its control terminal receives the first self-locking signal from the first switch module 101 and enters the on state under the action of this signal. The third switch module 103 is the unlocking and releasing device of the circuit; when its control terminal receives a release signal, it enters the on state and outputs a first unlocking signal to the second switch module 102. The unlock signal causes the second switch module 102 to turn off, thereby stopping the feedback of the self-locking signal to the first switch module 101. When the third switch module 103 confirms that the condition is met, it releases the self-locking state, allowing the system to return to a normal operating state that can be restarted.

[0046] The first switch module 101 includes, but is not limited to, the following implementation methods:

[0047] 1. A transistor structure with one end connected to a high level, using an NMOS / PMOS or NPN / PNP transistor as a switch. A fault signal is connected to the gate / base, which turns off upon triggering; simultaneously, a first latching signal (high-level signal) is output through the circuit node.

[0048] 2. The logic gate structure is connected to a high level at one end. It uses combinational logic such as NAND gates / OR NOT gates to receive fault inputs and output low or high levels as self-locking signals.

[0049] 3. Relay structure: An electromagnetic relay is used. The coil receives the fault voltage, opens the normally closed contact, and simultaneously feeds back a signal to the second switch module 102.

[0050] The second switch module 102 includes, but is not limited to, the following implementation methods:

[0051] 1. A dual-transistor latch circuit, similar to a bistable latch, typically uses two cross-coupled NPN / PNP transistors or MOSFETs to maintain conduction. After the first latching signal is triggered, the module maintains its output and continues to exist independently of the input.

[0052] 2. MOSFET feedback hold structure: An NMOS / PMOS controlled switch, after being turned on, maintains the latched state by feeding a feedback resistor / line to the control terminal of the first module.

[0053] 3. RS latch: The RS latch is constructed using logic gates (consisting of two NOR or NAND signals). The first self-locking signal is used as the Set terminal to maintain the lock.

[0054] The third switch module 103 includes, but is not limited to, the following implementation methods:

[0055] 1. A transistor switch structure using NMOS, PMOS, or NPN / PNP transistors as controlled switches. When a release signal is applied to the gate / base, the transistor turns on, outputting an unlock signal to the second switching module.

[0056] 2. Logic gate control structure, implemented by logic circuits such as AND gates, OR gates, and NOT gates.

[0057] 3. The relay control structure receives the release signal through the relay coil, triggers the normally open contact to close, and outputs an unlock signal.

[0058] 4. Optocoupler switch structure: It uses an optocoupler device to release a signal to drive the LED to light up, and the phototransistor or photosensitive MOS to conduct, thereby outputting an unlock signal.

[0059] The self-locking circuit provided in this embodiment of the invention, through the cooperation of the first switch module 101, the second switch module 102, and the third switch module 103, can achieve rapid fault detection, latching, and controllable release, and has the following technical effects: The first switch module 101, as the core trigger, immediately shuts off the main circuit upon receiving a fault signal and simultaneously outputs a first self-locking signal, ensuring that the circuit is blocked the instant a fault occurs, effectively preventing further fault propagation and improving the real-time performance of the circuit protection. The second switch module 102 enters the conducting state after receiving the first self-locking signal and continuously outputs a second self-locking signal to the control terminal of the first switch module 101 through feedback, keeping the first switch module 101 in the off state. Even if the fault signal disappears, the circuit can still maintain the protection mode, avoiding false resets caused by transient interference or jitter, and ensuring the stability and reliability of the protection process. The third switch module 103 turns on after receiving the release signal and outputs a first unlocking signal to the second switch module 102, causing the second switch module 102 to turn off, thereby stopping the feedback. At this point, the first switch module 101 can return to its initial state, enabling the circuit to resume operation. Conditional unlocking via an external release signal prevents automatic circuit recovery before fault resolution, improving system safety and controllability. The first switch module 101, second switch module 102, and third switch module 103 can all be implemented using transistors, MOSFETs, logic gates, or relays, offering flexible circuit configurations suitable for both low-power electronic devices and high-power drive applications, exhibiting excellent scalability and adaptability. Through this self-locking-unlocking mechanism, even without hardware protection in the gate driver chip, equivalent fault locking and protection are provided, preventing damage to the driver board and power devices due to faults and significantly improving the overall reliability and safety of the system.

[0060] In one implementation, the first switch module 101 is further configured to be in an ON state when it receives a working signal at its control terminal, and to output a second unlock signal to cause the second switch module 102 to enter an OFF state.

[0061] In this embodiment, the first switch module 101 not only enters a shutdown state and outputs a first self-locking signal when its control terminal receives a fault signal, but is also further configured to: enter a conduction state when its control terminal receives a working signal; in the conduction state, the first switch module 101 outputs a second unlocking signal; the second unlocking signal acts on the second switch module 102, causing it to switch to a shutdown state, thereby stopping the output of the second self-locking signal maintaining shutdown to the first switch module 101; finally, the self-locking logic loop is released, and the circuit returns to normal operation. The first switch module 101 is responsible for generating the self-locking signal after a fault is triggered, and can actively output an unlocking signal when it receives a normal operation signal, realizing bidirectional control of self-locking and unlocking.

[0062] The technical advantages of this embodiment are as follows: the first switch module 101 can switch between self-locking and unlocking according to different input signals (fault signal / working signal), avoiding reliance on the single release path of the third switch module 103 and enhancing circuit flexibility; after the fault is cleared, as long as the working signal is restored, the first switch module 101 can automatically output an unlocking signal to achieve self-recovery and reduce manual intervention.

[0063] As one implementation method, such as Figure 2 As shown, the first switching module 101 includes a first resistor R1, a first switching transistor Q1, and a first capacitor C1. One end of the first resistor R1 receives a first voltage, and the other end of the first resistor R1 is connected to the first end of the first switching transistor Q1, forming the output terminal of the first switching module 101. The second end of the first switching transistor Q1 and one end of the first capacitor C1 are connected to ground. The control terminal of the first switching transistor Q1 and the other end of the first capacitor C1 are connected to each other, forming the control terminal of the first switching module 101.

[0064] In this embodiment, one end of the first resistor R1 receives a first voltage (e.g., the operating power supply voltage Vcc); the other end is connected to the first terminal of the first switch Q1 and serves as the output terminal of the first switching module 101. It is used to limit and divide the input voltage to prevent current surges and provide a stable voltage input for subsequent stages. The first switch Q1 (which can be a MOSFET or a bipolar transistor) acts as the dominant on / off device, determining whether the output terminal remains high or is pulled low based on the voltage signal from the control terminal. The first capacitor C1 filters the control terminal signal to prevent transient pulses or glitches from causing malfunctions in the switch. The working principle of this embodiment is as follows: when the control terminal receives a fault signal, it turns off the first switch Q1, and the first voltage outputs current through the first resistor R1, thereby outputting a first latching signal (high-level signal). When the control terminal receives a working signal, the first capacitor C1 charges rapidly, causing the first switch Q1 to quickly turn on, thereby outputting a second unlocking signal (low-level signal).

[0065] The technical advantages of this embodiment are as follows: by introducing a combination structure of a first resistor, a first switching transistor, and a first capacitor into the first switching module 101, current limiting protection of the input voltage, filtering and stabilization of the control signal, and rapid on / off of the switching transistor are achieved, thereby enabling reliable output of a self-locking signal in fault conditions and rapid output of an unlocking signal when the working state is restored. This technical solution not only improves the anti-interference capability and response speed of the circuit, but also ensures the stability and safety of the self-locking and unlocking process.

[0066] In one implementation, the output terminal of the first switch module 101 is connected to the input terminal of the first module to be locked. When the control terminal of the first switch module 101 receives a fault signal, the output terminal of the first switch module 101 outputs a first self-locking signal to the input terminal of the first module to be locked, so as to lock the input terminal of the first module to be locked to a high-level signal.

[0067] When the control terminal of the first switch module 101 receives a fault signal, the first switch module 101 enters a shutdown state and outputs a high-level first self-locking signal at its output terminal, thereby forcing the input terminal of the first module to be locked to remain at a high level. This high-level locking state can effectively prevent the first module to be locked from continuing to respond to other input signals, ensuring that it maintains the locked state in the event of a fault.

[0068] In this embodiment, the first module to be locked can be specifically configured according to different application scenarios:

[0069] 1. Controller module, such as MCU, logic control circuit, etc. When the first switch module 101 outputs a high-level first self-locking signal, it directly locks the enable input terminal of the controller to a high level, thereby prohibiting it from continuing to output control commands.

[0070] 2. Power switching module, such as MOSFET driver circuit or IGBT module. When the first switching module 101 outputs a high-level self-locking signal, it forces the drive input terminal of the power switch to remain in a high-level state, keeping the power switch off and preventing the power device from continuing to conduct in case of a fault.

[0071] 3. Execution unit modules, such as motor drivers, heater drivers, relays, etc. When a high-level self-locking signal is received, its input terminal is locked at a high level, thereby preventing the execution unit from continuing to operate and ensuring that the controlled object is in a stopped or protected state.

[0072] In this embodiment, by setting the first self-locking signal to a high level and directly locking the input terminal of the module to be locked, the target module can be quickly and clearly locked into a stable state when a fault occurs, avoiding interference from abnormal signals to the system. This scheme ensures the reliability and determinism of the locking process and improves the system's safety and anti-interference capability under fault conditions.

[0073] like Figure 2 As shown, the second switch module 102 includes a second switch transistor Q2, a second capacitor C2, and a second resistor R2. The control terminal of the second switch transistor Q2, one end of the second capacitor C2, and one end of the second resistor R2 are connected together to form the control terminal of the second switch module 102. The first end of the second switch transistor Q2 is the output terminal of the second switch module 102. The second end of the second switch transistor Q2, the other end of the second capacitor C2, and the other end of the second resistor R2 are connected to ground.

[0074] In this embodiment, the second switch Q2 serves as the core conducting device. It turns on when the control terminal receives a high-level first self-locking signal, thus maintaining the second self-locking signal at the output terminal and achieving latching. When the control terminal returns to a low level, it turns off, stopping feedback. The second capacitor C2 filters and buffers the control terminal signal, preventing malfunctions of the second switch Q2 due to glitches, electromagnetic interference, or transient spikes. The second resistor R2 acts as a pull-down resistor, ensuring that the control terminal is pulled low when there is no input signal, preventing false turn-on due to a floating state. Simultaneously, it provides a fast discharge path for the control terminal when the self-lock is released, accelerating the turn-off speed of the second switch Q2. The working principle of this embodiment is as follows: When the first self-locking signal output by the first switch module 101 is high, it is applied to the control terminal of the second switch module 102, driving the second switch Q2 to conduct. Its output terminal then outputs the second self-locking signal and feeds it back to the first switch module 101, thus maintaining the self-locking state. During this process, the second capacitor C2 suppresses interference, and the second resistor R2 stabilizes the level. When the release signal or working signal arrives and the control terminal returns to a low level, the second switch Q2 is turned off, the output terminal stops feedback, and the self-locking state is released.

[0075] The technical advantages of this implementation are as follows: the second switch turns on upon receiving a latching signal, maintaining a high-level output and effectively ensuring continuous circuit locking under fault conditions. The second capacitor filters the control terminal signal, preventing false triggering caused by spikes or glitches; the second resistor provides a pull-down guarantee, avoiding uncertain states caused by floating input terminals. When unlocking, the second capacitor discharges rapidly, causing the control terminal potential to quickly return to a low level, thereby enabling the second switch to turn off quickly and ensuring the system promptly returns to normal operating conditions.

[0076] In one implementation, the output terminal of the second switch module 102 is connected to the input terminal of the second module to be locked. When the control terminal of the second switch module 102 receives the first self-locking signal, the output terminal of the second switch module 102 outputs the second self-locking signal to the input terminal of the second module to be locked, so as to lock the input terminal of the second module to be locked to a low-level signal.

[0077] Specifically, when the control terminal of the second switch module 102 receives a first self-locking signal (high level) from the first switch module 101, the second switch transistor Q2 is turned on, and its output terminal is pulled low, thereby outputting a second self-locking signal. At this time, the input terminal of the second module to be locked is forcibly locked to a low level state. In this state, the second module to be locked no longer responds to other input signals, but is kept in a stopped or prohibited state until the unlocking signal arrives.

[0078] In this embodiment, the second module to be locked can be specifically classified into the following categories according to application requirements:

[0079] 1. Power drive module, such as MOSFET driver or IGBT driver. When the second switching module 102 outputs a low-level second latching signal, the driver input is forced to remain at a low level, the drive signal is disabled, and the power device is turned off.

[0080] 2. Motor controller, such as a DC motor drive chip or inverter controller. When the input is locked low, the motor controller's start signal is suppressed, and the motor remains stopped, thus preventing the motor from continuing to operate in the event of a fault.

[0081] 3. Load actuators, such as relay control modules, heater drive modules, valve control units, etc. When the input is locked to a low level, the actuator's action signal is shielded, ensuring it is in a closed or disabled state to prevent dangerous operation.

[0082] The technical advantage of this embodiment is that by setting the second self-locking signal to a low level and directly applying it to the input terminal of the second module to be locked, it can be quickly and clearly kept in a prohibited state, preventing it from continuing to work. When a fault occurs, the second module to be locked is forcibly locked to a low level, ensuring that it will not be mistakenly activated when there is interference or abnormal control commands, thereby improving the safety and robustness of the entire system in fault conditions.

[0083] As one implementation method, such as Figure 2As shown, the third switch module 103 includes a third switch transistor Q3 and a third resistor R3. The first end of the third switch transistor Q3 is the output terminal of the third switch module 103. The control terminal of the third switch transistor Q3 is connected to one end of the third resistor R3. The other end of the third resistor R3 is the control terminal of the third switch module 103. The second end of the third switch transistor Q3 is grounded.

[0084] In this embodiment, the third switch Q3 turns on when the control terminal receives a release signal, thereby pulling its output terminal low and outputting a first unlock signal, which turns off the second switch module 102. The third resistor R3 is used to receive external release signals; when there is no release signal, it provides a pull-down or voltage regulation function to ensure that the control terminal is at a stable low level and to prevent the third switch Q3 from being mis-turned on; when the release signal arrives, it ensures stable and reliable signal transmission. The working principle of this embodiment is as follows: when the control terminal of the third switch module 103 receives a release signal, the third resistor R3 is applied to the control terminal of the third switch, turning it on. At this time, the output terminal of the third switch Q3 is pulled low, providing a first unlock signal to the second switch module 102, turning off the second switch Q2, stopping the output of the second self-locking signal, thereby releasing the self-locking state.

[0085] The technical effect of this embodiment is that when the third switch receives the release signal, it turns on and forcibly pulls the control terminal of the second switch module 102 low, thereby realizing the rapid release of the self-locking circuit, enabling a rapid response to external release signals, and ensuring that the system can resume normal operation in a timely manner.

[0086] The working process of this circuit structure is as follows:

[0087] Normal state: When the driver board is running normally, the output Fo signal is high, the base of the first switching transistor Q1 is driven by a high level, the first switching transistor Q1 is turned on, its collector is pulled low, causing the base of the second switching transistor Q2 to be in a low level state, and the second switching transistor Q2 is turned off. At this time, the circuit is in normal working state and has not entered latching.

[0088] Latching State: When the driver board malfunctions, the Fo signal is low, the base of the first switch Q1 is low, and Q1 is cut off. Its collector is pulled high, which in turn pulls the base of the third switch Q3 high, turning Q3 on. After Q3 turns on, it continuously pulls the base of the first switch Q1 low, keeping Q1 off, while its collector remains high, thus achieving the latching state. Even if the Fo signal returns to high, the first switch Q1 cannot automatically turn on again.

[0089] The third switch module 103 consists of a third switch transistor Q3 and a third resistor R3, and its operation is as follows:

[0090] Under normal conditions: When the latching circuit is in normal working condition, the MCU outputs a low level through the RESET terminal, the third switch Q3 is at a low level, the third switch Q3 is cut off, and it has no effect on the second switch Q2.

[0091] Release State: When the latching circuit is in latching state and the fault has been confirmed to be eliminated, the MCU outputs a high level through the RESET terminal, and the base of the third switch Q3 receives a high level, turning on Q3. After the third switch Q3 turns on, it pulls the base of the second switch Q2 low, turning off Q2 and thus releasing the latch of the second switch Q2 on the base of the first switch Q1. At this time, the base of the first switch Q1 can be driven again by the Fo signal. If the Fo signal returns to a high level, the first switch Q1 turns on again, the collector of the first switch Q1 returns to a low level, the circuit exits the latching state, and returns to normal operation.

[0092] Example 2

[0093] It's important to understand that currently, Intelligent Power Modules (IPMs) are widely used in the power drive units of frequency converters. IPM modules not only integrate power devices but also have built-in gate drive circuits and various hardware protection functions, such as overcurrent protection, undervoltage protection, and overtemperature protection, resulting in high overall reliability and wide application. However, some frequency converters also use Integrated Bridge Modules (CIBs). Unlike IPMs, CIBs typically only integrate power devices and do not have gate drive circuits or hardware protection functions. To ensure system safety, a common practice is to use a gate drive chip with hardware protection. This type of chip can trigger protection in time when an anomaly (such as a short circuit or overcurrent) is detected, preventing damage to the drive board and power devices. Its protection principle is similar to the internal protection mechanism of IPMs. However, in some designs, although CIB modules are used, the selected gate drive chip does not have hardware protection functions and can only perform basic drive functions. In this case, if the drive board fails, the power devices and drive circuits are easily damaged. Therefore, an independent hardware protection circuit is needed to achieve rapid detection and protection, thereby compensating for the functional deficiencies of the gate driver chip itself and improving the overall reliability and security of the system. The circuit proposed in this invention is designed precisely to address this problem.

[0094] Embodiment 2 of this application also provides a driving circuit, such as Figure 3As shown, the circuit includes the self-locking circuit of Embodiment 1 and the first inverter module 201. The first inverter module 201 is connected to the output terminal of the second switch module 102. When the control terminal of the second switch module 102 receives the first self-locking signal, the second switch module 102 is in the on state and outputs the second self-locking signal to the first inverter module 201 so that the first inverter module 201 is in the off state.

[0095] In this embodiment, the drive circuit includes the self-locking circuit of Embodiment 1 and a first inverter module 201. The self-locking circuit includes a first switch module 101, a second switch module 102, and a third switch module 103. When the first switch module 101 detects a fault signal, it outputs a first self-locking signal. After receiving the first self-locking signal at the control terminal, the second switch module 102 turns on and outputs a second self-locking signal to the input terminal of the first inverter module 201. The output terminal of the first inverter module 201 is connected to the output terminal of the second switch module 102. When the second self-locking signal is received from the second switch module 102, its control logic is forcibly locked, causing the first inverter module 201 to enter a shutdown state. During the latch maintenance period, the first inverter module 201 cannot be restarted, preventing the continued output of drive signals under fault conditions. Once the MCU or other control logic confirms that the fault has been cleared, it outputs an unlock signal through the working signal of the third switch module 103 or the first switch module 101. The second switch module 102 then turns off and stops outputting the second self-locking signal to the first inverter module 201. At this time, the input terminal of the first inverter module 201 resumes normal control logic, and the first inverter module 201 regains its operational capability.

[0096] The technical advantages of this embodiment are as follows: When the system detects a fault, the self-locking circuit immediately latches the fault and outputs a second self-locking signal through the second switch module 102, forcing the first inverter module 201 to shut down and cutting off the drive signal to ensure the safety of the motor or load. Even if the fault signal disappears momentarily, the second switch module 102 continues to output the second self-locking signal, keeping the first inverter module 201 continuously off, avoiding frequent start-stop of the first inverter module 201 due to interference or jitter. After the fault is cleared, the third switch module 103 will only output an unlocking signal to release the self-locking and allow the first inverter module 201 to resume operation, ensuring the safe and controllable recovery process of the system.

[0097] As an example, such as Figure 4 As shown, Figure 4PWM_UP, PWM_VP, PWM_WP, PWM_UN, PWM_VN, and PWM_WN are the PWM drive signals output by the MCU. IGBT1, IGBT2, IGBT3, IGBT4, IGBT5, and IGBT6 are connected to the input pins of the gate driver chip. When the driver board is operating normally, the Fo signal is high, and the base of the first switching transistor Q1 is high, which does not affect the PWM signal input to the gate driver chip. When the driver board malfunctions, the Fo signal is low. The latching circuit continuously locks the base of the first switching transistor Q1 to a low level, forcibly pulling the PWM signal low, making all signals input to the gate driver chip low, and turning off the subsequent IGBT modules to protect them.

[0098] Example 3

[0099] This embodiment three provides a driving circuit, such as Figure 5 As shown, the system includes a self-locking circuit, a gate driver chip 202, and a second inverter module 203 as provided in Embodiment 1. The gate driver chip 202 is connected to the output terminal of the first switch module 101 and the second inverter module 203, respectively. When the control terminal of the first switch module 101 receives a fault signal, it outputs a first self-locking signal to the input terminal of the gate driver chip 202. When the gate driver chip 202 receives the first self-locking signal, it outputs a turn-off signal to the second inverter module 203, causing the second inverter module 203 to stop working.

[0100] In this embodiment, the self-locking circuit detects a fault signal and outputs a first self-locking signal. When the first switching module 101 receives a fault signal, it enters a shutdown state and generates a high-level first self-locking signal at its output. One end of the gate driver chip 202 is connected to the output of the first switching module 101 to receive the first self-locking signal; the other end is connected to the second inverter module 203 to transmit control signals to the power switching devices (such as IGBTs, MOSFETs, etc.) of the second inverter module 203. When the first self-locking signal is received, the gate driver chip 202 recognizes it as a shutdown command and outputs a shutdown signal to the power switching transistors of the second inverter module 203, causing them to turn off. The second inverter module 203 includes multiple power switching transistors to invert DC voltage into AC voltage to drive a load (such as a motor). When the gate driver chip 202 outputs the shutdown signal, all power switches of the second inverter module 203 are turned off, and the inverter output stops, thereby ensuring that the system will not continue to output power under fault conditions. The working process of this embodiment is as follows: Under normal circumstances, the first switch module 101 outputs a low level, and the gate driver chip 202 provides a drive signal to the second inverter module 203 according to the normal control logic, and the second inverter module 203 operates normally; when a fault occurs, the first switch module 101 outputs a high-level first self-locking signal, and the gate driver chip 202 immediately recognizes it as a shutdown command and outputs a shutdown signal to the second inverter module 203, causing the power devices of the second inverter module 203 to shut down, and the second inverter module 203 stops working and enters a protection state; after the fault is cleared, the gate driver chip 202 will only resume outputting a normal drive signal when the self-locking circuit is unlocked, and the second inverter module 203 will start working again.

[0101] The technical advantages of this embodiment are as follows: After the self-locking circuit outputs the first self-locking signal, the gate driver chip 202 can immediately apply a shutdown command to the second inverter module 203, achieving rapid shutdown at the millisecond or even microsecond level. The synergistic effect of the self-locking circuit and the gate driver chip 202 ensures that the second inverter module 203 will not continue to conduct under fault conditions, avoiding damage to power devices or loads. The self-locking circuit can latch the fault state, so even if the fault signal recovers instantaneously, the second inverter module 203 will not restart prematurely, ensuring the stability and reliability of the protection measures. After the fault is cleared, the self-locking is released by releasing the signal, the gate driver chip 202 resumes normal drive output, and the second inverter module 203 restarts, ensuring the controllable recovery of the system.

[0102] As an example, such as Figure 6As shown in the diagram, chip U1 is a gate driver chip with built-in protection. Pin 5 of chip U1 is the enable pin. When this pin is low, chip U1 can convert the input signal into an output signal and output it; when this pin is high, chip U1 outputs a low level. When the driver board is operating normally, the Fo signal is high, and pin 5 DIS of chip U1 is low, allowing chip U1 to convert the input signal into an output signal and output it. When the driver board malfunctions, the Fo signal is low, and the latching circuit will continuously lock pin 5 DIS of chip U1 to a high level, causing chip U1 to output a low level. This completely shuts down the second inverter module 203, preventing shoot-through and protecting the second inverter module 203.

[0103] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A self-locking circuit, characterized in that, include: The first switch module is configured to: be in the off state upon receiving a fault signal and output a first self-locking signal; The second switch module has its control terminal connected to the output terminal of the first switch module, and its output terminal connected to the control terminal of the first switch module. The second switch module is configured to be in an on state when it receives the first self-locking signal at its control terminal, and to output a second self-locking signal to the control terminal of the first switch module so that the first switch module remains in an off state. The third switch module, whose output terminal is connected to the control terminal of the second switch module, is configured to: be in the on state when its control terminal receives a release signal, and output a first unlock signal to the control terminal of the second switch module, so that the second switch module enters the off state and stops outputting the second self-locking signal.

2. The self-locking circuit according to claim 1, characterized in that, The first switch module is further configured to be in an ON state when it receives a working signal at its control terminal, and to output a second unlock signal to cause the second switch module to enter an OFF state.

3. The self-locking circuit according to claim 2, characterized in that, The first switching module includes a first resistor, a first switching transistor, and a first capacitor. One end of the first resistor receives a first voltage, and the other end of the first resistor is connected to the first end of the first switching transistor to form the output terminal of the first switching module. The second end of the first switching transistor and one end of the first capacitor are connected to ground. The control terminal of the first switching transistor and the other end of the first capacitor are connected to each other to form the control terminal of the first switching module.

4. The self-locking circuit according to claim 3, characterized in that, The output terminal of the first switch module is connected to the input terminal of the first module to be locked. When the control terminal of the first switch module receives a fault signal, the output terminal of the first switch module outputs a first self-locking signal to the input terminal of the first module to be locked, so as to lock the input terminal of the first module to be locked to a high-level signal.

5. The self-locking circuit according to claim 1 or 2, characterized in that, The second switching module includes a second switching transistor, a second capacitor, and a second resistor. The control terminal of the second switching transistor, one end of the second capacitor, and one end of the second resistor are connected together to form the control terminal of the second switching module. The first end of the second switching transistor is the output terminal of the second switching module. The second end of the second switching transistor, the other end of the second capacitor, and the other end of the second resistor are connected to ground.

6. The self-locking circuit according to claim 5, characterized in that, The output terminal of the second switch module is connected to the input terminal of the second module to be locked. When the control terminal of the second switch module receives the first self-locking signal, the output terminal of the second switch module outputs the second self-locking signal to the input terminal of the second module to be locked, so as to lock the input terminal of the second module to be locked to a low level signal.

7. The self-locking circuit according to claim 1 or 2, characterized in that, The third switch module includes a third switch transistor and a third resistor. The first end of the third switch transistor is the output terminal of the third switch module. The control terminal of the third switch transistor is connected to one end of the third resistor. The other end of the third resistor is the control terminal of the third switch module. The second end of the third switch transistor is grounded.

8. A driving circuit, characterized in that, The circuit includes the self-locking circuit and the first inverter module as described in any one of claims 1 to 7, wherein the input terminal of the first inverter module is connected to the output terminal of the second switch module, and the second switch module, upon receiving the first self-locking signal at its control terminal, outputs a second self-locking signal to the input terminal of the first inverter module to lock the first inverter module in an off state.

9. A driving circuit, characterized in that, The device includes a self-locking circuit as described in any one of claims 1 to 7, a gate driving chip, and a second inverter module. The gate driving chip is connected to the output terminal of the first switching module and the second inverter module, respectively. When the control terminal of the first switching module receives a fault signal, it outputs a first self-locking signal to the input terminal of the gate driving chip. When the gate driver chip receives the first self-locking signal, it outputs a shutdown signal to the second inverter module, causing the second inverter module to stop working.

10. A frequency conversion system, characterized in that, Includes the drive circuit and controller as described in claim 8 or 9.

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