A test signal generation apparatus

Abstract

The utility model provides a kind of test signal generation device, including dial switch group, trigger button, programmable logic array and photocoupler relay, dial switch group output pulse number setting value and pulse interval setting value, trigger button is used to output single trigger pulse;Programmable logic array and dial switch group, trigger button are connected;Programmable logic array receives trigger pulse after, interval register, quantity register in it respectively latch pulse interval setting value, pulse number setting value, interval counter exports multiple interval pulse signals, quantity counter sends stop signal to interval counter when pulse signal quantity is equal to pulse number setting value, to make interval counter stop output pulse signal;Photocoupler relay is connected between interval counter and equipment to be tested.Such, can obtain a convenient to use, the test signal generation device capable of generating accurate pulse signal sequence.

Description

Technical Field

[0001] This application relates to the field of test equipment for event sequence recording systems, and more particularly to a test signal generation device. Background Technology

[0002] With the increasing scale and complexity of thermal power units, the requirements for safe operation in thermal power plants are also becoming more stringent. When a unit malfunctions, maintenance personnel need to quickly identify the cause of the accident and take appropriate measures, which requires the recording and logging of events. SOE (Sequence of Events) is a system that accurately records and reports changes in the states of predefined important switching signals. It can acquire and record changes in the states of field equipment switching signals with millisecond-level resolution, recording relevant information at the time of an accident, thereby helping maintenance personnel quickly analyze faults and identify their causes. Therefore, in existing technologies, SOE is often used as a subsystem of the distributed control system (DCS) in thermal power plants, so that when a thermal power unit malfunctions, SOE can be used to assist staff in quickly and accurately identifying the cause of the accident and taking appropriate measures.

[0003] According to DL / T659-2016 "Acceptance Test Procedure for Distributed Control Systems in Thermal Power Plants", the resolution of the SOE (System-on-Edge) of a distributed control system in a thermal power plant should not exceed 1 ms. However, as the system ages, some functions of the SOE may degrade or be lost, and the resolution may not meet the requirements of the procedure. Therefore, periodically testing the SOE of the distributed control system is an important means of verifying whether the SOE resolution meets the requirements of the procedure.

[0004] Therefore, a test signal generator is typically used to emit test signals at known time intervals. The SOE resolution is verified by judging the accuracy of the SOE system's recording of the test signals. The basic principle is: the switch signals emitted by the test signal generator simulate the SOE signals emitted by the device that can trigger the SOE system. Multiple switch signals emitted by the test signal generator precisely trigger each event channel according to a specific triggering sequence and time interval. Then, the accuracy of the SOE recording function is verified by comparing the triggering sequence of the multiple switch signals from the test signal generator with the real-time recording of the SOE.

[0005] Existing test signal generators suffer from drawbacks such as limited variety, high cost, inconvenience in portability, and low accuracy of test signal time intervals. Therefore, this application provides a novel test signal generator with high accuracy of test signal time intervals and low cost to meet diverse user needs. Utility Model Content

[0006] To address the aforementioned technical problems, this application provides a test signal generation device that can solve at least one of the aforementioned problems.

[0007] This application provides a test signal generation device, the test signal generation device comprising:

[0008] A DIP switch group, wherein the DIP switch group is used to output pulse quantity setting value and pulse interval setting value according to user setting value;

[0009] A trigger button, which is used to output a single trigger pulse when operated;

[0010] The programmable logic array includes an interval register, an interval counter, a count register, and a count counter, wherein...

[0011] The interval register is connected to the DIP switch group and the trigger button to receive the pulse interval setting value and the trigger pulse. After receiving the trigger pulse, the interval register latches the pulse interval setting value.

[0012] The interval counter is connected to the trigger button and the interval register to receive the trigger pulse and the pulse interval setting value. After receiving the trigger pulse, the interval counter outputs multiple interval pulse signals according to the pulse interval setting value.

[0013] The quantity register is connected to the DIP switch group and the trigger button to receive the pulse quantity setting value and the trigger pulse. After receiving the trigger pulse, the quantity register latches the pulse quantity setting value.

[0014] The quantity counter is connected to the trigger button and the quantity register to receive the trigger pulse and the pulse quantity setting value. The quantity counter is also connected to the interval counter to count the pulse signal after receiving the trigger pulse, and send a stop signal to the interval counter when the pulse quantity setting value is reached. The interval counter stops outputting the pulse signal according to the stop signal.

[0015] An optocoupler relay is provided, wherein the input terminal of the optocoupler relay is electrically connected to the interval counter to receive the pulse signal, and the output terminal of the optocoupler relay is used to connect to the device under test to send the pulse signal to the device under test.

[0016] In one alternative embodiment, the number of both the interval counter and the optocoupler relay is one; or,

[0017] The interval counter is one in number, the optocoupler relays are multiple in number, and the programmable logic array further includes a pulse wheel switch circuit and multiple single-channel output ports. The number of single-channel output ports, the number of optocoupler relays, and the pulse quantity setting value are the same. One of the multiple optocoupler relays is connected to one of the multiple single-channel output ports. The input terminal of the pulse wheel switch circuit is connected to the pulse output terminal of the interval counter, and the input terminal of the pulse wheel switch circuit is connected to the multiple single-channel output ports. The pulse wheel switch circuit is used to sequentially distribute the multiple pulse signals output by the interval counter to the multiple single-channel output ports, so that each single-channel output port outputs one pulse signal.

[0018] In one optional embodiment, the interval register has a first parallel output terminal, and the interval counter has a second preset input terminal, a second count enable terminal, and a pulse output terminal. The second preset input terminal is connected to the first parallel output terminal of the interval register to load the latched pulse interval setting value. The second count enable terminal is connected to the trigger button to start counting after receiving the trigger pulse. The interval counter counts according to the pulse interval setting value. When the count reaches zero, a pulse signal is output through the pulse output terminal, and the pulse interval setting value is immediately and automatically reloaded to start the next counting cycle.

[0019] In one optional embodiment, the quantity counter includes a stop output terminal, through which the quantity counter outputs the stop signal; the interval counter further includes a stop input terminal, which is connected to the stop output terminal to receive the stop signal, and the interval counter stops outputting the pulse signal according to the stop signal.

[0020] In one optional embodiment, the quantity counter has a fourth preset input terminal, a counting clock terminal, and a fourth counting enable terminal, wherein the fourth preset input terminal is connected to the quantity output terminal of the quantity register to load the pulse quantity setting value;

[0021] The fourth counting enable terminal is connected to the trigger button to enable the quantity counter to start counting when the trigger pulse is received; the counting clock terminal is connected to the pulse output terminal of the interval counter to count once when each pulse signal is received; when the count value is equal to the pulse quantity setting value, the quantity counter outputs the stop signal at the stop output terminal.

[0022] In one optional embodiment, the DIP switch group is further configured to output a pulse width setting value according to a user setting; the programmable logic array further includes a width register and a monostable multivibrator, wherein the width register is connected to the DIP switch group and the trigger button, and is configured to latch the pulse width setting value after receiving the trigger pulse; the monostable multivibrator has a fifth preset input terminal, a trigger input terminal, and a fixed-width output terminal, the fifth preset input terminal of the monostable multivibrator is connected to the width register, and is configured to load the pulse width setting value; the trigger input terminal of the monostable multivibrator is connected to the interval counter to receive the pulse signal; the monostable multivibrator expands the pulse signal into a fixed-width pulse equal to the pulse width setting value, and outputs the fixed-width pulse through the fixed-width output terminal; the input terminal of the optocoupler relay is connected to the fixed-width output terminal to receive the fixed-width pulse.

[0023] In one alternative embodiment, the programmable logic array further includes a clock source for generating a fixed-frequency clock signal; the interval register and the quantity register are both connected to the clock source to obtain a synchronous clock; and the interval counter is connected to the clock source for decrementing or incrementing the count.

[0024] In one optional embodiment, the test signal generating device further includes a Global Navigation Satellite System (GNSS) receiving module. The output of the GNSS receiving module is connected to the calibration input of the clock source, and is used to output the received satellite timing signal to the clock source to perform frequency calibration on the fixed frequency clock signal.

[0025] In one optional embodiment, the test signal generation device includes a main power supply and a backup power supply, and the clock source includes a main power supply pin and a backup power supply pin, wherein the main power supply pin is connected to the main power supply and the backup power supply pin is connected to the backup power supply.

[0026] In an optional embodiment, the test signal generating device according to claim 1, wherein the test signal generating device further comprises a plurality of current-limiting resistors, and one of the current-limiting resistors is connected in series between the interval counter and the input terminal of the optocoupler relay.

[0027] When using the technical solution provided in this application, the programmable logic array can precisely control the interval between multiple output pulse signals according to the received pulse interval setting value, effectively controlling the time error of the pulse signals and improving the time accuracy of each pulse signal. Simultaneously, the number of pulse signals can be precisely controlled according to the pulse quantity setting value, thus facilitating the provision of accurate test signal sequences to the device under test (DUT), enabling the DUT to complete accurate event sequence recording tests. Furthermore, the optocoupler relay not only achieves electrical isolation, effectively avoiding electrical interference between the test signal generation device and the DUT, improving system stability and safety, but also enhances the pulse signal by increasing current or voltage, ensuring the DUT can accurately acquire the pulse signal, thereby improving test accuracy and reliability. In addition, the design of the DIP switch group allows users to easily set the required pulse quantity and pulse interval to meet the needs of different test scenarios without complex programming or configuration processes, improving the ease of use of the device. The trigger button provides users with an intuitive operation method; a simple press triggers the output of the pulse signal, further simplifying the operation process. Thus, this application provides a user-friendly test signal generation device capable of generating accurate pulse signals. Attached Figure Description

[0028] Figure 1 This is a structural block diagram of a test signal generation device provided in an embodiment of this application;

[0029] Figure 2 This is a structural block diagram of a test signal generation device provided in an embodiment of this application;

[0030] Figure 3 This is a structural block diagram of a test signal generation device provided in an embodiment of this application;

[0031] Figure 4 This is a structural block diagram of a test signal generation device provided in an embodiment of this application;

[0032] Figure 5 This is a structural block diagram of a test signal generation device provided in an embodiment of this application.

[0033] List of reference numerals in the attached diagram:

[0034] 100 - Programmable logic array, 111 - Interval register, 112 - Interval counter, 121 - Quantity register, 122 - Quantity counter, 131 - Width register, 132 - Monostable multivibrator, 140 - Pulse wheel switch circuit, 150 - Single-channel output port, 160 - Clock source;

[0035] 200 - Optocoupler relay; 301 - DIP switch group; 302 - Trigger button;

[0036] 400 - Global Navigation Satellite System Receiver Module. Detailed Implementation

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0038] In the description of this application, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0039] This application provides a test signal generation device that can be used to test an event sequence recording system. Specifically, the test signal generation device can emit some pulse signals that can be used as test signals. The event sequence recording system receives and records these test signals. By judging the accuracy of the event sequence recording system in recording these test signals, the performance of the event sequence recording system can be judged, thereby completing the test of the event sequence recording system.

[0040] refer to Figure 1The test signal generation device provided in this application includes a DIP switch group 301, a trigger button 302, a programmable logic array 100, and an optocoupler relay 200. The DIP switch group 301 is used to output a pulse quantity setting value and a pulse interval setting value according to the user setting. The trigger button 302 is used to output a single trigger pulse when operated. The programmable logic array 100 includes an interval register 111, an interval counter 112, a quantity register 121, and a quantity counter 122. The interval register 111 is connected to both the DIP switch group 301 and the trigger button 302 to receive the pulse interval setting value and the trigger pulse. The interval register 111 latches the pulse interval setting value after receiving the trigger pulse. The interval counter 112 is connected to both the trigger button 302 and the interval register 111 to receive the pulse interval setting value and the trigger pulse. The interval counter 112 latches the pulse interval setting value after receiving the trigger pulse. The pulse signal is output at multiple intervals according to the pulse interval setting value. The quantity register 121 is connected to the DIP switch group 301 and the trigger button 302 to receive the pulse quantity setting value and the trigger pulse. The quantity register 121 latches the pulse quantity setting value after receiving the trigger pulse. The quantity counter 122 is connected to the trigger button 302 and the quantity register 121 to receive the trigger pulse and the pulse quantity setting value. The quantity counter 122 is also connected to the interval counter 112 to count the pulse signal after receiving the trigger pulse, and sends a stop signal to the interval counter 112 when the pulse quantity setting value is reached. The interval counter 112 stops outputting the pulse signal according to the stop signal. The input terminal of the optocoupler relay 200 is electrically connected to the interval counter 112 to receive the pulse signal. The output terminal of the optocoupler relay 200 is used to connect to the device under test to send the pulse signal to the device under test.

[0041] The device under test can refer to the corresponding device in the Sequence of Events (SOE) system under test.

[0042] The pulse interval can be understood as the time interval between adjacent pulse signals. The pulse interval can be set via the DIP switch group 301. The programmable logic array 100 can receive the pulse interval setting value and then input multiple pulse signals with intervals satisfying the pulse interval setting value. The pulse quantity setting value can be understood as the number of pulse signals continuously output by the programmable logic array 100 according to the pulse interval setting value after the trigger button 302 outputs a single trigger pulse.

[0043] Based on the above technical solution, the programmable logic array 100 can precisely control the interval between multiple output pulse signals according to the received pulse interval setting value, effectively controlling the time error of the pulse signals and improving the time accuracy of each pulse signal. Simultaneously, the number of pulse signals can be precisely controlled according to the pulse quantity setting value, thus facilitating the provision of accurate test signal sequences to the device under test (DUT), enabling the DUT to complete accurate event sequence recording tests. Furthermore, the optocoupler relay 200 not only achieves electrical isolation, effectively avoiding electrical interference between the test signal generation device and the DUT, improving system stability and safety, but also enhances the pulse signal by increasing current or voltage, ensuring the DUT can accurately acquire the pulse signal, thereby improving test accuracy and reliability. In addition, the fast response characteristic of the optocoupler relay 200 ensures pulse signal transmission efficiency, further improving test accuracy. Moreover, the design of the DIP switch group 301 allows users to easily set the required pulse quantity and pulse interval to meet the needs of different test scenarios without complex programming or configuration processes, improving the ease of use of the device. The trigger button 302 provides users with an intuitive operating method; a simple press triggers the output of a pulse signal, further simplifying the operation process. Thus, this application provides a user-friendly test signal generation device capable of generating precise pulse signals.

[0044] In practical applications, the test signal generation device of this application can be widely used in thermal power plants, nuclear power plants, chemical enterprises and other occasions that require event sequence recording systems. It can be used to accurately and reliably test the performance of these systems, help maintenance personnel quickly analyze faults, find the causes of faults, and improve the operating efficiency and safety of the system.

[0045] In one example, the DIP switch group 301 outputs the pulse quantity setting and pulse interval setting in parallel level mode.

[0046] In one example, both the interval counter 112 and the optocoupler relay 200 are present in one quantity. Thus, a single optocoupler relay 200 can send multiple pulse signals output by the interval counter 112 to the device under test. Of course, in practical applications, it should be noted that the pulse frequency must be less than or equal to the maximum allowable switching frequency of the optocoupler relay 200. In one example, the pulse interval setting can be 1 ms, or only 1 kHz. Common optocoupler relays (such as PC817, TLP521, TLP127, ACPL-M50L, etc.) have switching frequencies ranging from several kHz to several MHz, all of which can meet the condition that the pulse frequency must be less than or equal to the maximum allowable switching frequency of the optocoupler relay 200.

[0047] In another example, refer to Figure 2 The interval counter 112 has one unit, and the optocoupler relays 200 have multiple units. The programmable logic array 100 also includes a pulse wheel switch circuit 140 and multiple single-channel output ports 150. The number of single-channel output ports 150, the number of optocoupler relays 200, and the pulse number setting are the same. One of the multiple optocoupler relays 200 is connected to one of the multiple single-channel output ports 150. The input terminal of the pulse wheel switch circuit 140 is connected to the pulse output terminal of the interval counter 112, and the input terminal of the pulse wheel switch circuit 140 is connected to the multiple single-channel output ports 150. The pulse wheel switch circuit 140 is used to sequentially distribute the multiple pulse signals output by the interval counter 112 to the multiple single-channel output ports 150, so that each single-channel output port 150 outputs one pulse signal. Based on this technical solution, by setting up a pulse wheel switching circuit 140 and multiple single-channel output ports 150, and connecting each of the single-channel output ports 150 to a corresponding optocoupler relay 200, the serial pulse stream output by a single interval counter 112 can be distributed to multiple independent channels. Each single-channel output port 150 is connected to the device under test (DUT) through a corresponding optocoupler relay 200, enabling the test signal generation device to simultaneously output independent pulse signal sequences to multiple DUTs. This design not only improves testing efficiency and allows for parallel testing of multiple devices, but also ensures the accuracy and reliability of pulse distribution through hardware counting and decoding. Furthermore, since each channel is completely independent, signal interference between channels is avoided, further improving the accuracy and stability of the test.

[0048] Furthermore, in one specific embodiment, the test signal generation device may also include an output-side connector. When there are multiple optocoupler relays 200, the output-side connector is a multi-pin interface type, and the output interfaces of each optocoupler relay 200 are connected to the device under test (DUT) through the same output-side connector. This design facilitates connection between the DUT and the 200 in the SOE system under test using a single or few cables, improving the convenience and reliability of the test. In one example, the total number of optocoupler relays 200 is 16, and the output terminal of each optocoupler relay 200 can be connected to a DB25 multi-pin interface output-side connector. The DB25 output-side connector has 25 pins, sufficient to accommodate 16 channel signals and one common terminal, as well as other possible signals (such as ground, shield, etc.), thus allowing the pulse count setting to be 16. This connection method makes the connection between the test signal generation device and the SOE system under test simple and reliable. Users only need to use a single DB25 cable to connect all channels, avoiding cumbersome wiring processes and improving the convenience and reliability of the test.

[0049] In one possible embodiment, the interval register 111 has a first parallel output terminal, and the interval counter 112 has a second preset input terminal, a second count enable terminal, and a pulse output terminal. The second preset input terminal is connected to the first parallel output terminal of the interval register 111 to load a latched pulse interval setting value. The second count enable terminal is connected to the trigger button 302 to start counting after receiving a trigger pulse. The interval counter 112 counts according to the pulse interval setting value. When the count reaches zero, a pulse signal is output through the pulse output terminal, and the pulse interval setting value is immediately and automatically reloaded to start the next counting cycle. Based on this counting scheme, the interval counter 112 can accurately output pulse signals according to the pulse interval setting value. After each pulse signal is output, the pulse interval setting value is automatically reloaded, and a new counting cycle begins to output the next pulse signal. This continues until the interval counter 112 receives a stop signal and stops outputting pulse signals. This not only ensures the continuity and accuracy of the pulse signal output but also allows the output of a test signal sequence composed of multiple intervald pulse signals. The number of pulse signals in this test signal sequence equals the pulse quantity setting value, and the interval between adjacent pulse signals equals the pulse interval setting value. This design not only improves the timing accuracy of the pulse signal but also makes the entire testing process more automated and reliable. Furthermore, since the second counting enable terminal of the interval counter 112 is connected to the trigger button 302, the user can trigger the output of the pulse signal through simple button operation, further simplifying the operation process and improving testing efficiency.

[0050] In one example, the interval register 111 also has a first parallel input terminal and a first latch trigger terminal. The first parallel input terminal of the interval register 111 is connected to the output pin of the DIP switch group 301 to acquire the pulse interval setting value in parallel. The first latch trigger terminal of the interval register 111 is connected to the trigger button 302 to receive the trigger pulse. The interval register 111 latches the pulse interval setting value under the trigger action of the trigger pulse.

[0051] In one example, the quantity register 121 has a third parallel input, a third latch trigger, and a third parallel output. The third parallel input is directly connected to the output pin of the DIP switch group 301 to acquire the pulse quantity setting value in parallel. The third latch trigger is connected to the single pulse output of the trigger button 302 to receive the trigger pulse. After receiving the trigger pulse at the third latch trigger, the quantity register 121 latches the pulse quantity setting value.

[0052] In one possible implementation, the count counter 122 includes a stop output terminal, through which it outputs a stop signal. The interval counter 112 also includes a stop input terminal, which is connected to the stop output terminal to receive the stop signal. The interval counter 112 stops outputting pulse signals according to the stop signal. Based on this technical solution, when the count reaches the set pulse count value, the count counter 122 outputs a stop signal through the stop output terminal in a timely manner. This stop signal is quickly transmitted to the stop input terminal of the interval counter 112, enabling the interval counter 112 to respond immediately and stop outputting pulse signals. This process ensures that the number and interval time of the pulse signals are output strictly according to their respective set values, thereby improving the accuracy and reliability of the test signal. At the same time, this design also avoids the adverse effects on the test results caused by too many or too few pulse signals, further improving the accuracy and efficiency of the test.

[0053] Furthermore, in one specific embodiment, the count counter 122 has a fourth preset input terminal, a counting clock terminal, and a fourth counting enable terminal. The fourth preset input terminal is connected to the count output terminal of the count register 121 to load a pulse count setting value. The fourth counting enable terminal is connected to the trigger button 302 to start counting when a trigger pulse is received. The counting clock terminal is connected to the pulse output terminal of the interval counter 112 to count once for each received pulse signal. When the count value equals the pulse count setting value, the count counter 122 outputs a stop signal at the stop output terminal. Based on this technical solution, the count counter 122, through close cooperation with the count register 121 and the interval counter 112, achieves precise control over the number of pulse signals. Specifically, the fourth preset input terminal loads the pulse count setting value from the count register 121, providing a reference for the subsequent counting process. The fourth counting enable terminal is connected to the trigger button 302, allowing the user to start the counting process through simple button operation, improving operational convenience. The connection between the counting clock terminal and the pulse output terminal of the interval counter 112 ensures that the quantity counter 122 can accurately count each pulse signal. When the count value reaches the pulse count set value, the quantity counter 122 immediately outputs a stop signal at the stop output terminal, thereby timely terminating the pulse signal output of the interval counter 112. This process not only ensures the accuracy of the pulse signal count but also avoids test errors caused by excessive pulse signals, further improving the accuracy and reliability of the test.

[0054] The width of the pulse signal affects the signal reception and recognition performance of the device under test, therefore, the pulse signal width is quite important. Therefore, in the test signal generation device of this application, reference is made to... Figure 3The DIP switch group 301 is also used to output a pulse width setting value according to the user setting; the programmable logic array 100 also includes a width register 131 and a monostable multivibrator 132, wherein the width register 131 is connected to the DIP switch group 301 and the trigger button 302, and is used to latch the pulse width setting value after receiving a trigger pulse; the monostable multivibrator 132 has a fifth preset input terminal, a trigger input terminal and a fixed width output terminal. The fifth preset input terminal of the monostable multivibrator 132 is connected to the width register 131 and is used to load the pulse width setting value. The trigger input terminal of the monostable multivibrator 132 is connected to the interval counter 112 to receive the pulse signal. The monostable multivibrator 132 widens the pulse signal into a fixed width pulse equal to the pulse width setting value, and outputs the fixed width pulse through the fixed width output terminal; the input terminal of the optocoupler relay 200 is connected to the fixed width output terminal to receive the fixed width pulse.

[0055] Based on this technical solution, the width register 131 can quickly latch the pulse width setting value from the DIP switch group 301 after receiving the trigger pulse, providing a precise reference for subsequent pulse widening operations. The monostable multivibrator 132 loads the pulse width setting value through its fifth preset input terminal, and when it receives a pulse signal from the interval counter 112 at its trigger input terminal, it immediately widens the pulse signal into a fixed-width pulse equal to the pulse width setting value. That is, by connecting the monostable multivibrator 132 between the interval counter 112 and the optocoupler relay 200, each pulse signal output by the interval counter 112 can be converted into a fixed-width pulse equal to the pulse width setting value before being output to the optocoupler relay 200. This process ensures that each pulse signal output by the programmable logic array 100 has a consistent width, and the input terminal of the optocoupler relay 200 can accurately receive and transmit these fixed-width pulse signals, thereby improving the signal reception and recognition effect of the device under test. Furthermore, since the pulse width can be easily set by the DIP switch group 301, the test signal generation device of this application can adapt to the needs of different test scenarios, improving the flexibility and versatility of the device. This design allows for precise control of the pulse signal width, meeting the pulse signal width requirements of different devices under test, further improving the accuracy and applicability of the test signal, and ensuring that the test results can truly reflect the performance of the test event sequence recording system.

[0056] In one example, DIP switch group 301 outputs the pulse width setting in parallel level mode.

[0057] The pulse width can be understood as the duration of each pulse signal. Regarding the pulse signal output by the interval counter 112, it can be implemented as follows: the interval counter 112 counts according to the set pulse interval value. Whenever the count reaches zero, the hardware circuit automatically pulls the pulse output terminal level low (or high). After a pulse signal of the preset width has passed, the level returns to normal, thus completing the output of one pulse signal. One counting cycle corresponds to one level toggle and one pulse signal output. That is, the time between the pulse output terminal level being pulled low (or high) and returning to normal is equivalent to the pulse signal width.

[0058] Further reference Figure 4In one example, there are multiple optocoupler relays 200. The programmable logic array 100 includes a width register 131, a monostable multivibrator 132, a pulse wheel switching circuit 140, and multiple single-channel output ports 150. The number of single-channel output ports 150, the number of optocoupler relays 200, and the pulse count are all set to the same value. The multiple optocoupler relays 200 and the multiple single-channel output ports 150 are connected in a one-to-one correspondence. The trigger input of the monostable multivibrator 132 is connected to the interval counter 112 to receive pulse signals. Device 132 widens the pulse signal into a fixed-width pulse equal to the pulse width setting value and outputs the fixed-width pulse through the fixed-width output terminal. The input terminal of the pulse wheel switch circuit 140 is connected to the fixed-width output terminal of the monostable multivibrator 132, and the output terminal of the pulse wheel switch circuit 140 is connected to multiple single-channel output ports 150. The pulse wheel switch circuit 140 distributes the multiple interval pulse signals output by the monostable multivibrator 132 to the multiple single-channel output ports 150, so that each single-channel output port 150 outputs a fixed-width pulse signal. Based on this technical solution, by setting the width register 131, the monostable multivibrator 132, and the pulse wheel switch circuit 140, and by making the multiple single-channel output ports 150 correspond one-to-one with the multiple optocoupler relays 200, precise control of the pulse signal width and output channels is achieved. Specifically, the width register 131 latches the pulse width setting value after receiving the trigger pulse, providing a precise widthing reference for the monostable multivibrator 132. The monostable multivibrator 132 then widens the pulse signal from the interval counter 112 into a fixed-width pulse, ensuring that each output pulse has a consistent width. The pulse wheel switch circuit 140 sequentially distributes multiple serial pulse signals to multiple single-channel output ports 150, enabling each channel to independently output a fixed-width pulse signal. This design not only ensures the accuracy of the pulse signal width but also enables parallel testing of multiple devices under test through multi-channel independent output, significantly improving testing efficiency. Simultaneously, since each channel is completely independent, signal interference is avoided, further enhancing testing accuracy and stability. In one example, the pulse wheel switch circuit 140 uses a hardware counting-decoding method to sequentially distribute multiple serial pulse signals output by the interval counter 112 to multiple single-channel output ports 150.

[0059] In one possible implementation, refer to Figure 5The programmable logic array 100 also includes a clock source 160, which generates a fixed-frequency clock signal. The interval register 111 and the quantity register 121 are both connected to the clock source 160 to obtain a synchronous clock. The interval counter 112 is connected to the clock source 160 for decrementing or incrementing the count. Furthermore, the width register 131 and the monostable multivibrator 132 can also be connected to the clock source 160 to obtain a synchronous clock signal. Based on this technical solution, the fixed-frequency clock signal generated by the clock source 160 provides a unified timing reference for the entire programmable logic array 100. The interval register 111 and the quantity register 121, connected to the clock source 160, can accurately latch and update data according to the synchronous clock, ensuring the accuracy and stability of the pulse interval setting and the pulse quantity setting. The interval counter 112 uses the clock signal from the clock source 160 to decrement or increment the count, thereby precisely controlling the output time interval of the pulse signal. Similarly, after the width register 131 and the monostable multivibrator 132 are connected to the clock source 160, the width register 131 can latch the pulse width setting value under accurate clock ticks, while the monostable multivibrator 132 accurately widens the pulse signal to the set width according to the synchronous clock signal. This design enables all modules of the entire test signal generation device to work collaboratively under a unified clock signal, greatly improving the time accuracy and stability of the pulse signal output, further enhancing the accuracy and reliability of the test signal, and better meeting the needs of accurate testing of the equipment under test in different test scenarios.

[0060] Furthermore, in one possible embodiment, refer to Figure 5 The test signal generation device also includes a Global Navigation Satellite System (GNSS) receiver module 400. The output of the GNSS receiver module 400 is connected to the calibration input of the clock source 160, used to output the received satellite timing signal to the clock source 160 for frequency calibration of the fixed-frequency clock signal. Based on this technical solution, the GNSS receiver module 400 can receive precise time signals from satellites, which have extremely high time accuracy and stability. By connecting the output of this module to the calibration input of the clock source 160 in the test signal generation device, the satellite timing signal can be introduced into the clock source 160, thereby calibrating the fixed-frequency clock signal generated by the clock source 160 in real time. This calibration mechanism can effectively eliminate frequency drift of the clock source 160 caused by environmental factors, component aging, etc., ensuring the long-term stability and accuracy of the clock signal.

[0061] The Global Navigation Satellite System (GNSS) receiver module 400 is a device capable of receiving and parsing satellite signals. The GNSS receiver module 400 can be a GPS (Global Positioning System) receiver module or a BDS (Beijing Navigation Satellite System) receiver module. Taking a GPS receiver module as an example, a GPS receiver module typically includes a GPS antenna, a radio frequency front-end, and a baseband processing unit. In the test signal generation device provided in this application, the GPS receiver module is responsible for receiving the time and position signals transmitted by GPS satellites and transmitting the parsed time data (such as UTC time) and the second pulse signal (1PPS, one pulse per second, with an accuracy up to the nanosecond level) to the clock source 160.

[0062] The calibration logic for clock source 160 can be as follows: When a Global Navigation Satellite System (GNSS) receiver module (such as a GPS receiver module) receives a pulse-per-second (1PPS) signal transmitted by a satellite, it transmits this high-precision time signal to the calibration input of clock source 160. Clock source 160 internally contains calibration logic circuitry that compares the received pulse-per-second signal with its own fixed-frequency clock signal. If a frequency deviation is detected (e.g., clock frequency shift due to temperature changes or device aging), the calibration logic circuitry adjusts the oscillation parameters inside clock source 160 (e.g., adjusting the control voltage of the voltage-controlled oscillator) to gradually bring the frequency of the output clock signal closer to the satellite signal's frequency standard. Simultaneously, clock source 160 records the adjustment amount for each calibration and eliminates accumulated errors through a dynamic compensation mechanism. For example, if the GPS receiver module detects that the clock source 160 frequency is too fast within several consecutive calibration cycles, the calibration logic will gradually reduce the oscillation frequency until the phase difference between the clock signal and the satellite signal stabilizes within a preset threshold. This closed-loop calibration method ensures that the fixed-frequency clock signal output by the clock source 160 maintains high precision over a long period of time, thereby providing a reliable timing reference for modules such as the interval counter 112 and the quantity counter 122, and ultimately improving the output accuracy of the entire test signal generation device.

[0063] In one example, the Global Navigation Satellite System receiver module 400 can be an UBLOX NEO-7M module, which is connected to the clock source 160 via a UART serial port.

[0064] Furthermore, in one possible embodiment, the test signal generation device includes a main power supply and a backup power supply. The clock source 160 includes a main power supply pin and a backup power supply pin, with the main power supply pin connected to the main power supply and the backup power supply pin connected to the backup power supply. Based on this technical solution, the main power supply serves as the primary energy source for the clock source 160, providing a stable operating voltage to the clock source 160 under normal circumstances, ensuring that the clock source 160 can continuously and accurately generate a fixed-frequency clock signal. The backup power supply is in standby mode; if the main power supply fails, such as due to abnormal voltage or power outage, the backup power supply will immediately supply power to the clock source 160 through the backup power supply pin. This dual-power supply design allows the clock source 160 to seamlessly switch power supplies in the event of a power failure, avoiding clock signal interruption or frequency abrupt changes caused by power outages, thereby ensuring the continuity and stability of the clock signal.

[0065] In addition, the DIP switch group 301, trigger button 302, interval register 111, interval counter 112, quantity register 121 and quantity counter 122, optocoupler relay 200, width register 131 and monostable trigger 132 can all be connected to the main power supply to obtain electrical energy.

[0066] In one possible embodiment, the test signal generation device further includes multiple current-limiting resistors, with one resistor connected in series between the interval counter 112 and the input terminal of the optocoupler relay 200. Based on this technical solution, the current-limiting resistor plays a crucial role in limiting the current magnitude in the circuit. When the interval counter 112 outputs a pulse signal, this signal is transmitted to the input terminal of the optocoupler relay 200 through the current-limiting resistor. Due to the presence of the current-limiting resistor, even if the current output by the interval counter 112 fluctuates or abnormally increases, the current reaching the input terminal of the optocoupler relay 200 will be limited within a safe range, thereby avoiding the risk of damaging the optocoupler relay 200 or other circuit components due to excessive current. Of course, in practical applications, the selection of the current-limiting resistor needs to comprehensively consider factors such as the circuit's operating current, the input impedance of the optocoupler relay 200, and the stability of signal transmission to ensure that while limiting the current, it does not significantly affect the transmission quality of the pulse signal. This design not only improves the reliability and stability of the test signal generation device but also extends the device's service life and reduces maintenance costs.

[0067] In addition, the test signal generation device may also include a touch screen, which can be connected to the DIP switch group 301 and the trigger button 302 to achieve more intuitive and convenient operation control. Users can directly input pulse interval settings, pulse quantity settings, and pulse width settings through the touch screen, eliminating the need for manual adjustment of the DIP switch group 301 and greatly simplifying the operation process. Simultaneously, the touch screen can also display the current operating status of the test signal generation device in real time, including the number of output pulses and the parameters of the pulse signal being output, allowing users to easily monitor the test progress.

[0068] In practical applications, a microcontroller can be used to replace the programmable logic array 100. The microcontroller's hardware timer serves as the time reference for the pulse signals. The clock source 160 of the hardware timer's internal counter comes from the microcontroller's system master clock, providing high time accuracy and effectively controlling the time error of the pulse signals, thus improving the time precision of each pulse signal. Specifically, compared to traditional software programs that are prone to time instability and jitter during execution, the hardware timer's time reference is directly derived from a crystal oscillator. The timing error depends only on the crystal oscillator itself, with no software-accumulated drift. Furthermore, counting, comparing, and output toggling are all performed by silicon circuits, resulting in zero instruction and zero interrupt response. The period jitter is less than one clock cycle, thus achieving reliable microsecond-level accuracy and ensuring that the time interval accuracy of the output pulse sequence reaches the microsecond level.

[0069] Specifically, pulse signals can be output from the microcontroller's input / output ports (I / O ports). The input / output ports of the microcontroller have high and low level states. Under the control of a hardware timer, the input / output ports toggle between high and low levels. Each time a toggle occurs, the corresponding optocoupler relay 200 immediately turns on or off. The sequence of input / output port levels of the microcontroller is equivalent to the pulse signal output by the microcontroller.

[0070] In one example, the microcontroller can be an STM32F103 series microcontroller, and the hardware timer is the TIM1 or TIM8 advanced control timer integrated inside the microcontroller.

[0071] In one example, the microcontroller can be the SIMATIC S7-1500 model. This model also features powerful hardware timers and abundant I / O interface resources, meeting the requirements of test signal generation devices for high-precision time control and multi-channel signal output. Its integrated hardware timer module supports multiple operating modes, including an output compare mode, which can accurately generate the pulse sequence required by the user. Furthermore, the SIMATIC S7-1500 microcontroller's input / output ports are flexibly configurable and can be easily configured via software for timer output compare functions, achieving seamless connection with the optocoupler relay 200.

[0072] In one example, the optocoupler relay 200 can be model TLP521-4. This model of optocoupler relay 200 has four independent optocoupler channels, which can meet the requirements of multi-channel signal isolation and control in test signal generation devices. Internally, it uses a combination of high-sensitivity light-emitting diodes and phototransistors to ensure reliable operation even with low drive current, while providing good electrical isolation performance to effectively prevent electrical interference between the test signal generation device and the device under test. Furthermore, the TLP521-4 optocoupler relay 200 has a fast response speed, ensuring accurate pulse signal transmission and meeting the stringent signal timing requirements of high-precision SOE testing. In practical applications, the model and quantity of optocoupler relays 200 can be flexibly selected according to the number and requirements of test channels to construct test signal generation devices that meet different testing scenarios.

[0073] In one example, the microcontroller can have 16 channels, each corresponding to one of the 16 input / output ports (I / O ports). That is, one channel corresponds to one input / output port. There are also 16 optocoupler relays 200, each connected to one of the microcontroller's 16 input / output ports. Thus, by sequentially toggling the level of each of the 16 input / output ports at 1mm intervals, each of the 16 I / O ports can output a pulse signal, allowing the microcontroller to output a signal sequence consisting of 16 pulse signals spaced 1mm apart.

[0074] In one example, a current-limiting resistor can be connected in series between the microcontroller and the optocoupler relay 200. For instance, the anode of the input interface of each optocoupler relay 200 can be connected to a DC power supply (e.g., a +3.3V DC power supply) through a current-limiting resistor (e.g., 1kΩ), while the cathode of the input interface is directly connected to an input / output port of the microcontroller. When the microcontroller needs to turn on a certain optocoupler, it sets the corresponding input / output port to a low level. At this time, current flows from the positive terminal of the power supply through the current-limiting resistor, the LED inside the optocoupler, and into the input / output port of the microcontroller (current sinking method). The function of the current-limiting resistor is to limit the current and protect the input / output port of the microcontroller and the LED of the optocoupler from damage due to overcurrent.

[0075] By using the test signal generation device provided in this application, users can set and obtain accurate test start time and interval time between pulse signals from the test signal generation device. Then, users can compare the event occurrence table of the SOE under test recorded by the SOE under test system to verify whether the records of the SOE under test system are accurate and reliable.

[0076] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0077] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A test signal generation device, characterized in that, The test signal generation device includes: A DIP switch group (301) is used to output pulse quantity setting value and pulse interval setting value according to user settings; A trigger button (302) is used to output a single trigger pulse when it is operated; The programmable logic array (100) includes an interval register (111), an interval counter (112), a count register (121), and a count counter (122), wherein, The interval register (111) is connected to the DIP switch group (301) and the trigger button (302) to receive the pulse interval setting value and the trigger pulse. The interval register latches the pulse interval setting value after receiving the trigger pulse. The interval counter (112) is connected to the trigger button (302) and the interval register (111) to receive the trigger pulse and the pulse interval setting value. After receiving the trigger pulse, the interval counter (112) outputs multiple interval pulse signals according to the pulse interval setting value. The quantity register (121) is connected to the DIP switch group (301) and the trigger button (302) to receive the pulse quantity setting value and the trigger pulse. The quantity register (121) latches the pulse quantity setting value after receiving the trigger pulse. The quantity counter (122) is connected to the trigger button (302) and the quantity register (121) to receive the trigger pulse and the pulse quantity setting value. The quantity counter (122) is also connected to the interval counter (112) to count the pulse signal after receiving the trigger pulse, and send a stop signal to the interval counter (112) when the pulse quantity setting value is reached. The interval counter (112) stops outputting the pulse signal according to the stop signal. An optocoupler relay (200) is provided, the input terminal of which is electrically connected to the interval counter (112) to receive the pulse signal, and the output terminal of which is used to connect to the device under test to send the pulse signal to the device under test.

2. The test signal generation device according to claim 1, characterized in that, The number of the interval counter (112) and the optocoupler relay (200) is one; or, The number of the interval counter (112) is one, and the number of the optocoupler relays (200) is multiple. The programmable logic array (100) further includes a pulse wheel switch circuit (140) and multiple single-channel output ports (150). The number of single-channel output ports (150), the number of optocoupler relays (200), and the pulse number setting value are the same. One of the multiple optocoupler relays (200) is connected to one of the multiple single-channel output ports (150). The input terminal of the pulse rotation switch circuit (140) is connected to the pulse output terminal of the interval counter (112). The input terminal of the pulse rotation switch circuit (140) is connected to multiple single-channel output ports (150). The pulse rotation switch circuit (140) is used to sequentially distribute the multiple pulse signals output by the interval counter (112) to the multiple single-channel output ports (150) so that each single-channel output port (150) outputs one pulse signal.

3. The test signal generation device according to claim 1, characterized in that, The interval register (111) has a first parallel output terminal, and the interval counter (112) has a second preset input terminal, a second counting enable terminal, and a pulse output terminal, wherein, The second preset input terminal is connected to the first parallel output terminal of the interval register (111) to load the latched pulse interval setting value. The second counting enable terminal is connected to the trigger button (302) to start counting the interval counter (112) upon receiving the trigger pulse. The interval counter (112) counts according to the pulse interval setting value. When the count reaches zero, it outputs a pulse signal through the pulse output terminal and immediately and automatically reloads the pulse interval setting value to start the next counting cycle.

4. The test signal generation device according to claim 3, characterized in that, The quantity counter (122) includes a stop output terminal, and the quantity counter (122) outputs the stop signal through the stop output terminal; The interval counter (112) further includes a stop input terminal, which is connected to the stop output terminal to receive the stop signal. The interval counter (112) stops outputting the pulse signal according to the stop signal.

5. The test signal generation device according to claim 4, characterized in that, The count counter (122) has a fourth preset input terminal, a counting clock terminal, and a fourth counting enable terminal, wherein, The fourth preset input terminal is connected to the quantity output terminal of the quantity register (121) to load the pulse quantity setting value; The fourth counting enable terminal is connected to the trigger button (302) to enable the quantity counter (122) to start counting when the trigger pulse is received; The counting clock terminal is connected to the pulse output terminal of the interval counter (112) and is used to count once when each pulse signal is received. When the count value is equal to the pulse quantity setting value, the quantity counter (122) outputs the stop signal at the stop output terminal.

6. The test signal generation device according to claim 1, characterized in that, The DIP switch group (301) is also used to set the output pulse width setting value according to the user setting; The programmable logic array (100) further includes a width register (131) and a monostable multivibrator (132), wherein, The width register (131) is connected to the DIP switch group (301) and the trigger button (302) and is used to latch the pulse width setting value after receiving the trigger pulse; The monostable multivibrator (132) has a fifth preset input terminal, a trigger input terminal, and a fixed width output terminal. The fifth preset input terminal of the monostable multivibrator (132) is connected to the width register (131) and is used to load the pulse width setting value. The trigger input terminal of the monostable multivibrator (132) is connected to the interval counter (112) to receive the pulse signal. The monostable multivibrator (132) expands the pulse signal into a fixed-width pulse equal to the pulse width setting value and outputs the fixed-width pulse through the fixed-width output terminal. The input terminal of the optocoupler relay (200) is connected to the fixed-width output terminal to receive the fixed-width pulse.

7. The test signal generation device according to any one of claims 1-6, characterized in that, The programmable logic array (100) also includes a clock source (160) for generating a fixed-frequency clock signal; The interval register (111) and the quantity register (121) are both connected to the clock source (160) to obtain a synchronous clock. The interval counter (112) is connected to the clock source (160) for decrementing or incrementing the count.

8. The test signal generation device according to claim 7, characterized in that, The test signal generation device further includes a global navigation satellite system receiving module (400), the output of which is connected to the calibration input of the clock source (160) to output the received satellite timing signal to the clock source (160) for frequency calibration of the fixed frequency clock signal.

9. The test signal generation device according to claim 7, characterized in that, The test signal generation device includes a main power supply and a backup power supply. The clock source (160) includes a main power supply pin and a backup power supply pin. The main power supply pin is connected to the main power supply, and the backup power supply pin is connected to the backup power supply.

10. The test signal generation device according to claim 1, characterized in that, The test signal generation device further includes multiple current-limiting resistors, one of which is connected in series between the interval counter (112) and the input terminal of the optocoupler relay (200).

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