A digital delay-locked loop circuit and memory

Abstract

The utility model provides a kind of digital delay-locked loop circuit and memory, digital delay-locked loop circuit includes: the delay chain of multiple delay units cascaded;The first control end, second control end of each delay unit is used to receive first control signal, second control signal respectively;For any other delay unit in delay chain, the first input end, the first output end, the second output end, the second input end of this delay unit are respectively connected with the second output end of last delay unit, the second input end of last delay unit, the first input end of next delay unit, the first output end of next delay unit. To solve the technical problem that memory is difficult to delay processing of high requirement of DQS and DQ by the utility model provides a kind of digital delay-locked loop circuit and memory.

Description

Technical Field

[0001] This utility model relates to the field of storage, and in particular to a digital delay-locked loop circuit and a memory. Background Technology

[0002] In the field of storage systems, timing skew occurs between the clock signal (DQS) and the data signal (DQ) due to differences in transmission paths, affecting the accuracy of data sampling. In existing technologies, delay-locked loops (DLLs) are mostly implemented using analog delay units, with purely digital DLLs being relatively rare. Some digital DLLs use delay chains based on inverter buffers and select the delay length using a multiplexer. However, this type of structure has scalability limitations; as the delay chain length increases, the size and load of the multiplexer increase accordingly, leading to inconsistent loads under different delay configurations.

[0003] The aforementioned structure introduces significant linearity issues and duty cycle distortion when the multiplexer load varies with the delay length. Furthermore, traditional solutions struggle to achieve a smooth, glitch-free transition when switching DLL delay sizes, limiting their application in high-precision, scalable interfaces and failing to fully meet the stringent requirements of memory for DQS and DQ delay processing. Therefore, improvements are needed. Utility Model Content

[0004] This invention provides a digital delay-locked loop circuit and a memory to solve the technical problem that the memory is difficult to handle the high requirements of DQS and DQ delay processing.

[0005] This utility model provides a digital delay-locked loop circuit, comprising: a delay chain formed by cascading multiple delay units; each delay unit has a first input terminal, a first output terminal, a second input terminal, a second output terminal, a first control terminal, and a second control terminal; The first control terminal and the second control terminal of each delay unit are used to receive the first control signal and the second control signal, respectively. For the first delay unit in the delay chain, its first input terminal and first output terminal are respectively used to receive the original clock signal and output the delayed clock signal; For the last delay unit in the delay chain, its second output terminal and second input terminal are respectively used to be left floating and to receive high-level / low-level signals; For any other delay unit in the delay chain, the first input, first output, second output, and second input of the delay unit are respectively connected to the second output, second input, first input, and first output of the previous delay unit; Specifically, the first control signal and the second control signal of each delay unit are determined according to the delay duration of the clock signal.

[0006] In one embodiment of the present invention, the delay unit includes: The first logic gate circuit has two input terminals and one output terminal, one of which forms the second control terminal and the output terminal forms the second output terminal; The second logic gate circuit has two input terminals and one output terminal. One of its input terminals forms the first control terminal, and the other input terminal and the other input terminal of the first logic gate circuit together form the first input terminal. The third logic gate has two inputs and one output. One of its inputs forms the second input, and the other input is connected to the output of the second logic gate. Its output forms the first output.

[0007] In one embodiment of this utility model, the first logic gate circuit, the second logic gate circuit, and the third logic gate circuit are NAND gate circuits.

[0008] In one embodiment of the present invention, the NAND gate circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form an input terminal; The gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form another input terminal; The drains of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected to form an output terminal; The source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the power supply. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is grounded.

[0009] In one embodiment of the present invention, the first PMOS transistor and the second PMOS transistor are of type SMIC_N28HKCPPMOS, and the first NMOS transistor and the second NMOS transistor are of type SMIC_N28HKCPNMOS.

[0010] In one embodiment of the present invention, the delay unit is used to selectively output the received clock signal to a first output terminal or to a second output terminal through a first input terminal, based on the first control signal and the second control signal.

[0011] In one embodiment of the present invention, when the first control signal is a low-level signal and the second control signal is a high-level signal, the delay unit outputs the received clock signal to the second output terminal through the first input terminal; When the first control signal is a high-level signal and the second control signal is a low-level signal, the delay unit outputs the received clock signal to the first output terminal through the first input terminal.

[0012] In one embodiment of the present invention, when the first n delay units are selected to delay the clock signal in the delay chain, the delay chain is used to receive n+1 sets of control signals, and the n+1 sets of control signals correspond to n+1 delay units. Among them, the first control signal and the second control signal in the first n-1 groups of control signals are low-level signals and high-level signals, respectively; the first n-1 delay units are used to output the received clock signal from its first input terminal to its second output terminal; The first control signal and the second control signal in the nth group of control signals are high-level signals and low-level signals, respectively; the nth delay unit is used to output the received clock signal from its first input terminal to its first output terminal; The first control signal of the (n+1)th group of control signals is a high-level signal. The (n+1)th delay unit is used to receive the high-level signal of the second output terminal of the nth delay unit through its first input terminal, and output a high-level signal to the second input terminal of the nth delay unit in sequence through its second logic gate circuit, third logic gate circuit, and first output terminal. The first n-1 delay units are also used to output the returned clock signal to its first output through its second input.

[0013] This invention also provides a memory, including the aforementioned digital delay-locked loop circuit.

[0014] The beneficial effects of this invention are as follows: The digital delay-locked loop circuit, through a cascaded delay chain and dual control signal control mechanism, effectively overcomes the linearity and duty cycle distortion problems caused by the load variation of the multiplexer with the delay length in traditional digital DLLs. Since the input and output loads of each delay unit are fixed and unaffected by the delay chain length, the uniformity and consistency of delay adjustment are guaranteed. Simultaneously, all signal paths are processed through structurally consistent delay units, avoiding the duty cycle degradation caused by uneven load in traditional schemes, and significantly improving data sampling accuracy. Attached Figure Description

[0015] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0016] In the attached diagram: Figure 1 A schematic diagram of a digital delay-locked loop circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of a delay unit provided in one embodiment of the present invention; Figure 3 This is a schematic diagram of a NAND gate circuit provided in one embodiment of the present invention.

[0017] The attached figures are labeled as follows: 10. Delay unit; 20. First logic gate; 30. Second logic gate; 40. Third logic gate. Detailed Implementation

[0018] The following specific examples illustrate the implementation of this utility model. Those skilled in the art can easily understand other advantages and effects of this utility model from the content disclosed in this specification. This utility model can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this utility model. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. The drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present invention. However, it will be apparent to those skilled in the art that embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present invention.

[0021] This invention discloses a digital delay-locked loop (DLL) circuit, which can be applied in memory to delay clock signals. The DLL circuit can employ a fully digital architecture, forming a delay chain through the cascading of multiple configurable delay units. Each delay unit can select a different signal path according to the control signal, thereby achieving flexible and precise delay adjustment.

[0022] Please see Figure 1 and Figure 2 In some embodiments, the digital delay-locked loop circuit can be a delay chain composed of multiple cascaded delay units 10. Each delay unit 10 may have a first input terminal (In1), a first output terminal (Out1), a second input terminal (In2), a second output terminal (Out2), a first control terminal (Ctrl1), and a second control terminal (Ctrl2). The first control terminal and the second control terminal of each delay unit 10 are used to receive a first control signal and a second control signal, respectively. The first control signal and the second control signal together determine the connectivity of the signal path within each delay unit 10.

[0023] Please see Figure 1 In some embodiments, for the first delay unit in the delay chain, its first input terminal and first output terminal are respectively used to receive the original clock signal and output the delayed clock signal.

[0024] In some embodiments, the first delay unit in the delay chain has a specific signal connection. The first input of this delay unit directly receives the original clock signal from the clock source, which serves as the starting signal for the entire delay chain. The first output of the first delay unit serves as the final output of the entire digital delay-locked loop circuit, outputting the delayed clock signal processed by the delay chain. This connection method ensures that the original clock signal is accurately injected into the delay chain and guarantees that the processed clock signal can be output effectively.

[0025] Please see Figure 1 In some embodiments, for the last delay unit in the delay chain, its second output terminal and second input terminal are respectively used to be left floating and to receive high-level / low-level signals.

[0026] In some embodiments, the last delay unit in the delay chain also has a special signal connection. The second output of this delay unit is floating and not connected to any circuit node. The second input of this delay unit is fixedly connected to the power supply voltage or ground voltage, i.e., it continuously receives high-level or low-level signals. This connection method provides stable termination electrical characteristics for the delay chain, ensuring the integrity of signal transmission.

[0027] Please see Figure 1 In some embodiments, for any other delay unit in the delay chain, the first input, first output, second output, and second input of the delay unit are respectively connected to the second output of the previous delay unit, the second input of the previous delay unit, the first input of the next delay unit, and the first output of the next delay unit.

[0028] In some embodiments, for intermediate delay units in the delay chain (excluding the first and last units), each delay unit is connected to its adjacent delay unit, thus forming a complete signal path. The first input terminal of each delay unit is connected to the second output terminal of the previous delay unit, forming a signal transmission path. The first output terminal of each delay unit is connected to the second input terminal of the next delay unit, forming a signal transmission path. The second output terminal of each delay unit is connected to the first input terminal of the next delay unit, forming a signal transmission path. The second input terminal of each delay unit is connected to the first output terminal of the previous delay unit, completing the signal loop closure. This symmetrical interconnection structure ensures the orderly transmission of signals in the delay chain.

[0029] Please see Figure 2 In some embodiments, the delay unit 10 further includes a first logic gate circuit 20, a second logic gate circuit 30, and a third logic gate circuit 40. The first logic gate circuit 20, the second logic gate circuit 30, and the third logic gate circuit 40 can employ the same circuit structure but achieve specific signal processing functions through different connection methods. Each logic gate circuit has two circuit input terminals and one circuit output terminal, and these ports are connected to the external connection terminals and internal signal nodes of the delay unit in a specific manner.

[0030] Please see Figure 2 In some embodiments, the first logic gate 20 has two inputs and one output. One input of the first logic gate 20 can form a second control terminal for receiving a second control signal provided externally. The output of the first logic gate 20 can form a second output terminal, which transmits a signal to a lower-level delay unit or serves as an output for a specific mode.

[0031] Please see Figure 2 In some embodiments, the second logic gate 30 has two inputs and one output. One input of the second logic gate can form a first control terminal for receiving a first control signal provided externally. The other input of the second logic gate 30, together with the other input of the first logic gate 20, forms a first input terminal for receiving an input signal from a preceding delay unit or a clock source. The output of the second logic gate 30 is connected to the third logic gate 40 as an internal node.

[0032] Please see Figure 2 In some embodiments, the third logic gate 40 has two inputs and one output. One input of the third logic gate 40 forms a second input, which receives a feedback signal or a fixed level signal from a lower-level delay unit. The other input of the third logic gate 40 is connected to the output of the second logic gate 30 and receives a control signal generated by the second logic gate 30. The output of the third logic gate 40 forms a first output, which outputs the processed signal to a higher-level delay unit or as the final output.

[0033] Please see Figure 3 In some embodiments, the first logic gate 20, the second logic gate 30, and the third logic gate 40 are NAND gates. The NAND gates may include a first PMOS transistor (M1), a second PMOS transistor (M2), a first NMOS transistor (N1), and a second NMOS transistor (N2). The first and second PMOS transistors are of type SMIC_N28HKCPPMOS. The first and second NMOS transistors are of type SMIC_N28HKCPNMOS.

[0034] Please see Figure 3 In some embodiments, the gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form an input terminal.

[0035] In some embodiments, one input terminal of each NAND gate is formed by connecting the gates of a first PMOS transistor and a first NMOS transistor. This input terminal can receive other signals from outside or inside the delay unit 10, serving as an input signal source for the NAND gate. The signal at this input terminal simultaneously controls the conduction states of the first PMOS transistor and the first NMOS transistor, thereby affecting the level state of the output terminal.

[0036] Please see Figure 3 In some embodiments, the gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form another input terminal.

[0037] In some embodiments, the other input terminal of each NAND gate is formed by connecting the gates of a second PMOS transistor and a second NMOS transistor. This input terminal receives another control signal, which, together with the signal at the other input terminal, determines the output result. The combination of the two input signals will produce an output response that conforms to NAND logic.

[0038] Please see Figure 3 In some embodiments, the drains of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected to form an output terminal.

[0039] In some embodiments, the output of each NAND gate is formed by interconnecting the drains of a first PMOS transistor, a second PMOS transistor, and a first NMOS transistor. The output generates a signal after logical operation and transmits this signal to subsequent circuitry. The output level depends on the combination of the two input signals and the conduction status of the MOS transistors.

[0040] Please see Figure 3 In some embodiments, the source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the power supply (VDD).

[0041] In some embodiments, regarding power supply connections, the sources of the first and second PMOS transistors are respectively connected to a power supply to provide operating voltages for the PMOS transistors. This connection method ensures that the PMOS transistors can provide a high-level signal to the output terminal when the input conditions are met.

[0042] Please see Figure 3 In some embodiments, the source of the first NMOS transistor is connected to the drain of the second NMOS transistor; the source of the second NMOS transistor is grounded.

[0043] In some embodiments, regarding the grounding connection, the source of the second NMOS transistor is directly connected to ground potential (GND) to provide a current loop for the NMOS transistor. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor to form a series structure. This connection method ensures that the NMOS path will only be fully turned on when both input signals are high, thereby pulling the output terminal low.

[0044] In some embodiments, a first control signal and a second control signal for each delay unit 10 can be determined based on the delay duration of the clock signal. The delay unit 10 is used to selectively output the received clock signal from a first input terminal to a first output terminal or to a second output terminal based on the first control signal and the second control signal. Each delay unit 10 can selectively guide the received clock signal to different output paths according to the level combination of the received pair of control signals, thereby achieving precise delay control.

[0045] In some embodiments, when the first control signal is a low-level signal and the second control signal is a high-level signal, the delay unit 10 outputs the received clock signal to the second output terminal through the first input terminal.

[0046] In some embodiments, when the first control signal is a low-level signal and the second control signal is a high-level signal, the delay unit 10 enters a first operating mode. Under this level combination, the logic gate circuits inside the delay unit 10 generate corresponding control states, causing the clock signal received from the first input terminal to be guided to the second output terminal for output. The first operating mode can be used in scenarios where the signal is passed forward to the next delay unit, and the clock signal is passed to the next delay unit in the delay chain through the second output terminal, thereby continuing to propagate in the delay chain and accumulating delay.

[0047] In some embodiments, when the first control signal is a high-level signal and the second control signal is a low-level signal, the delay unit 10 outputs the received clock signal to the first output terminal through the first input terminal.

[0048] In some embodiments, when the first control signal is a high-level signal and the second control signal is a low-level signal, the delay unit 10 enters a second operating mode. Under this level combination, the logic gate circuit inside the delay unit 10 generates another control state, causing the clock signal received from the first input terminal to be guided to the first output terminal for output. The second operating mode can be used in signal output or feedback scenarios, where the clock signal is transmitted to the previous stage circuit through the first output terminal or used as the final output signal, thereby realizing a specific delay-locking function.

[0049] In some embodiments, when the first n delay units are selected to delay the clock signal in the delay chain, the delay chain receives n+1 sets of control signals, each corresponding to one of the n+1 delay units. The delay chain receives these n+1 sets of control signals to control the operating state of the n+1 delay units. These control signals are configured according to the required clock signal delay length. Each set of control signals includes two signals: a first control signal and a second control signal, which together determine the signal path selection for the corresponding delay unit.

[0050] In some embodiments, the first control signal and the second control signal in the first n-1 groups of control signals are low-level signals and high-level signals, respectively; the first n-1 delay units are used to output the received clock signal through their first input terminal to their second output terminal.

[0051] In some embodiments, the first n-1 groups of control signals employ the same control logic, i.e., the first control signal is a low-level signal and the second control signal is a high-level signal. Under this combination of control signals, the first n-1 delay units operate in the first operating mode, and each delay unit transmits the clock signal received at its first input terminal to the next delay unit through its second output terminal. In this way, the clock signal is transmitted sequentially in the first n-1 delay units, and each delay unit adds a certain delay time to the clock signal.

[0052] In some embodiments, the first control signal and the second control signal in the nth group of control signals are a high-level signal and a low-level signal, respectively; the nth delay unit is used to output the received clock signal through its first input terminal to its first output terminal.

[0053] In some embodiments, the nth group of control signals employs different control logics, with the first control signal being a high-level signal and the second control signal being a low-level signal. This signal combination causes the nth delay unit to operate in a second mode. The nth group of delay units outputs the clock signal received at its first input terminal through its first output terminal.

[0054] In some embodiments, the first control signal of the (n+1)th group of control signals is a high-level signal. The (n+1)th delay unit is used to receive the high-level signal of the second output terminal of the nth delay unit through its first input terminal, and output a high-level signal to the second input terminal of the nth delay unit in sequence through its second logic gate circuit, third logic gate circuit, and first output terminal.

[0055] In some embodiments, the first control signal of the (n+1)th group of control signals is a high-level signal, and the (n+1)th delay unit receives a high-level signal from the second output of the nth delay unit through its first input. This signal is processed sequentially through the second and third logic gates inside the (n+1)th delay unit, and finally outputs a high-level signal to the second input of the nth delay unit through its first output, forming a complete feedback path.

[0056] In some embodiments, the first n-1 delay units are further configured to output the returned clock signal to their first output via their second input.

[0057] In some embodiments, the first n-1 delay units are also used to pass the returned clock signal received at their second input to the next higher delay unit through their first output. This establishes a complete signal loop in the delay chain, allowing the clock signal to be transmitted cyclically within the delay chain, thereby achieving more precise delay control and clock synchronization.

[0058] In some embodiments, each NAND gate has a fixed signal propagation delay of 15 ps. This delay represents the time required for a signal to propagate from the input to the output of the logic gate, and is an inherent characteristic determined by the switching speed of the transistors and the circuit structure. The 15 ps delay of each NAND gate includes the total propagation delay required for the signal to pass through all internal transistors. Each delay unit contains multiple NAND gates cascaded in a specific manner, requiring the signal to pass through multiple NAND gates sequentially, resulting in a delay longer than that of a single NAND gate. The overall delay of each delay unit is 30 ps. This overall delay refers to the total time required for the signal to propagate from the input to the output of the delay unit.

[0059] This invention also discloses a memory that integrates a digital delay-locked loop (DLL) circuit as its timing control component to provide precise clock synchronization and timing control functions. The DLL circuit achieves precise delay adjustment of the clock signal through its delay chain, ensuring that the various functional modules within the memory can work collaboratively according to the correct timing relationships.

[0060] As can be seen, in the above scheme, the digital delay-locked loop circuit effectively overcomes the linearity and duty cycle distortion problems caused by the load variation of the multiplexer with the delay length in traditional digital DLLs through cascaded delay chains and a dual control signal control mechanism. Since the input and output loads of each delay unit are fixed and unaffected by the delay chain length, the uniformity and consistency of delay adjustment are guaranteed. Simultaneously, all signal paths are processed through structurally consistent delay units, avoiding the duty cycle degradation caused by uneven load in traditional schemes, and significantly improving data sampling accuracy.

[0061] The above embodiments are merely illustrative of the principles and effects of this utility model and are not intended to limit the scope of this utility model. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this utility model. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this utility model should still be covered by the claims of this utility model.

Claims

1. A digital delay-locked loop circuit, characterized in that, include: A delay chain consisting of multiple cascaded delay units; each delay unit has a first input terminal, a first output terminal, a second input terminal, a second output terminal, a first control terminal, and a second control terminal; The first control terminal and the second control terminal of each delay unit are used to receive the first control signal and the second control signal, respectively. For the first delay unit in the delay chain, its first input terminal and first output terminal are respectively used to receive the original clock signal and output the delayed clock signal; For the last delay unit in the delay chain, its second output terminal and second input terminal are respectively used to be left floating and to receive high-level / low-level signals; For any other delay unit in the delay chain, the first input, first output, second output, and second input of the delay unit are respectively connected to the second output, second input, first input, and first output of the previous delay unit; Specifically, the first control signal and the second control signal of each delay unit are determined according to the delay duration of the clock signal.

2. The digital delay-locked loop circuit according to claim 1, characterized in that, The delay unit includes: The first logic gate circuit has two input terminals and one output terminal, one of which forms the second control terminal and the output terminal forms the second output terminal; The second logic gate circuit has two input terminals and one output terminal. One of its input terminals forms the first control terminal, and the other input terminal and the other input terminal of the first logic gate circuit together form the first input terminal. The third logic gate has two inputs and one output. One of its inputs forms the second input, and the other input is connected to the output of the second logic gate. Its output forms the first output.

3. The digital delay-locked loop circuit according to claim 2, characterized in that, The first logic gate, the second logic gate, and the third logic gate are NAND gates.

4. The digital delay-locked loop circuit according to claim 3, characterized in that, The NAND gate circuit includes a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The gate of the first PMOS transistor is connected to the gate of the first NMOS transistor to form an input terminal; The gate of the second PMOS transistor is connected to the gate of the second NMOS transistor to form another input terminal; The drains of the first PMOS transistor, the second PMOS transistor, and the first NMOS transistor are connected to form an output terminal; The source of the first PMOS transistor and the source of the second PMOS transistor are respectively connected to the power supply. The source of the first NMOS transistor is connected to the drain of the second NMOS transistor; The source of the second NMOS transistor is grounded.

5. The digital delay-locked loop circuit according to claim 4, characterized in that, The first PMOS transistor and the second PMOS transistor are of model number SMIC_N28HKCPPMOS, and the first NMOS transistor and the second NMOS transistor are of model number SMIC_N28HKCPNMOS.

6. The digital delay-locked loop circuit according to claim 1, characterized in that, The delay unit is used to selectively output the received clock signal to the first output terminal or to the second output terminal through the first input terminal, based on the first control signal and the second control signal.

7. The digital delay-locked loop circuit according to claim 6, characterized in that, When the first control signal is a low-level signal and the second control signal is a high-level signal, the delay unit outputs the received clock signal to the second output terminal through the first input terminal; When the first control signal is a high-level signal and the second control signal is a low-level signal, the delay unit outputs the received clock signal to the first output terminal through the first input terminal.

8. The digital delay-locked loop circuit according to claim 7, characterized in that, In the delay chain, when the first n delay units are selected to delay the clock signal, the delay chain is used to receive n+1 sets of control signals, and the n+1 sets of control signals correspond to n+1 delay units; Among them, the first control signal and the second control signal in the first n-1 groups of control signals are low-level signals and high-level signals, respectively; the first n-1 delay units are used to output the received clock signal from its first input terminal to its second output terminal; The first control signal and the second control signal in the nth group of control signals are high-level signals and low-level signals, respectively; the nth delay unit is used to output the received clock signal from its first input terminal to its first output terminal; The first control signal of the (n+1)th group of control signals is a high-level signal. The (n+1)th delay unit is used to receive the high-level signal of the second output terminal of the nth delay unit through its first input terminal, and output a high-level signal to the second input terminal of the nth delay unit in sequence through its second logic gate circuit, third logic gate circuit, and first output terminal. The first n-1 delay units are also used to output the returned clock signal to its first output through its second input.

9. A memory, characterized in that, Includes the digital delay-locked loop circuit as described in any one of claims 1 to 8.

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