A phase-locked loop

Abstract

The application discloses a phase-locked loop, and particularly belongs to the technical field of phase-locked loops. In the phase-locked loop, a frequency discriminator and phase discriminator can realize a more high-speed and low-power working state, and effectively counteract the "dead zone effect", a charge pump can realize higher current matching precision, a wide output voltage range, and fast turn-off of a current tube, and cooperate with a digital control module to realize multi-gear output and non-linear adjustment of charging and discharging current, and a current source circuit and a band gap reference circuit therein can provide accurate and stable bias current and reference voltage for the phase-locked loop. The phase-locked loop can effectively eliminate the influence of non-ideal factors such as "dead zone effect", charge sharing and clock feedthrough on the charging and discharging current matching precision and the phase-locked loop noise, reduce the interference of ripple, stray and PVT characteristics on the output clock of the phase-locked loop, improve the overall phase noise level and reliability of the phase-locked loop, and can realize flexible adjustment of loop bandwidth, match different phase-locked stage requirements, and have a wider frequency adaptation range.

Description

Technical Field

[0001] This application relates to the field of phase-locked loop (PLL) technology, and in particular to a PLL. Background Technology

[0002] With the increasing demands for faster and more efficient data transmission and processing in today's information age, high-speed serial communication systems (SerDes) have become a core technology for achieving multi-standard and high-speed transmission, attracting widespread attention. Phase-locked loops (PLLs) are the core modules for clock generation and recovery, playing a crucial role in high-speed data transmission and directly determining the accuracy and reliability of data transmission.

[0003] As the speed of high-speed serial communication systems increases from 10Gbps to 56Gbps, 112Gbps, and even higher, more severe challenges are posed to the noise suppression capability, reliability, and wide frequency adaptability of the phase-locked loop (PLL) output clock. The mainstream charge pump PLL currently includes: a phase-frequency discriminator (PFD), a charge pump (CP), a loop filter (LPF), a voltage-controlled oscillator (VCO), and a frequency divider (DIV). Its working principle is that the PFD compares the phase difference between the input reference signal and the feedback signal output by the VCO, generates an error current signal in the CP, and obtains the control voltage after the error current signal is filtered by the LPF. The VCO adjusts its output frequency according to the change of the control voltage, and finally, the DIV reduces the frequency of the output feedback signal to close to the frequency of the input reference signal, thereby realizing the phase-locked loop phase locking.

[0004] The phase-frequency discriminator and charge pump, as core sub-modules in a phase-locked loop (PLL), generally work together. The phase-frequency discriminator converts the detected phase difference into charging and discharging current pulses via the charge pump. These charging and discharging current pulses require high matching accuracy. The matching accuracy and the "dead-zone effect" of the phase-frequency discriminator will have a cascading effect on the phase noise performance of the PLL. Furthermore, mismatch in the charging and discharging current pulses will produce unexpected jitter and spurious signals. Moreover, the loop bandwidth, phase margin, and other indicators of the PLL are related to various parameters such as the output current of the charge pump, the gain Kvco of the voltage-controlled oscillator, the capacitance and resistance values ​​of the loop filter, and the division ratio of the frequency divider. However, some parameters are difficult to adjust in a PLL system, resulting in a relatively fixed bandwidth. Therefore, the performance of the PLL will be affected when facing a wide range of input reference frequencies.

[0005] Furthermore, modern technology requires phase-locked loops (PLLs) to operate in more complex noise and deviation environments. This significantly affects the charging and discharging current matching accuracy and the overall noise and frequency stability of the PLL in terms of power supply, temperature, and process (PVT) fluctuations. As a result, auxiliary circuits are needed to provide stable and accurate bias voltage and current to the PLL to resist the interference of PVT characteristics on the reliability of the PLL frequency output.

[0006] While existing technologies have improved current matching accuracy, they are limited to specific output voltage ranges and lack reliability. The output charging and discharging currents are relatively fixed, and the loop bandwidth within the phase-locked loop (PLL) cannot be adaptively adjusted to meet demands. This makes it difficult to satisfy the noise and wide frequency adaptability requirements of modern high-speed SerDes systems. Therefore, for the mainstream charge pump PLL structure, achieving good noise performance and wide frequency adaptability while maintaining high system reliability is a practical problem in related technologies. This is especially true in high-speed SerDes applications, where a balance between low noise, reliability, and wide frequency adaptability of the overall PLL is urgently needed. Therefore, the development of a PLL to solve these problems is urgently required. Utility Model Content

[0007] In view of this, this application provides a phase-locked loop (PLL) that can effectively eliminate the "dead zone effect" in the frequency and phase detector and the impact of non-ideal factors such as clock feedthrough and charge sharing in the charge pump on the charging and discharging current matching accuracy and PLL noise. It reduces the interference of ripple, spurious signals, and PVT characteristics on the PLL output clock, improves the overall phase noise level and reliability of the PLL, and allows for flexible adjustment of the loop bandwidth by flexibly adjusting the charging and discharging current through the control word to match the requirements of different phase-locking stages. It has a wider frequency adaptation range and meets the requirements of low noise, reliability, and wide frequency adaptability of the PLL.

[0008] Specifically, the following technical solutions are included:

[0009] This application provides a phase-locked loop, the phase-locked loop comprising:

[0010] The frequency and phase detector includes input terminal 1, input terminal 2, pulse output terminal 1, and pulse output terminal 2. It is used to compare the frequency and phase of the reference clock CLK_REF and the feedback clock CLK_DIV, and output UP pulse signal and DN pulse signal. Input terminal 1 is connected to the reference clock CLK_REF, and input terminal 2 is connected to the feedback clock CLK_DIV.

[0011] The charge pump includes input terminals three, four, five, eight, and six. Input terminals three and four are connected to output terminals six and seven of the digital control module, respectively. Based on the PD control signal, the phase difference between the UP0, UP1, and UP2 pulse signals and the DN0, DN1, and DN2 pulse signals is converted into adjustable multi-channel charging and discharging current pulse signals Icpout0, Icpout1, and Icpout2, respectively.

[0012] The digital control module includes input terminals six, seven, nine, ten, eleven, and twelve, and output terminals six and seven. Input terminals six and seven are connected to pulse output terminals one and two of the frequency and phase detector, respectively. Output terminals six and seven are connected to input terminals three and four of the charge pump. Input terminals nine, ten, eleven, and twelve are connected to external control signals A0, A1, B0, and B1, respectively, and are used to determine the UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals based on the UP pulse signal, DN pulse signal, and external control signals, and control the on / off state of the current transistor in the charge pump.

[0013] The current source circuit includes input terminal thirteen, input terminal fourteen, and current output terminal. Input terminal thirteen is used to receive the external control signal Sel. <0> Input terminal fourteen is used to receive external control signal Sel <1> It is used to adjust and change the output reference current IDC. The current output terminal is connected to the input terminal 5 of the charge pump to input the reference current IDC to the charge pump.

[0014] In some embodiments, the frequency and phase detector includes an input buffer, a D flip-flop, a reset delay unit, and an output circuit.

[0015] The input buffer includes buffer1 and buffer2, the D flip-flop includes flip-flop D1 and flip-flop D2, the reset delay unit includes delay unit Delay and NAND gate, and the output circuit includes transmission gate TG1 and inverters INV1~INV7.

[0016] Buffers buffer1 and buffer2 are connected to the reference clock and feedback clock, respectively, to receive clock signals. The input CLK1 of flip-flop D1 is connected to the output of buffer1, and the input CLK2 of flip-flop D2 is connected to the output of buffer2. The output of flip-flop D1 generates signal A, which is connected to the input of inverter INV1 and the first input of NAND gate Nand. Signal A from flip-flop D1 passes through inverters INV1~INV4 to generate and output the UP pulse signal. The output of flip-flop D2 generates signal B, which is connected to the input of transmission gate TG1 and NAND gate Na. The second input terminals of Nand are all connected. The B signal output by flip-flop D2 passes through transmission gate TG1 and inverters INV5~INV7 to generate and output the DN pulse signal. The output terminal of Nand generates the C signal and connects to the input terminal of the delay unit Delay. The delay unit Delay delays the C signal and sends the resulting reset signal to the reset terminals Reset1 of flip-flop D1 and Reset2 of flip-flop D2. Inverters INV1~INV4 are connected in series, and transmission gate TG1 is connected in series with inverters INV5~INV7. The UP pulse signal is output by inverter INV4, and the DN pulse signal is output by inverter INV7.

[0017] In some embodiments, the charge pump includes a current bias circuit, a first operational amplifier circuit, a replication startup circuit, and a multiple current output circuit.

[0018] The bias circuit is connected to the first operational amplifier circuit and the replication startup circuit. It is used to control the input of the reference current IDC, replicate the reference current IDC, and generate a bias voltage VGS, providing a tail current source and bias voltage for the first operational amplifier circuit and the replication startup circuit. The first operational amplifier circuit is connected to the replication startup circuit and the multi-channel current output circuit. It uses high gain and clamping effect to enable current replication. The replication startup circuit is connected to both the first operational amplifier circuit and the multi-channel current output circuit. It is used to accelerate the current replication in the negative feedback loop of the first operational amplifier circuit and ensure smooth changes at the negative input terminal of the first operational amplifier. The multi-channel output current circuit is connected to the first operational amplifier circuit. It is used to cooperate with the digital control module to perform nonlinear adjustment of the charging and discharging current in the range of 50~150μA.

[0019] In some embodiments, the PD control signal includes a PDP control signal and a PDN control signal, in the charge pump:

[0020] The current bias circuit includes transistors M0 to M17. The drain of transistor M0 and the source of transistor M1 are connected to the current output terminal of the current source circuit to receive the reference current IDC. The gates of transistors M0 and M1 are used to receive the PDN control signal and PDP control signal, respectively. The source of transistor M0 and the drain of transistor M1 are connected to the drain of transistor M2. The drain of transistor M2 is connected to the gate of transistor M2. The source of transistor M2 is connected to the drain of transistor M4. The gate of transistor M5 is connected to the gate of transistor M3; the drain of transistor M5 is connected to the source of transistor M3; the drain of transistor M3 is connected to the drain of transistor M6; the drain of transistor M6 is connected to the gate of transistor M6; the gate of transistor M6 is connected to the gate of transistor M9; the drain of transistor M8 is connected to the source of transistor M9; the drain of transistor M9 is connected to the drain of transistor M10; the drain of transistor M10 is connected to the gate of transistor M10; and the source of transistor M10 is connected to the drain of transistor M11. The gate-to-drain connections of transistor M11 are as follows: the drain of transistor M11 is connected to the gate of transistor M11; the source of transistor M11 is connected to the drain of transistor M13; the gate of transistor M12 is connected to the gate of transistor M11; the source of transistor M12 is connected to the drain of transistor M14; the drain of transistor M12 is connected to the drain of transistor M15; the source of transistor M15 is connected to the drain of transistor M16; the source of transistor M16 is connected to the drain of transistor M17; and the gate of transistor M15 is connected to the drain of transistor M18. The gates of transistors M16 and M17 are connected. The gates of transistors M4, M5, M7, M8, M13, M14, and M17 are connected to the power supply terminal VDD. The sources of transistors M4, M5, M13, M14, M7, M8, and M17 are connected to the common terminal GND.

[0021] The first operational amplifier circuit includes transistors M18 to M33. The drain of transistor M18 is connected to the source of transistor M20, the drain of transistor M20 is connected to the gate of transistor M20, the drain of transistor M20 is connected to the drain of transistor M22, the gate of transistor M22 is connected to node CN, the drain of transistor M19 is connected to the source of transistor M21, the gate of transistor M21 is connected to the gate of transistor M20, and the drain of transistor M21 is connected to the drain of transistor M23. The gate of transistor M23 is connected to the output node Icp of the charge pump, and current pulse signals Icpout0, Icpout1, and Icpout2 are output from the output node Icp. The source of transistor M22 is connected to the source of transistor M23 and the drain of transistor M24. The gate of transistor M24 is connected to the gate of transistor M12. The source of transistor M24 is connected to the drain of transistor M25. The drain of transistor M26 is connected to the source of transistor M27. The gate of transistor M27 is connected to the gate and drain of transistor M16. The drain of transistor M27 is connected to the source of transistors M28 and M29. The gate of transistor M28 is connected to node CN. The gate of transistor M29 is connected to the output node Icp of the charge pump. The drains of transistors M28 and M29 are connected to the drains of transistors M30 and M31, respectively. The drain of transistor M30 is connected to the gate of transistor M30. The source of transistor M30... The source of transistor M31 is connected to the drain of transistor M32 and the drain of transistor M33, respectively. The source of transistor M18, the source of transistor M19, the gate of transistor M25, the source of transistor M26, the gate of transistor M32, and the gate of transistor M33 are connected to the power supply terminal VDD. The gate of transistor M18, the gate of transistor M19, the source of transistor M25, the gate of transistor M26, the source of transistor M32, and the source of transistor M33 are connected to the common terminal GND.

[0022] The replication startup circuit includes transistors M34 to M45. The drain of transistor M34 is connected to the source of transistor M35. The drain of transistor M35 is connected to the gate of transistor M35, the source of transistor M36, and the drain of transistor M21. The gate of transistor M36 is connected to the gate and drain of transistor M15. The drain of transistor M36, the source of transistor M37, and the drain of transistor M38 are connected. The drain of transistor M38 is connected to the gate of transistor M38 and the drain of transistor M31. The source of transistor M38 is connected to the drain of transistor M39. The drain of transistor M40 is connected to the source of transistor M41. The gate of transistor M41 is connected to the drain of transistor M35 and the drain of transistor M42. The gates of transistors M41 and M43 are connected, and one end of capacitor C1 is connected to node CN. The gate of transistor M43 is connected to the gate of transistor M45 and the drain of transistor M38. The source of transistor M43 is connected to the drain of transistor M44. The source of transistor M44 is connected to the source and drain of transistor M45. The gates of transistors M39, M44, M34, M42, and M40 are connected to the power supply terminal VDD. The gates of transistors M34 and M40, the other end of capacitor C1, the source of transistor M39, M45, and M44 are connected to the common terminal GND.

[0023] The multi-channel current output circuit includes three current output circuits, which are used to generate charging and discharging current pulse signals Icpout0, Icpout1, and Icpout2 based on the phase difference between UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals. The UP0 pulse signal is input to the gates of transistors M46 and Ndummy1, the UP1 pulse signal is input to the gates of transistors M50 and Ndummy2, the UP2 pulse signal is input to the gates of transistors M54 and Ndummy3, the DN0 pulse signal is input to the gates of transistors M49 and Pdummy1, the DN1 pulse signal is input to the gates of transistors M53 and Ndummy2, and the DN2 pulse signal is input to the gates of transistors M57 and Pdummy3.

[0024] The first current output circuit includes transistors M46~M49, transistor Ndummy1, and transistor Pdummy1. The gate of transistor M46 is connected to the gate of transistor Ndummy1. The gates of transistor M46 and Ndummy1 are used to receive the UP0 pulse signal. The gates of transistor M49 and Pdummy1 are used to receive the DN0 pulse signal. The drain of transistor M46 is connected to the drain of transistor Ndummy1 and the source of transistor M47. The drain of transistor M47 and the drain of transistor M48 are connected to the output node Icp of the charge pump. The gate of transistor M47 is connected to the gate of transistor M41. The gate of transistor M48 is connected to the gate of transistor M43. The source of transistor M48 is connected to the drain of transistor Pdummy1. The drain of transistor M49 is connected. The gate of transistor M49 is connected to the gate of transistor Pdummy1. The source of transistor M46... The source of transistor Pdummy1 is connected to the power supply terminal VDD, and the sources of transistor Ndummy1 and transistor M49 are connected to the common terminal GND. The second current output circuit includes transistors M50~M53, transistor Ndummy2, and transistor Pdummy2. The gates of transistor M50 and Ndummy2 are used to receive the UP1 pulse signal, and the gates of transistor M53 and Pdummy2 are used to receive the DN1 pulse signal. The third current output circuit includes transistors M54~M57, transistor Ndummy3, and Pdummy3. The gates of transistor M54 and Ndummy3 are used to receive the UP2 pulse signal, and the gates of transistor M57 and Pdummy3 are used to receive the DN2 pulse signal. The circuit structures of the second and third current output circuits are the same as those of the first current output circuit.

[0025] Transistors M0, M2~M5, M10~M14, M22~M25, M30~M33, M37~M39, M43~M45, M48~M49, M52~M53, M56~M57, and Ndummy1~Ndummy3 are NMOS type, while transistors M1, M6~M9, M15~M21, M26~M29, M34~M36, M40~M42, M46~M47, M50~M51, M54~M55, and Pdummy1~Pdummy3 are PMOS type.

[0026] In some embodiments, the current source circuit includes a bandgap reference circuit, a current replication circuit, and a current output circuit;

[0027] The bandgap reference circuit is connected to the current replication circuit to provide the voltage at the reference voltage node VREF generated by the low bandgap reference circuit to the current replication circuit.

[0028] The current replication circuit is connected to the current output circuit. It is used to clamp the voltage at the reference voltage node VREF to the resistor R6 to obtain the required current IR, and then replicate it as a current Iref to transmit to the current output circuit.

[0029] The current output circuit is connected to the current replication circuit and is used to output an adjustable reference current IDC based on the input current Iref to provide bias current for the charge pump circuit.

[0030] In some embodiments, in the current source circuit:

[0031] The bandgap reference circuit includes a bias circuit, a fast start-up circuit, and a core circuit.

[0032] The bias circuit is connected to the core circuit and the fast start circuit to provide a precise and stable bias current at node i_opa of the core circuit.

[0033] The fast-start circuit is connected to the core circuit and is used to provide temporary start-up current when the circuit starts up, thereby speeding up the state response;

[0034] The core circuit is connected to the fast start-up circuit and the bias circuit. By utilizing the high-gain operational amplifier OPA1 inside the core circuit, the bias circuit provides a stable bias current at node i_opa, the fast start-up circuit provides the start-up current, and the input power supply voltage VDD, a temperature-independent reference voltage at node VREF is generated.

[0035] In some embodiments, in a bandgap reference circuit:

[0036] The bias circuit includes resistors R0 and R1, transistor pnp1, PMOS transistors M66~M67, and NMOS transistors M58~M62.

[0037] Transistors M58, M59, M66, and M67 form a current mirror structure. One end of resistor R0 is connected to the drain and gate of transistor M58. The gate of transistor M58 is connected to the gate of transistor M59. The source of transistor M58 is connected to the emitter of transistor PNP1. The source of transistor M59 is connected to one end of resistor R1. The drain of transistor M59 is connected to the drain of transistor M66. The drain and gate of transistor M66 are connected. The gate of transistor M67 is connected to the gate of transistor M66. The drain of transistor M67 is connected to the drain of transistor M60, the gate of transistor M60 is connected to the drain, the gates of transistors M61 and M62 are connected to the gate of transistor M60, the drain of transistor M62 is connected to node i_opa, the other end of resistor R0, the source of transistor M66, and the source of transistor M67 are connected to the power supply terminal VDD, the base and collector of transistor pnp1, the other end of resistor R1, the source of transistor M60, the source of transistor M61, and the source of transistor M62 are connected to the common terminal GND;

[0038] The fast-start circuit includes PMOS type transistors M68~M72; the gate and drain of transistor M68 are connected, the gate of transistor M69 is connected to the gate of M68, the gate of transistor M70 is connected to the gate of transistor M68, the drain of transistor M68 is connected to the drain of transistor M61, the drain of transistor M69 is connected to node Vn via one end of resistor R2 in the core circuit, the drain of transistor M70 is connected to node Vp via one end of resistor R4 in the core circuit, the drain of transistor M71 is connected to the source of transistor M72, the drain of transistor M72 is connected to node C via the drain of transistor M68, and the sources of transistors M68, M69, M70, and M71 are connected to the power supply terminal VDD;

[0039] The core circuit includes PMOS transistors M73~M80, NMOS transistors M63~M65, resistors R2, R3, R4, and R5, transistors PNP2 and PNP3, capacitor C1, and operational amplifier OPA1. The current input terminal of OPA1 provides the bias current at node i_opa. The gates of transistors M73, M75, M77, and M79, the output terminal of OPA1, and the gate of transistor M71 are connected to node Vp1. The drain of transistor M73 is connected to the source of transistor M74, the drain of transistor M75 is connected to the source of transistor M76, and the drain of transistor M77 is connected to the source of transistor M78. The gates of transistors M74, M76, and M78, one end of capacitor C1, and the gate of transistor M72 are connected to node Vp2. The negative input terminal of operational amplifier OPA1 and the drain of transistor M74 are connected to node Vn, and the positive input terminal of operational amplifier OPA1 and the drain of transistor M76 are connected to node Vp. One end of resistor R2 is connected to the transistor... The emitter of transistor PNP2 is connected to node Vn. One end of resistor R3 and one end of resistor R4 are connected to node Vp. The other end of resistor R3 is connected to the emitter of transistor PNP3. The drain of transistor M78 and one end of resistor R5 are connected to the reference voltage node VREF. The gate of transistor M65 is connected to the reference voltage node VREF. The drain of transistor M79 is connected to the drain of transistor M63. The gate and drain of transistor M63 are connected. The gate of transistor M64 is connected to the gate of transistor M63. The drain of transistor M64 is connected to the gate of transistor M80. The drain and gate of transistor M80 are connected to node Vp2. The other end of capacitor C1, the source of transistor M73, the source of transistor M75, the source of transistor M77, the source of transistor M79, and the source of transistor M80 are connected to the power supply terminal VDD. The other end of resistor R2, the base and collector of transistor pnp2, the base and collector of transistor pnp3, the other end of resistor R4, the other end of resistor R5, the source and drain of transistor M65, the source of transistor M63, and the source of transistor M64 are connected to the common terminal GND.

[0040] In some embodiments, in the current source circuit:

[0041] The current replication circuit includes operational amplifier OPA2, transistors M81~M87, and resistor R6. The reference voltage generated by the bandgap reference circuit at node VREF is connected to the positive input terminal of operational amplifier OPA2. The negative input terminal of operational amplifier OPA2 is connected to the source of transistor M85, and one end of resistor R6 is connected to node F. The output terminal of operational amplifier OPA2 is connected to the gate of transistor M85. The drain of transistor M85, along with the drain and gate of transistors M81, M82, and M84, are connected to node K. The drain of transistor M82 is connected to the drain and gate of transistor M86. The gate of transistor M87 is connected to the gate of transistor M86. The drain of transistor M87, along with the drain of transistor M84 and the gate of transistor M83, are connected to node L. The source of transistor M84... The drain of transistor M83 is connected to the power supply terminal VDD. The sources of transistors M81, M82, and M83, along with the other end of resistor R6, are connected to the common terminal GND. The current output circuit includes transistors M88 to M93. The gates of transistors M88 and M89 are connected to node L. The drain of transistor M88 is connected to the source of transistor M90, and the drain of transistor M89 is connected to the source of transistor M91. The gates of transistors M90 and M91 are connected to the gate of transistor M84. The drain of transistor M90 is connected to the drain of transistor M92, and the drain of transistor M91 is connected to the drain of transistor M93. The gate of transistor M92 is used to receive the external control signal Sel. <0> The gate of transistor M93 is used to receive the external control signal Sel. <1> The source of transistor M88 and the source of transistor M89 are connected to the power supply terminal VDD, and the source of transistor M92 and the source of transistor M93 are connected to the output reference current IDC.

[0042] In some embodiments, the digital control module includes a UP digital control circuit and a DN digital control circuit. The UP digital control circuit is used to input UP0 pulse signals, UP1 pulse signals, and UP2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump, so as to control the on and off of each pull-up current transistor. The DN digital control circuit is used to input DN0 pulse signals, DN1 pulse signals, and DN2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump, so as to control the on and off of each pull-down current transistor.

[0043] The beneficial effects of the technical solutions provided in this application include at least the following:

[0044] This application provides a phase-locked loop (PLL) in which the frequency and phase detector can achieve higher speed and lower power consumption, and effectively offset the "dead zone effect". The charge pump can achieve higher current matching accuracy, a wide output voltage range, and fast turn-off of the current tube. It works with the digital control module to achieve multi-level output of charging and discharging current and nonlinear adjustment. The current source circuit and its bandgap reference circuit can provide the PLL with accurate and stable bias current and reference voltage. This PLL can effectively eliminate the impact of non-ideal factors such as the "dead zone effect", charge sharing, and clock feedthrough on the charging and discharging current matching accuracy and PLL noise. It reduces the interference of ripple, spurious emissions, and PVT characteristics on the PLL output clock, improves the overall phase noise level and reliability of the PLL, and can achieve flexible adjustment of the loop bandwidth to match the requirements of different phase-locking stages, with a wider frequency adaptation range. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic structural diagram of a phase-locked loop provided in an embodiment of this application.

[0047] Figure 2 This is a schematic diagram of the structure of a phase-locked loop frequency detector provided in an embodiment of this application.

[0048] Figure 3 This is a schematic diagram of the structure of a D flip-flop in a phase-locked loop provided in an embodiment of this application.

[0049] Figure 4 This is a schematic diagram of the structure of a charge pump in a phase-locked loop provided in an embodiment of this application.

[0050] Figure 5 This is a schematic diagram of a current source circuit in a phase-locked loop provided in an embodiment of this application.

[0051] Figure 6 This is a schematic diagram of the structure of a bandgap reference circuit in a phase-locked loop provided in an embodiment of this application.

[0052] Figure 7 Simulation results of the input and output signals of a phase-locked loop frequency and phase detector provided in an embodiment of this application.

[0053] Figure 8The simulation results of the operating swing voltage range and static charge / discharge current mismatch of a charge pump in a phase-locked loop under PVT are provided for the embodiments of this application.

[0054] Figure 9 The simulation results show the output reference voltage variation with temperature under different process angles and power supply voltages in a bandgap reference circuit in a phase-locked loop provided in this application embodiment.

[0055] Figure 10 The simulation results of the cascaded output noise of a phase-locked loop circuit consisting of a frequency and phase detector, a digital control module, a charge pump, and a current source under different PVT conditions are provided in the embodiments of this application.

[0056] Figure 11(a) shows the simulation results of dynamic charging of the control voltage Vctrl under the cascaded circuit of frequency and phase detector, digital control module, charge pump and current source circuit in a phase-locked loop provided in the embodiment of this application.

[0057] Figure 11(b) shows the simulation results of dynamic discharge of control voltage Vctrl in a phase-locked loop with cascaded frequency and phase detector, digital control module, charge pump and current source circuit provided in the embodiment of this application.

[0058] Figure 12 This is a schematic diagram of the structure of the DN digital control circuit in the digital control module of a phase-locked loop, provided in an embodiment of this application.

[0059] Figure 13 This is a schematic diagram of the structure of the UP digital control circuit in the digital control module of a phase-locked loop provided in an embodiment of this application. Detailed Implementation

[0060] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0061] To make the technical solutions and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0062] This application provides a phase-locked loop, such as Figure 1 As shown, the phase-locked loop includes:

[0063] The frequency and phase detector includes input terminal 1, input terminal 2, pulse output terminal 1, and pulse output terminal 2. It is used to compare the frequency and phase of the reference clock CLK_REF and the feedback clock CLK_DIV, and output UP pulse signal and DN pulse signal. Input terminal 1 is connected to the reference clock CLK_REF, and input terminal 2 is connected to the feedback clock CLK_DIV.

[0064] The charge pump includes input terminals three, four, five, and eight, and output terminal six. Input terminals three and four are connected to output terminals six and seven of the digital control module, respectively. Based on the PD control signal, the pump converts the phase difference between the UP0, UP1, and UP2 pulse signals and the DN0, DN1, and DN2 pulse signals into adjustable multi-channel charging and discharging current pulse signals Icpout0, Icpout1, and Icpout2, respectively.

[0065] The digital control module includes input terminals six, seven, nine, ten, eleven, and twelve, and output terminals six and seven. Input terminals six and seven are connected to pulse output terminals one and two of the frequency and phase detector, respectively. Output terminals six and seven are connected to input terminals three and four of the charge pump. Input terminals nine, ten, eleven, and twelve are connected to external control signals A0, A1, B0, and B1, respectively, and are used to determine the UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals based on the UP pulse signal, DN pulse signal, and external control signals, and control the on / off state of the current transistor in the charge pump.

[0066] The current source circuit includes input terminal thirteen, input terminal fourteen, and current output terminal. Input terminal thirteen is used to receive the external control signal Sel. <0> Input terminal fourteen is used to receive external control signal Sel <1> It is used to adjust and change the output reference current IDC. The current output terminal is connected to the input terminal 5 of the charge pump to input the reference current IDC to the charge pump.

[0067] In summary, the phase-locked loop (PLL) provided in this application embodiment can achieve higher speed and lower power consumption operation with the frequency and phase detector, and effectively offset the "dead zone effect". The charge pump can achieve high current matching accuracy, wide output voltage range and fast turn-off of the current tube. It can also work with the digital control module to achieve multi-level output of charging and discharging current and nonlinear adjustment. The current source circuit and its bandgap reference circuit can provide the PLL with accurate and stable bias current and reference voltage. This PLL can effectively eliminate the impact of non-ideal factors such as "dead zone effect", charge sharing and clock feedthrough on the charging and discharging current matching accuracy and PLL noise, reduce the interference of ripple, spurious and PVT characteristics on the PLL output clock, improve the overall phase noise level and reliability of the PLL, and realize flexible adjustment of loop bandwidth to match the requirements of different phase-locking stages, with a wider frequency adaptation range.

[0068] In some embodiments, such as Figure 2 As shown, the frequency and phase detector includes an input buffer, a D flip-flop, a reset delay unit, and an output circuit.

[0069] The input buffer includes buffer1 and buffer2, the D flip-flop includes flip-flop D1 and flip-flop D2, the reset delay unit includes delay unit Delay and NAND gate, and the output circuit includes transmission gate TG1 and inverters INV1~INV7.

[0070] Buffers buffer1 and buffer2 are connected to the reference clock and feedback clock, respectively, to receive clock signals. The input CLK1 of flip-flop D1 is connected to the output of buffer1, and the input CLK2 of flip-flop D2 is connected to the output of buffer2. The output of flip-flop D1 generates signal A, which is connected to the input of inverter INV1 and the first input of NAND gate Nand. Signal A from flip-flop D1 passes through inverters INV1~INV4 to generate and output the UP pulse signal. The output of flip-flop D2 generates signal B, which is connected to the input of transmission gate TG1 and NAND gate Na. The second input terminals of Nand are all connected. The B signal output by flip-flop D2 passes through transmission gate TG1 and inverters INV5~INV7 to generate and output the DN pulse signal. The output terminal of Nand generates the C signal and connects to the input terminal of the delay unit Delay. The delay unit Delay delays the C signal and sends the resulting reset signal to the reset terminals Reset1 of flip-flop D1 and Reset2 of flip-flop D2. Inverters INV1~INV4 are connected in series, and transmission gate TG1 is connected in series with inverters INV5~INV7. The UP pulse signal is output by inverter INV4, and the DN pulse signal is output by inverter INV7.

[0071] like Figure 3As shown, the D flip-flops in the frequency and phase discriminator are suitable for a 100MHz high-speed clock reference signal and employ an optimized true single-phase clock (TSPC) structure. The input CLK1 of flip-flop D1 is connected to the output of buffer1 to receive the shaped reference clock CLK_REF; the input CLK2 of flip-flop D2 is connected to the output of buffer2 to receive the shaped feedback clock CLK_DIV. The output of flip-flop D1 is connected to the input of inverter INV1 and the first input of NAND gate Nand, generating signal A and ultimately outputting the UP pulse signal; the output of flip-flop D2 is connected to the input of transmission gate TG1 and the second input of NAND gate Nand, generating signal B and ultimately outputting the DN pulse signal.

[0072] The reset delay unit generates a reset signal based on the input signals A and B, which is then provided to the reset input terminals of flip-flops D1 and D2. By adding a delay unit Delay, when the phase-locked loop (PLL) is locked, the delay unit Delay ensures that the output signals of the two NAND gates operate simultaneously for a period of time. The parameters of the delay unit Delay are selected so that its reset delay time is just enough to activate the switch in the charge pump. The output terminal of the NAND gate is connected to the input terminal of the delay unit Delay to generate a C signal. The delay unit Delay then delays the C signal to obtain the reset signal, which is sent to the reset terminals Reset1 and Reset2 of flip-flops D1 and D2, thus completing the entire process of one cycle of the input signal. The reset delay unit introduces an inverter delay unit and an improved NAND gate structure. The delay uses a four-stage cascaded inverter structure to amplify the reset pulse signal, ensuring that the reset signal can completely turn off the two D flip-flops and that the UP and DN pulse signals have sufficient time to trigger and cancel the "dead-time effect". The improved NAND gate employs a symmetrical layout to ensure that the arrival times of input signals A and B at the Q terminals of the two output flip-flops are approximately the same, thus avoiding discrepancies in the arrival times of the two D flip-flops at the reset terminal, which would affect circuit performance. Input buffers buffer1 and buffer2 transmit the input reference clock CLK_REF and feedback clock CLK_DIV to the input terminals CLK1 of flip-flop D1 and CLK2 of flip-flop D2, respectively. These buffers isolate and enhance the high-speed reference and feedback clock signals. The output circuit of the frequency and phase discriminator has two pulse output terminals: one composed of four cascaded inverters, and the other composed of a transmission gate TG1 and a three-stage inverter. Their inputs and outputs are connected sequentially to enhance signal driving capability. The transmission gate TG1 and inverter INV1 are used to match the delay times of the D flip-flop output signals to pulse output terminals one and two, reducing the time error between the arrival times of signals A and B at the output terminals.

[0073] In some embodiments, such as Figure 3As shown, a single-phase clock D flip-flop can be composed of eight MOS transistors. When both the reset signal Reset and the input clock signal CLK are low, PMOS transistors PM1 and PM2 will conduct, and NM1 will be cut off. This charges node S0 to a high level, while node S1 and the output are in an indeterminate state. In the next clock cycle, when the rising edge of CLK arrives, NMOS transistors NM4 and NM2 will conduct simultaneously, pulling node S1 low and setting the output Q to a high level. When Reset is high, node S0 is pulled low to ground, PM3 will conduct, node S1 will rise to a high level, and the output Q will be low. This true single-phase clock D flip-flop has three operating states. When the reset signal Reset is high, all outputs are forced low, a state known as asynchronous data reset. When the clock signal CLK is low, the reset signal and node S0 are high, and node S1 is low, output node Q is high, maintaining the previously stored state, a state known as data hold. When the rising edge of the clock signal CLK arrives, the reset signal and node S1 are low, node S0 is high, and output node Q is high, the output is set high, a state known as data set. Furthermore, this circuit has only three branches from the power supply voltage to ground, significantly reducing power consumption and making it more suitable for high-speed clock signals.

[0074] In some embodiments, such as Figure 4 As shown, the charge pump includes a current bias circuit, a first operational amplifier circuit, a replication startup circuit, and a multi-channel current output circuit.

[0075] The bias circuit is connected to the first operational amplifier circuit and the replication startup circuit. It controls the input of the reference current IDC, replicates the reference current IDC, and generates a bias voltage VGS, providing a tail current source and bias voltage for the first operational amplifier circuit and the replication startup circuit. The first operational amplifier circuit is connected to the replication startup circuit and the multi-channel current output circuit. It uses high gain and clamping effect to enable current replication. The replication startup circuit is connected to both the first operational amplifier circuit and the multi-channel current output circuit. It is used to accelerate the current replication in the negative feedback loop of the first operational amplifier circuit and ensure smooth changes at the negative input terminal of the first operational amplifier. The multi-channel output current circuit is connected to the first operational amplifier circuit. It is used to cooperate with the digital control module to perform nonlinear adjustment of the charging and discharging current in the range of 50~150μA, so as to flexibly adjust the overall loop bandwidth of the phase-locked loop, match the requirements of different phase-locked stages, and broaden the frequency adaptation range of the phase-locked loop.

[0076] In some embodiments, such as Figure 4 As shown, the PD control signal includes the PDP control signal and the PDN control signal in the charge pump:

[0077] The current bias circuit includes transistors M0 to M17. The drain of transistor M0 and the source of transistor M1 are connected to the current output terminal of the current source circuit to receive the reference current IDC. The gates of transistors M0 and M1 are used to receive the PDN control signal and PDP control signal, respectively. The source of transistor M0 and the drain of transistor M1 are connected to the drain of transistor M2. The drain of transistor M2 is connected to the gate of transistor M2. The source of transistor M2 is connected to the drain of transistor M4. The gate of transistor M5 is connected to the gate of transistor M3; the drain of transistor M5 is connected to the source of transistor M3; the drain of transistor M3 is connected to the drain of transistor M6; the drain of transistor M6 is connected to the gate of transistor M6; the gate of transistor M6 is connected to the gate of transistor M9; the drain of transistor M8 is connected to the source of transistor M9; the drain of transistor M9 is connected to the drain of transistor M10; the drain of transistor M10 is connected to the gate of transistor M10; and the source of transistor M10 is connected to the drain of transistor M11. The gate-to-drain connections of transistor M11 are as follows: the drain of transistor M11 is connected to the gate of transistor M11; the source of transistor M11 is connected to the drain of transistor M13; the gate of transistor M12 is connected to the gate of transistor M11; the source of transistor M12 is connected to the drain of transistor M14; the drain of transistor M12 is connected to the drain of transistor M15; the source of transistor M15 is connected to the drain of transistor M16; the source of transistor M16 is connected to the drain of transistor M17; and the gate of transistor M15 is connected to the drain of transistor M18. The gates of transistors M16 and M17 are connected. The gates of transistors M4, M5, M7, M8, M13, M14, and M17 are connected to the power supply terminal VDD. The sources of transistors M4, M5, M13, M14, M7, M8, and M17 are connected to the common terminal GND. The current biasing circuit in the charge pump consists of transmission gates M0 and M1 with switches, selectively directing the input reference current IDC into the charge pump. Then, transistors M2 and M6 mirror the current to the third branch. Transistors M10, M11, M15, and M16 are self-biased MOSFETs used to generate a suitable bias voltage VGS, which biases the tail current source of the operational amplifier, ensuring its normal operation. Furthermore, switching matching transistors such as transistors M7, M8, M4, M5, M13, M14, and M25 were added to each branch to ensure the compatibility of each branch with the layout implementation.

[0078] The first operational amplifier circuit includes transistors M18 to M33. The drain of transistor M18 is connected to the source of transistor M20, the drain of transistor M20 is connected to the gate of transistor M20, the drain of transistor M20 is related to the drain of transistor M22, the gate of transistor M22 is connected to node CN, the drain of transistor M19 is connected to the source of transistor M21, the gate of transistor M21 is connected to the gate of transistor M20, the drain of transistor M21 is connected to the drain of transistor M23, and transistor M23... The gate of transistor M22 is connected to the output node Icp of the charge pump. Current pulse signals Icpout0, Icpout1, and Icpout2 are output from Icp. The source of transistor M22 is connected to the source of transistor M23 and the drain of transistor M24. The gate of transistor M24 is connected to the gate of transistor M12. The source of transistor M24 is connected to the drain of transistor M25. The drain of transistor M26 is connected to the source of transistor M27. The gate of transistor M27 is connected to the gate and drain of transistor M16. The drain of transistor M27 is connected to the source of transistors M28 and M29. The gate of transistor M28 is connected to the negative input terminal CN of the first operational amplifier circuit. The gate of transistor M29 is connected to the output node Icp of the charge pump. The drains of transistors M28 and M29 are connected to the drains of transistors M30 and M31, respectively. The drain of transistor M30 is connected to the gate of transistor M30. The source of transistor M31 is connected to the drain of transistor M32 and the drain of transistor M33, respectively. The source of transistor M18, the source of transistor M19, the gate of transistor M25, the source of transistor M26, the gate of transistor M32, and the gate of transistor M33 are connected to the power supply terminal VDD. The gate of transistor M18, the gate of transistor M19, the source of transistor M25, the gate of transistor M26, the source of transistor M32, and the source of transistor M33 are connected to the common terminal GND.

[0079] The replication startup circuit includes transistors M34 to M45. The drain of transistor M34 is connected to the source of transistor M35. The drain of transistor M35 is connected to the gate of transistor M35, the source of transistor M36, and the drain of transistor M21. The gate of transistor M36 is connected to the gate and drain of transistor M15. The drain of transistor M36, the source of transistor M37, and the drain of transistor M38 are connected. The drain of transistor M38 is connected to the gate of transistor M38 and the drain of transistor M31. The source of transistor M38 is connected to the drain of transistor M39. The drain of transistor M40 is connected to the source of transistor M41. The gate of transistor M41 is connected to the drain of transistor M35 and the drain of transistor M42. The gates of transistors M41 and M43 are connected, and one end of capacitor C1 is connected to node CN. The gate of transistor M43 is connected to the gate of transistor M45 and the drain of transistor M38. The source of transistor M43 is connected to the drain of transistor M44. The source of transistor M44 is connected to the drain of transistor M45. The gates of transistors M39, M44, M34, M42, and M40 are connected to the power supply terminal VDD. The gates of transistors M34 and M40, the other end of capacitor C1, the source of transistor M39, M45, and M44 are connected to the common terminal GND.

[0080] The replication startup circuit in the charge pump consists of transistors M35 to M38. The drain terminals of transistors M36 and M37 are directly connected to the gate of the output current source, and in the initial stage, transistors M36 and M37 are in the conducting state. When the voltage at point X is less than VGS, M36 charges point X. When the voltage reaches VGS, transistor M38 starts to conduct, and continues to charge point X. As the voltage at point X increases, the leakage current of M38 also increases until the charging current of M36 equals the discharging current of M38, at which point X stabilizes. The same applies to point Y. Thus, the charging and discharging of points X and Y ensures the rapid normal operation of the operational amplifier and the loop. In addition, the function of capacitor C1 is to prevent sudden changes in the voltage at node CN, ensuring a smooth change at the negative input terminal of the operational amplifier.

[0081] The multi-channel current output circuit includes three current output circuits, which work in conjunction with the UP0~UP2 pulse signals and DN0~DN2 pulse signals generated by the digital control module to output a non-linearly adjustable charging and discharging current in the range of 50~150μA. This satisfies the requirements for adjusting the overall loop bandwidth of the phase-locked loop, matches the requirements of different phase-locked stages, and widens the frequency adaptation range of the phase-locked loop. Specifically, the UP0 pulse signal is input to the gates of transistors M46 and Ndummy1, the UP1 pulse signal is input to the gates of transistors M50 and Ndummy2, the UP2 pulse signal is input to the gates of transistors M54 and Ndummy3, the DN0 pulse signal is input to the gates of transistors M49 and Pdummy1, the DN1 pulse signal is input to the gates of transistors M53 and Ndummy2, and the DN2 pulse signal is input to the gates of transistors M57 and Pdummy3.

[0082] The first current output circuit includes transistors M46~M49, transistor Ndummy1, and transistor Pdummy1. The gate of transistor M46 is connected to the gate of transistor Ndummy1. The gates of transistor M46 and Ndummy1 are used to receive the UP0 pulse signal. The gates of transistor M49 and Pdummy1 are used to receive the DN0 pulse signal. The drain of transistor M46 is connected to the drain of transistor Ndummy1 and the source of transistor M47. The drain of transistor M47 and the drain of transistor M48 are connected to the output node Icp of the charge pump. The gate of transistor M47 is connected to the gate of transistor M41. The gate of transistor M48 is connected to the gate of transistor M43. The source of transistor M48 is connected to the drain of transistor Pdummy1. The drain of transistor M49 is connected. The gate of transistor M49 is connected to the gate of transistor Pdummy1. The gate of transistor M1 is connected to the power supply terminal VDD, and the source of transistor M46 and the source of transistor Pdummy1 are connected to the common terminal GND. The second current output circuit includes transistors M50~M53, transistor Ndummy2, and transistor Pdummy2. The gates of transistor M50 and Ndummy2 are used to receive the UP1 pulse signal, and the gates of transistor M53 and Pdummy2 are used to receive the DN1 pulse signal. The third current output circuit includes transistors M54~M57, transistor Ndummy3, and transistor Pdummy3. The gates of transistor M54 and Ndummy3 are used to receive the UP2 pulse signal, and the gates of transistor M57 and Pdummy3 are used to receive the DN2 pulse signal.

[0083] The circuit structures of the second and third current output circuits are the same as those of the first current output circuit. Since the output range of the charge pump is close to 0 to VDD, to avoid being constrained by the common-mode voltage input range of the amplifier, the first operational amplifier circuit in the charge pump uses a complementary structure of NMOS and PMOS transistors to form a rail-to-rail input circuit. Transistors M22-M23 and M28-M29 together form the input terminals of the first operational amplifier circuit. Specifically, transistors M22-M23 are NMOS input type, and transistors M28-M29 are PMOS input type. Because the output control of the first operational amplifier circuit uses PMOS transistors, and the voltage controlling its gate usually does not require rail-to-rail characteristics, the operational amplifier output stage does not require a rail-to-rail structure. The output node Icp of the charge pump is connected to the positive input terminal of the operational amplifier circuit to form a negative feedback structure, which increases the output resistance of the structure. By utilizing the large open-loop gain of the operational amplifier, the drain voltages of transistors M40 and M46, and transistors M44 and M49 are made the same, so that the current can be accurately replicated, thereby improving the current matching accuracy and the output voltage range.

[0084] Furthermore, the multi-channel current output circuit is based on a source-switching structure. However, ordinary source-switching structures suffer from charge sharing issues. Taking the M48 and M49 branches as an example, when the switch is turned off, the source of transistor M48 remains at a low potential. To completely turn off the current of transistor M48, it discharges to the output node Icp of the charge pump until the voltage difference between the source and gate of transistor M48 is less than the threshold voltage Vth of the MOSFET. Based on the source-switching design, corresponding transistors Pdummy1 and Ndummy1 are added to the source design of transistors M47 and M48 to quickly turn off the current sources of transistors M47 and M48. When transistor M49 is turned off, transistor Pdummy1 directly pulls the source voltage of transistor M48 up to VDD, completing the rapid turn-off of the current source. Therefore, the introduction of transistors Pdummy1~Pdummy3 and Ndummy1~Ndummy3 reduces the impact of factors such as charge sharing and clock feedthrough. Due to the clamping effect of the first operational amplifier circuit, the voltages at node CN and the output node Icp of the charge pump are the same. When transistors M46 and M49 are turned on, transistors M41 and M47, and transistors M43 and M48 are identical in size and have the same port voltage, so the currents flowing through them are also the same. That is, the currents flowing through nodes Iru, Ird, Iup, and Idn are the same, thus making the pull-up and pull-down currents at the output exactly the same, solving the problem of charge and discharge current mismatch.

[0085] Among them, transistors M0, M2~M5, M10~M14, M22~M25, M30~M33, M37~M39, M43~M45, M48~M49, M52~M53, M56~M57, and Ndummy1~Ndummy3 are NMOS type, while transistors M1, M6~M9, M15~M21, M26~M29, M34~M36, M40~M42, M46~M47, M50~M51, M54~M55, and Pdummy1~Pdummy3 are PMOS type.

[0086] In some embodiments, such as Figure 5 As shown, the current source circuit includes a bandgap reference circuit, a current replication circuit, and a current output circuit.

[0087] The bandgap reference circuit is connected to the current replication circuit and is used to provide the voltage at the reference voltage node VREF generated by the bandgap reference circuit to the current replication circuit.

[0088] The current replication circuit is connected to the current output circuit. It is used to clamp the voltage at the reference voltage node VREF to the resistor R6 to obtain the required current IR, and then replicate it as a current Iref to transmit to the current output circuit.

[0089] The current output circuit is connected to the current replication circuit and is used to output an adjustable reference current IDC based on the input current Iref to provide bias current for the charge pump circuit.

[0090] In some embodiments, such as Figure 6 As shown, the main body of the bandgap reference circuit includes a bias circuit, a fast start-up circuit, and a core circuit.

[0091] The bias circuit is connected to the core circuit and the fast start circuit to provide a precise and stable bias current at node i_opa of the core circuit.

[0092] The fast-start circuit is connected to the core circuit and is used to provide temporary start-up current when the circuit starts up, thereby speeding up the state response;

[0093] The core circuit is connected to the fast start-up circuit and the bias circuit. By utilizing the high-gain operational amplifier OPA1 inside the core circuit, the bias circuit provides a stable bias current at node i_opa, the fast start-up circuit provides the start-up current, and the input power supply voltage VDD, a temperature-independent reference voltage at node VREF is generated.

[0094] In some embodiments, such as Figure 6 As shown, in the bandgap reference circuit:

[0095] The bias circuit includes resistors R0 and R1, transistor pnp1, PMOS transistors M66~M67, and NMOS transistors M58~M62.

[0096] Transistors M58, M59, M66, and M67 form a current mirror structure. One end of resistor R0 is connected to the drain and gate of transistor M58. The gate of transistor M58 is connected to the gate of transistor M59. The source of transistor M58 is connected to the emitter of transistor PNP1. The source of transistor M59 is connected to one end of resistor R1. The drain of transistor M59 is connected to the drain of transistor M66. The drain and gate of transistor M66 are connected. The gate of transistor M67 is connected to the gate of transistor M66. The drain of transistor 67 is connected to the drain of transistor M60. The gate of transistor M60 is connected to the drain. The gates of transistors M61 and M62 are connected to the gate of transistor M60. The drain of transistor M62 is connected to node i_opa. The other end of resistor R0, the gate and source of transistor M66, and the source of transistor M67 are connected to the power supply terminal VDD. The base and collector of transistor pnp1, the other end of resistor R1, the source of transistor M60, the source of transistor M61, and the source of transistor M62 are connected to the common terminal GND.

[0097] The fast-start circuit includes PMOS type transistors M68 to M72; the gate and drain of transistor M68 are connected, the gate of transistor M69 is connected to the gate of M68, the gate of transistor M70 is connected to the gate of transistor M68, the drain of transistor M68 is connected to the drain of transistor M61, the drain of transistor M69 is connected to node Vn via one end of resistor R2 in the core circuit, the drain of transistor M70 is connected to node Vp via one end of resistor R4 in the core circuit, the drain of transistor M71 is connected to the source of transistor M72, the drain of transistor M72 is connected to node C via the drain of transistor M68, and the sources of transistors M68, M69, M70, and M71 are connected to the power supply terminal VDD.

[0098] The core circuit includes PMOS transistors M73~M80, NMOS transistors M63~M65, resistors R2, R3, R4, and R5, transistors PNP2 and PNP3, capacitor C1, and operational amplifier OPA1. The current input terminal of operational amplifier OPA1 provides the bias current at node i_opa. The gates of transistors M73, M75, M77, and M79, the output terminal of operational amplifier OPA1, and the gate of transistor M71 are connected to node Vp1. The drain of transistor M73 is connected to the source of transistor M74, the drain of transistor M75 is connected to the source of transistor M76, and the drain of transistor M77 is connected to the source of transistor M78. The gates of transistors M74, M76, and M78, one end of capacitor C1, and the gate of transistor M72 are connected to node Vp2. The negative input terminal of operational amplifier OPA1 and the drain of transistor M74 are connected to node Vn, and the positive input terminal of operational amplifier OPA1 and the drain of transistor M76 are connected to node Vp. One end of resistor R2 is connected to transistor p. The emitter of transistor pnp2 is connected to node Vn. One end of resistor R3 and one end of resistor R4 are connected to node Vp. The other end of resistor R3 is connected to the emitter of transistor pnp3. The drain of transistor M78 and one end of resistor R5 are connected to the reference voltage node VREF. The gate of transistor M65 is connected to the reference voltage node VREF. The drain of transistor M79 is connected to the drain of transistor M63. The gate of transistor M63 is connected to its drain. The gate of transistor M64 is connected to the gate of transistor M63. The drain of transistor M64 is connected to the drain of transistor M80. The drain and gate of transistor M80 are connected to node Vp2. The other end of capacitor C1, the source of transistor M73, the source of transistor M75, the source of transistor M77, the source of transistor M79, and the source of transistor M80 are connected to the power supply terminal VDD. The other end of resistor R2, the base and collector of transistor pnp2, the base and collector of transistor pnp3, the other end of resistor R4, the other end of resistor R5, the source and drain of transistor M65, the source of transistor M63, and the source of transistor M64 are connected to the common terminal GND.

[0099] The bias circuit in the bandgap reference circuit consists of resistors R0 and R1, transistor PNP1, and a current mirror structure. Transistors M58, M59, M66, and M67 form NMOS and PMOS current mirrors, respectively, with their gates connected together to ensure identical gate voltages and accurate replication of their drain currents. Resistor R0 is connected between the power supply voltage VDD and the drain of transistor M58 to form a voltage divider, generating a stable voltage. Resistor R1 is connected between the source and ground of transistor M59 to ensure stable source voltage. The base and collector of transistor PNP1 are connected to ground, and its emitter is connected to the source of transistor M58, providing a stable current bias for subsequent circuitry. Transistors M60, M61, and M62 form the structure that provides bias current to operational amplifier OPA1. The bias circuit is connected to both the core circuit and the fast-start circuit. It provides a stable and precise bias current at node i_opa for the operational amplifier OPA1 in the core circuit and provides a current difference at node C for the fast-start circuit, causing transistors M70 and M69 to turn off and shut down the fast-start circuit. The core circuit is connected to the fast-start circuit and generates and outputs a near-zero temperature coefficient reference voltage at node VREF based on the input power supply voltage VDD. The fast-start circuit is connected to the core circuit and provides a temporary startup current to the core circuit module after power-on, allowing the core circuit module to quickly transition from zero-current degenerate current to normal operating conditions.

[0100] The core circuit of the bandgap reference circuit consists of operational amplifier OPA1, a cascode current mirror, resistors R2-R5, and transistors PNP2 and PNP3. Transistors M73-M76 form a cascode current mirror to increase impedance, and the drains of transistors M76 and M74 are connected to the emitter of transistor PNP2 and resistor R3, respectively. The positive input of operational amplifier OPA1 is connected to node Vp and resistors R4 and R3, while the negative input is connected to node Vn and resistors R2 and transistor PNP2. Its virtual short characteristic clamps the voltages at nodes Vn and Vp, making the voltage at node Vn equal to the voltage at node Vp. A MOS capacitor C1 is added to the Cascode current mirror in the core circuit. One end of C1 is connected to the power supply terminal VDD, and the other end is connected to node Vp2. The gate of transistor M65 is connected to the reference voltage node VREF. The added transistor M65 acts as a MOS capacitor to filter high-frequency noise and improve the power supply rejection ratio (PSRR) at the reference voltage node VREF. In the fast startup circuit, the drains of transistors M70 and M69 are connected to nodes Vp and Vn, respectively, to provide temporary startup current to nodes Vn and Vp when the overall circuit starts up, accelerating loop establishment and entering normal operating state. The gate bias voltages of transistors M71 and M72 come from nodes Vp1 and Vp2, respectively. The drain of transistor M72 is connected to node C, which is the drain and gate of transistor M18. Due to the current difference between transistors M61 and M72, the parasitic capacitance at node C is charged. When the loop is stable, the gate voltages of transistors M70 and M69 can be pulled up to VDD, thereby automatically turning off transistors M70 and M69 to complete the fast startup process.

[0101] In the core circuit, the bases and collectors of transistors PNP2 and PNP3 are connected to the common terminal GND. The emitter of transistor PNP3 is connected to resistor R3. The voltage across resistor R3 is the voltage difference ΔVBE between transistors PNP2 and PNP3, which is a positive temperature coefficient voltage. The current through resistor R3 also has a positive temperature coefficient. Meanwhile, since resistors R2 and PNP2 are connected in parallel, the voltage across resistor R2 is VBE, which is a negative temperature coefficient voltage. The current through resistor R2 also has a negative temperature coefficient. The drain of transistor M77 is connected to the source of transistor M78. Its gate bias voltage comes from nodes Vp1 and Vp2. The drain of transistor M78 is connected to the common terminal GND through resistor R5. Thus, a near-zero temperature coefficient reference voltage at node VREF is obtained through a current mirror along the path connecting resistor R5 and transistor M78.

[0102] In some embodiments, such as Figure 5 As shown, in the current source circuit:

[0103] The current replication circuit includes operational amplifier OPA2, transistors M81~M87, and resistor R6. The reference voltage generated by the bandgap reference circuit at node VREF is connected to the positive input terminal of operational amplifier OPA2. The negative input terminal of operational amplifier OPA2 is connected to the source of transistor M85, and one end of resistor R6 is connected to node F. The output terminal of operational amplifier OPA2 is connected to the gate of transistor M85. The drain of transistor M85, along with the drain and gate of transistors M81, M82, and M84, are all connected to node K. The drain of M82 is connected to the drain and gate of transistor M86. The gate of transistor M87 is connected to the gate of transistor M86. The drain of transistor M87, the drain of transistor M84, and the gate of transistor M83 are all connected to node L. The source of transistor M84 is connected to the drain of transistor M83. The sources of transistors M81, M82, and M83 are connected to the power supply terminal VDD. The sources of transistors M86 and M87, along with the other end of resistor R6, are connected to the common terminal GND.

[0104] The current output circuit includes transistors M88 to M93; the gates of transistors M88 and M89 are connected to node L; the drain of transistor M88 is connected to the source of transistor M90; the drain of transistor M89 is connected to the source of transistor M91; the gates of transistors M90 and M91 are connected to the gate of transistor M84; the drain of transistor M90 is connected to the drain of transistor M92; the drain of transistor M91 is connected to the drain of transistor M93; and the gate of transistor M92 is used to receive the external control signal Sel. <0> The gate of transistor M93 is used to receive the external control signal Sel. <1> The source of transistor M88 and the source of transistor M89 are connected to the power supply terminal VDD, and the source of transistor M92 and the source of transistor M93 are connected to the output reference current IDC.

[0105] The voltage at the reference voltage node VREF output by the bandgap reference circuit is provided to the op-amp OPA2. Utilizing the high gain and virtual short characteristics of the op-amp OPA2, the voltage at the reference voltage node VREF is clamped to the resistor R6. By using the temperature-independent voltage at the reference voltage node VREF and the high-precision and stable resistor R6, a stable and accurate reference current IDC is generated. Thus, the current IR can be obtained first on the branch of transistor M81.

[0106] Since the input resistance of a MOS transistor is infinite, it can be approximated that there is no static current at the gate of the MOS transistor. Therefore, the current IR flowing through resistor R6 is equal to the current in transistor M81. When the size ratio of transistor M81 and transistor M82 is set to be the same, transistor M81 replicates the current IR to the branch of transistor M82 in the same proportion to obtain IR1. The magnitude of current IR1 is only related to resistor R6 and the voltage at the reference voltage node VREF. Thus, by selecting the resistance value of resistor R6 and the voltage value of VREF, the set current value can be obtained. Similarly, the size ratio of transistor M86 and transistor M87 is set to be the same, and finally, the current Iref is replicated in the branch of transistor M87.

[0107] Because the charge pump circuit needs to ensure the accuracy of the charging and discharging current, but the output impedance of the MOS transistor is limited, and non-ideal factors such as the channel length modulation effect cause the replication current Iref to change with the drain-source voltage of the MOS transistor, an optimized current mirror structure with cascode is used in the current output circuit to improve the replication accuracy of the current Iref. In addition, a 2-bit external control word is used to control the two switching transistors M92 and M93 to realize the adjustable output reference current IDC, so as to meet the different requirements of the charge pump and phase-locked loop for the accuracy, stability and value of the bias current.

[0108] In some embodiments, the multi-channel current output circuit is implemented by combining multiple sets of high-precision matching current mirrors in parallel with a digital control module. The digital control module includes a UP digital control circuit and a DN digital control circuit. The UP digital control circuit is used to input UP0 pulse signals, UP1 pulse signals, and UP2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump to control the on / off state of each pull-up current transistor. The DN digital control circuit is used to input DN0 pulse signals, DN1 pulse signals, and DN2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump to control the on / off state of each pull-down current transistor. The digital control module controls the UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals to control the charging and discharging of transistors such as M47, M51, M55, M48, M52, and M56 in the charge pump. This enables the charging and discharging current to be nonlinearly adjustable from 50μA to 150μA to match the requirements of different phase-locked loop stages and increase the frequency adaptation range of the phase-locked loop. Similarly, Pdummy or Ndummy transistors are added to the source terminals of each group of transistors to reduce charge sharing, clock feedthrough, and contributions to phase noise and spurious emissions in the phase-locked loop.

[0109] In some embodiments, the digital control module includes a UP digital control circuit for inputting UP0 pulse signals, UP1 pulse signals, and UP2 pulse signals to the gates of the pull-up current transistors in the charge pump multi-channel current output circuit, in order to control the on / off state of each pull-up current transistor, such as... Figure 12 As shown, the UP digital control circuit includes NOR gates and cascaded inverters. The UP pulse signal first passes through inverter INV0, then is output to the inputs of each NOR gate NOR1 / NOR2 / NOR3, and then sequentially passes through three cascaded inverters such as INV8, INV8_1, and INV8_2, finally outputting UP0 / UP1 / UP2 pulse signals to cooperate with the charge pump to control the transistor's on / off state. The other input of NOR gate NOR1 is connected to a fixed low level 0 to ensure that the charge pump always has current output. The remaining control words B0 and B1 can select whether the UP1 / UP2 pulse signals are turned on or off, thereby changing the magnitude of the pull-up current of the second and third channels in the multi-channel current output circuit of the charge pump.

[0110] In some embodiments, the digital control module further includes a DN digital control circuit for inputting DN0 pulse signals, DN1 pulse signals, and DN2 pulse signals to the gates of the pull-down current transistors in the charge pump multi-channel current output circuit, in order to control the on / off state of each pull-down current transistor, such as... Figure 13 As shown, the DN digital control circuit includes NAND gates and cascaded inverters. The DN pulse signal first passes through inverter INV14, then is output to the inputs of NAND gates Nand1 / Nand2 / Nand3, and then sequentially passes through three cascaded inverters such as INV11, INV11_1, and INV11_2 to finally output DN0 / DN1 / DN2 pulse signals to cooperate with the charge pump to control the transistor's on / off state. The other input of NAND gate Nand1 is connected to a fixed high level (1) to ensure that the charge pump always has current output. The remaining control words A0 and A1 can select whether the DN1 / DN2 pulse signals are on or off. Thus, by combining the control words A0, A1, B0, and B1, the overall output current of the charge pump is changed.

[0111] In some embodiments, the phase-locked loop may further include a loop filter, a voltage-controlled oscillator (VCO), and a programmable frequency divider. The current pulse signals Icpout0, Icpout1, and Icpout2 from the charge pump are used as inputs to the loop filter. The loop filter converts the current pulse signals generated by the charge pump into a control voltage Vctrl, performs low-pass filtering on Vctrl, and transmits it to the VCO. The VCO adjusts its output oscillation frequency fvco according to the input control voltage Vctrl, and finally uses the output oscillation frequency fvco as input to the programmable frequency divider. The programmable frequency divider down-divides the VCO output oscillation frequency fvco according to a set division ratio M, and can flexibly switch its division ratio M as needed to correspond to different output frequencies of the VCO. Finally, it generates a feedback clock CLK_DIV close to the reference clock and provides it to the frequency and phase detector, thereby achieving the locking of the entire phase-locked loop.

[0112] Figure 7 Simulation results of the input and output signals of a phase-locked loop frequency and phase detector provided in an embodiment of this application. For example... Figure 7 As shown, the inputs are the reference clock CLK_REF and the feedback clock CLK_DIV of the frequency and phase detector, both with a frequency of 100MHz. However, the phase of the reference clock leads the phase of the feedback clock by 1 / 5 of a cycle (2ns). Therefore, the frequency and phase detector generates two output signals, UP pulse signal and DN pulse signal, based on the phase comparison. The pulse width of the UP pulse signal is greater than that of the DN pulse signal; the difference between the two is the phase error between the reference clock and the feedback clock. The UP and DN pulse signals are then transmitted to the charge pump via the digital control module. The charge pump, based on the phase differences between the UP0, UP1, and UP2 pulse signals output from the digital control module and the DN0, DN1, and DN2 pulse signals respectively, effectively charges the load capacitor of the loop filter, allowing the feedback clock to catch up with the reference clock until the frequency and phase of the feedback clock are equal.

[0113] Figure 8 Simulation results for the operating swing voltage range and static charge / discharge current adaptation of a charge pump in a phase-locked loop under different PVT conditions, as provided in the embodiments of this application. Figure 8As shown, by scanning the output voltage X of the charge pump within the range of 0~1.8V when the control words A0 and B0 in the digital module are turned on, the static current matching and output voltage swing under different PVTs are displayed. It can be seen that the charge pump has good current matching within the output voltage range of 0.3~1.5V, and its output voltage swing can be used within the range of 0.3~1.5V. Table 1 shows the output voltage swing under different PVTs, and the specific values ​​of the charge pump pull-up charging current Iup0 / 1 / 2 and discharge current Idn0 / 1 / 2 under different output voltage values:

[0114] Table 1. Specific values ​​of the pull-up charging current Iup0 / 1 / 2 and the discharge current Idn0 / 1 / 2 of each charge pump.

[0115]

[0116] Therefore, the average output current is 101.37uA at the TT process angle / 27℃ / 1.8V, and 92.3uA and 110.02uA at the SS process angle / -45℃ / 1.62V and the FF process angle / 125℃ / 1.98V, respectively.

[0117] According to the formula for current mismatch rate:

[0118] ;

[0119] Where Iup is the charging current pulled up by the charge pump, and Idn is the discharging current pulled down; thus, the mismatch rates of the charge pump at half the output power supply voltage, i.e., VDD / 2, are shown in Table 2, which are 0.069%, 0.097% and 0.18%, respectively, with the minimum mismatch rate being only 0.07%.

[0120] Table 2. Average output current and current mismatch rate of the charge pump under different PVT conditions.

[0121]

[0122] Depend on Figure 8 As can be seen from Table 2, under different PVT conditions, the designed charge pump can still have a very small current mismatch rate within a large operating swing range of 0.3~1.5V.

[0123] Figure 9 The results of the output reference voltage changing with temperature under different process angles and power supply voltages in a phase-locked loop bandgap reference circuit provided in this application embodiment. Figure 9The table shows the voltage variation at the reference voltage node VREF (hereinafter referred to as the reference voltage) within the temperature range of -45~130℃ under different process angles and power supply voltages. Table 3 shows the specific values ​​of the reference voltage at different process angles, power supply voltages, and temperatures.

[0124] Table 3. Specific values ​​of reference voltage as a function of temperature under different process angles and power supply voltages.

[0125]

[0126] The temperature coefficient represents the change in output voltage during temperature changes, and its calculation formula is:

[0127] ;

[0128] Where VREF(max) is the maximum value of the reference voltage within this temperature range, VREF(min) is the minimum value, and Vaverage is the average value; Tmax is the maximum temperature value within this temperature range, and Tmin is the minimum temperature value; the maximum, minimum, and average values ​​of the reference voltage and the temperature drift coefficient are shown in Table 4.

[0129] Table 4. Maximum, minimum, and average values ​​of the reference voltage and temperature drift coefficient

[0130]

[0131] The average value of the reference voltage is 594~595.7mV, with the highest temperature drift coefficient being 36.93 ppm / ℃ and the lowest being only 19.61 ppm / ℃. Overall, it has a low temperature coefficient and can cover various extreme conditions with different process angles and temperatures, demonstrating excellent reliability and stability.

[0132] Figure 10 The simulation results of the cascaded output noise of a phase-locked loop circuit consisting of a frequency and phase detector, a digital control module, a charge pump, and a current source under different PVT conditions are provided in the embodiments of this application. Figure 10 Simulation results of output noise are presented for four cascaded circuit modules, with a charge pump output current of 50μA at a reference clock frequency offset of 1kHz to 10MHz, and under different PVT and temperature conditions. Table 5 shows the specific values ​​of output current noise at 100kHz and 1MHz.

[0133] Table 5. Specific values ​​of output current noise at frequency deviations of 100kHz and 1MHz.

[0134]

[0135] It can be seen that under different PVT conditions, the output current noise is in the range of -242.6 to -246.9 dBA / Hz at a frequency offset of 100 kHz; and the output current noise is in the range of -245.2 to -248.9 dBA / Hz at a frequency offset of 1 MHz. This indicates that the cascaded circuit of frequency discriminator, digital control module, charge pump and current source circuit has good reliability and excellent noise performance, which greatly suppresses the noise contribution of the overall phase-locked loop within the band.

[0136] Figure 11(a) shows the simulation results of dynamic charging of the control voltage Vctrl under the cascaded circuitry of a phase-locked loop (PLL) containing a frequency detector, a charge pump, and a current source, according to an embodiment of this application. As shown in Figure 11(a), with the four circuit modules cascaded and control words A0 and B0 in the digital module enabled, the simulation results of dynamic charging of the loop filter's load capacitor under different PVT conditions within the time range of 0~150ns are presented. Table 6 shows the specific values ​​of the charging variation of the control voltage Vctrl under different PVT conditions.

[0137] Table 6. Specific values ​​for the charging variation of the control voltage Vctrl.

[0138]

[0139] As can be seen, when the reference clock CLK_REF leads the feedback clock CLK_DIV by 1 / 5 cycle (2ns), the charge pump needs to charge the load capacitor. The UP pulse signal width must be greater than the DN pulse signal width. Therefore, the control voltage Vctrl output by the charge pump through the loop filter and load capacitor continuously increases in charge following the signal control, and the average charge value of the output control voltage Vctrl per cycle over 15 cycles is approximately 0.964mV.

[0140] Figure 11(b) shows the simulation results of dynamic discharge of the control voltage Vctrl under the cascaded circuit of frequency detector, charge pump and current source in a phase-locked loop provided in the embodiment of this application. Similarly, Table 7 shows the specific values ​​of the discharge change of the control voltage Vctrl under different PVTs:

[0141] Table 7. Specific values ​​for the discharge variation of the control voltage Vctrl.

[0142]

[0143] As can be seen, when the reference clock CLK_REF lags behind the feedback clock CLK_DIV by 1 / 5 cycle (2ns), the charge pump needs to discharge the load capacitor. The DN pulse signal width must be greater than the UP pulse signal width. Therefore, the control voltage Vctrl output by the charge pump through the loop filter and load capacitor continuously decreases following the signal control. The average charging value of the control voltage Vctrl per cycle over 15 cycles is approximately 0.9603mV. Based on this, under different PVT conditions, the minimum mismatch rate of the cascaded dynamic charge / discharge current is less than 1%, indicating excellent dynamic current matching. This significantly reduces the contribution to the overall PLL phase noise and spurious signals, thereby improving the PLL noise level.

[0144] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The term "multiple" refers to two or more unless otherwise expressly defined.

[0145] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only.

[0146] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A phase-locked loop, characterized in that, The phase-locked loop includes: The frequency and phase detector includes input terminal 1, input terminal 2, pulse output terminal 1, and pulse output terminal 2. It is used to compare the frequency and phase of the reference clock CLK_REF and the feedback clock CLK_DIV, and output UP pulse signal and DN pulse signal. Input terminal 1 is connected to the reference clock CLK_REF, and input terminal 2 is connected to the feedback clock CLK_DIV. The charge pump includes input terminals three, four, five, eight, and six. Input terminals three and four are connected to output terminals six and seven of the digital control module, respectively. Based on the PD control signal, the phase difference between the UP0, UP1, and UP2 pulse signals and the DN0, DN1, and DN2 pulse signals is converted into adjustable multi-channel charging and discharging current pulse signals Icpout0, Icpout1, and Icpout2, respectively. The digital control module includes input terminals six, seven, nine, ten, eleven, and twelve, and output terminals six and seven. Input terminals six and seven are connected to pulse output terminals one and two of the frequency and phase detector, respectively. Output terminals six and seven are connected to input terminals three and four of the charge pump. Input terminals nine, ten, eleven, and twelve are connected to external control signals A0, A1, B0, and B1, respectively, and are used to determine the UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals based on the UP pulse signal, DN pulse signal, and external control signals, and control the on / off state of the current transistor in the charge pump. The current source circuit includes input terminal thirteen, input terminal fourteen, and current output terminal. Input terminal thirteen is used to receive the external control signal Sel. <0> Input terminal fourteen is used to receive external control signal Sel. <1> It is used to adjust and change the output reference current IDC. The current output terminal is connected to the input terminal 5 of the charge pump to input the reference current IDC to the charge pump.

2. A phase-locked loop according to claim 1, characterized in that, The frequency and phase detector includes an input buffer, a D flip-flop, a reset delay unit, and an output circuit. The input buffer includes buffer1 and buffer2, the D flip-flop includes flip-flop D1 and flip-flop D2, the reset delay unit includes delay unit Delay and NAND gate, and the output circuit includes transmission gate TG1 and inverters INV1~INV7. Buffers buffer1 and buffer2 are connected to the reference clock and feedback clock, respectively, to receive clock signals. The input terminal CLK1 of flip-flop D1 is connected to the output terminal of buffer buffer1, and the input terminal CLK2 of flip-flop D2 is connected to the output terminal of buffer buffer2. The output terminal of flip-flop D1 generates signal A, which is connected to the input terminal of inverter INV1 and the first input terminal of NAND gate. The signal A output by flip-flop D1 passes through inverters INV1~INV4 to generate and output an UP pulse signal. The output terminal of flip-flop D2 generates signal B, which is connected to the input terminal of transmission gate TG1. The second input terminals of both the NAND gate and the NAND gate are connected. The B signal output by the flip-flop D2 passes through the transmission gate TG1 and the inverters INV5~INV7 to generate and output the DN pulse signal. The output terminal of the NAND gate generates the C signal and connects to the input terminal of the delay unit Delay. The delay unit Delay delays the C signal and sends the resulting reset signal to the reset terminals Reset1 of flip-flop D1 and Reset2 of flip-flop D2. The inverters INV1~INV4 are connected in series, and the transmission gate TG1 is connected in series with the inverters INV5~INV7. The inverter INV4 outputs the UP pulse signal, and the inverter INV7 outputs the DN pulse signal.

3. A phase-locked loop according to claim 1, characterized in that, The charge pump includes a current bias circuit, a first operational amplifier circuit, a replication startup circuit, and a multi-channel current output circuit. The bias circuit is connected to the first operational amplifier circuit and the replication startup circuit. It is used to control the input of the reference current IDC, replicate the reference current IDC and generate a bias voltage VGS, providing the tail current source and bias voltage for the first operational amplifier circuit and the replication startup circuit. The first operational amplifier circuit is connected to the replication startup circuit and the multiple current output circuit, and uses high gain and clamping effect to enable the current to be replicated. The replication startup circuit is connected to the first operational amplifier circuit and the multiple current output circuit. It is used to accelerate the current replication in the negative feedback loop of the first operational amplifier circuit and ensure that the negative input terminal of the first operational amplifier changes smoothly. The multi-output current circuit is connected to the first operational amplifier circuit and is used in conjunction with the digital control module to perform nonlinear adjustment of the charging and discharging current in the range of 50~150μA.

4. A phase-locked loop according to claim 3, characterized in that, The PD control signal includes the PDP control signal and the PDN control signal, in the charge pump: The current bias circuit includes transistors M0 to M17. The drain of transistor M0 and the source of transistor M1 are connected to the current output terminal of the current source circuit to receive the reference current IDC. The gates of transistors M0 and M1 are used to receive the PDN control signal and the PDP control signal, respectively. The source of transistor M0 and the drain of transistor M1 are connected to the drain of transistor M2. The drain of transistor M2 is connected to the gate of transistor M2. The source of transistor M2 is connected to the drain of transistor M4. The gate of transistor M2 is connected to the gate of transistor M3; the drain of transistor M5 is connected to the source of transistor M3; the drain of transistor M3 is connected to the drain of transistor M6; the drain of transistor M6 is connected to the gate of transistor M6; the gate of transistor M6 is connected to the gate of transistor M9; the drain of transistor M8 is connected to the source of transistor M9; the drain of transistor M9 is connected to the drain of transistor M10; the drain of transistor M10 is connected to the gate of transistor M10; and the source of transistor M10 is connected to the gate of transistor M11. The drain of transistor M11 is connected to the gate of transistor M11; the source of transistor M11 is connected to the drain of transistor M13; the gate of transistor M12 is connected to the gate of transistor M11; the source of transistor M12 is connected to the drain of transistor M14; the drain of transistor M12 is connected to the drain of transistor M15; the source of transistor M15 is connected to the drain of transistor M16; the source of transistor M16 is connected to the drain of transistor M17; and the gate of transistor M15 is connected to the drain of transistor M16. The drain is connected, the gate of transistor M16 is connected to the drain of transistor M16, the gate of transistor M4, the gate of transistor M5, the source of transistor M7, the source of transistor M8, the gate of transistor M13, the gate of transistor M14, and the source of transistor M17 are connected to the power supply terminal VDD, and the source of transistor M4, the source of transistor M5, the source of transistor M13, the source of transistor M14, the gate of transistor M7, the gate of transistor M8, and the gate of transistor M17 are connected to the common terminal GND. The first operational amplifier circuit includes transistors M18 to M33. The drain of transistor M18 is connected to the source of transistor M20, the drain of transistor M20 is connected to the gate of transistor M20, the drain of transistor M20 is connected to the drain of transistor M22, the gate of transistor M22 is connected to node CN, the drain of transistor M19 is connected to the source of transistor M21, the gate of transistor M21 is connected to the gate of transistor M20, and the drain of transistor M21 is connected to the drain of transistor M23. The gate of transistor M23 is connected to the output node Icp of the charge pump. Current pulse signals Icpout0, Icpout1, and Icpout2 are output from the output node Icp. The source of transistor M22 is connected to the source of transistor M23 and the drain of transistor M24. The gate of transistor M24 is connected to the gate of transistor M12. The source of transistor M24 is connected to the drain of transistor M25. The drain of transistor M26 is connected to the source of transistor M27. The gate of transistor M27 is connected to the gate and drain of transistor M16. The drain of transistor M27 is connected to the source of both transistor M28 and transistor M29. The gate of transistor M28 is connected to node CN. The gate of transistor M29 is connected to the output node Icp of the charge pump. The drains of transistors M28 and M29 are connected to the drains of transistors M30 and M31, respectively. The drain of transistor M30 is connected to its gate. The source of transistor M31 is connected to the drain of transistor M32 and the drain of transistor M33, respectively. The source of transistor M18, the source of transistor M19, the gate of transistor M25, the source of transistor M26, the gate of transistor M32, and the gate of transistor M33 are connected to the power supply terminal VDD. The gate of transistor M18, the gate of transistor M19, the source of transistor M25, the gate of transistor M26, the source of transistor M32, and the source of transistor M33 are connected to the common terminal GND. The replication startup circuit includes transistors M34 to M45. The drain of transistor M34 is connected to the source of transistor M35. The drain of transistor M35 is connected to the gate of transistor M35, the source of transistor M36, and the drain of transistor M21. The gate of transistor M36 is connected to the gate and drain of transistor M15. The drain of transistor M36, the source of transistor M37, and the drain of transistor M38 are connected. The drain of transistor M38 is connected to the gate of transistor M38 and the drain of transistor M31. The source of transistor M38 is connected to the drain of transistor M39. The drain of transistor M40 is connected to the source of transistor M41. The gate of transistor M41 is connected to the drain of transistor M35 and the drain of transistor M45.

2. The gate of transistor M41 is connected to the drain of transistor M43, one end of capacitor C1 is connected to node CN, the gate of transistor M43 is connected to the gate of transistor M45 and the drain of transistor M38, the source of transistor M43 is connected to the drain of transistor M44, the source of transistor M44 is connected to the source and drain of transistor M45, the gate of transistor M39, the gate of transistor M44, the source of transistor M34, the source and drain of transistor M42, and the source of transistor M40 are connected to the power supply terminal VDD, the gate of transistor M34, the gate of transistor M40, the other end of capacitor C1, the source of transistor M39, the source and drain of transistor M45, and the source of transistor M44 are connected to the common terminal GND. The multi-channel current output circuit includes three current output circuits, used to generate charging and discharging current pulse signals Icpout0, Icpout1, and Icpout2 based on the phase difference between UP0, UP1, UP2, DN0, DN1, and DN2 pulse signals. The UP0 pulse signal is input to the gates of transistors M46 and Ndummy1, the UP1 pulse signal is input to the gates of transistors M50 and Ndummy2, the UP2 pulse signal is input to the gates of transistors M54 and Ndummy3, the DN0 pulse signal is input to the gates of transistors M49 and Pdummy1, the DN1 pulse signal is input to the gates of transistors M53 and Ndummy2, and the DN2 pulse signal is input to the gates of transistors M57 and Pdummy3. The first current output circuit includes transistors M46~M49, transistor Ndummy1, and transistor Pdummy1. The gate of transistor M46 is connected to the gate of transistor Ndummy1. The gates of transistor M46 and Ndummy1 are used to receive the UP0 pulse signal. The gates of transistor M49 and Pdummy1 are used to receive the DN0 pulse signal. The drain of transistor M46 is connected to the drain of transistor Ndummy1 and the source of transistor M47. The drain of transistor M47 and the drain of transistor M48 are connected to the output node Icp of the charge pump. The gate of transistor M47 is connected to the gate of transistor M41. The gate of transistor M48 is connected to the gate of transistor M43. The source of transistor M48 is connected to the drain of transistor Pdummy1. The drain of transistor M49 is connected. The gate of transistor M49 is connected to the gate of transistor Pdummy1. The gate of transistor M1 is connected to the power supply terminal VDD, and the source of transistor M46 and the source of transistor Pdummy1 are connected to the common terminal GND. The second current output circuit includes transistors M50~M53, transistor Ndummy2, and transistor Pdummy2. The gates of transistor M50 and Ndummy2 are used to receive the UP1 pulse signal, and the gates of transistor M53 and Pdummy2 are used to receive the DN1 pulse signal. The third current output circuit includes transistors M54~M57, transistor Ndummy3, and transistor Pdummy3. The gates of transistor M54 and Ndummy3 are used to receive the UP2 pulse signal, and the gates of transistor M57 and Pdummy3 are used to receive the DN2 pulse signal. The circuit structures of the second and third current output circuits are the same as those of the first current output circuit. Transistors M0, M2~M5, M10~M14, M22~M25, M30~M33, M37~M39, M43~M45, M48~M49, M52~M53, M56~M57, and Ndummy1~Ndummy3 are NMOS type, while transistors M1, M6~M9, M15~M21, M26~M29, M34~M36, M40~M42, M46~M47, M50~M51, M54~M55, and Pdummy1~Pdummy3 are PMOS type.

5. A phase-locked loop according to claim 1, characterized in that, The current source circuit includes a bandgap reference circuit, a current replication circuit, and a current output circuit. The bandgap reference circuit is connected to the current replication circuit and is used to provide the current replication circuit with the voltage at the reference voltage node VREF generated by the low bandgap reference circuit. The current replication circuit is connected to the current output circuit and is used to clamp the voltage at the reference voltage node VREF to the resistor R6 to obtain the required current IR, and replicate it as a current Iref to transmit to the current output circuit. The current output circuit is connected to the current replication circuit and is used to output an adjustable reference current IDC based on the input current Iref to provide bias current for the charge pump circuit.

6. A phase-locked loop according to claim 5, characterized in that, In the current source circuit: The bandgap reference circuit includes a bias circuit, a fast start-up circuit, and a core circuit. The bias circuit is connected to the core circuit and the fast start circuit, and is used to provide a precise and stable bias current at node i_opa of the core circuit. The fast start circuit is connected to the core circuit and is used to provide a temporary start-up current when the circuit starts up, thereby accelerating the state response. The core circuit is connected to the fast start-up circuit and the bias circuit. By utilizing the high-gain operational amplifier OPA1 inside the core circuit, the bias circuit provides a stable bias current at node i_opa, the fast start-up circuit provides the start-up current, and the input power supply voltage VDD, a temperature-independent reference voltage at node VREF is generated.

7. A phase-locked loop according to claim 6, characterized in that, In the bandgap reference circuit: The bias circuit includes resistor R0, resistor R1, transistor pnp1, PMOS type transistors M66~M67, and NMOS type transistors M58~M62. Transistors M58, M59, M66, and M67 form a current mirror structure. One end of resistor R0 is connected to the drain and gate of transistor M58. The gate of transistor M58 is connected to the gate of transistor M59. The source of transistor M58 is connected to the emitter of transistor PNP1. The source of transistor M59 is connected to one end of resistor R1. The drain of transistor M59 is connected to the drain of transistor M66. The drain and gate of transistor M66 are connected. The gate of transistor M67 is connected to the gate of transistor M66. The drain of transistor M67 is connected to the drain of transistor M60, the gate of transistor M60 is connected to the drain, the gates of transistors M61 and M62 are connected to the gate of transistor M60, the drain of transistor M62 is connected to node i_opa, the other end of resistor R0, the source of transistor M66, and the source of transistor M67 are connected to the power supply terminal VDD, the base and collector of transistor pnp1, the other end of resistor R1, the source of transistor M60, the source of transistor M61, and the source of transistor M62 are connected to the common terminal GND; The fast startup circuit includes PMOS type transistors M68 to M72; the gate and drain of transistor M68 are connected, the gate of transistor M69 is connected to the gate of M68, the gate of transistor M70 is connected to the gate of transistor M68, the drain of transistor M68 is connected to the drain of transistor M61, the drain of transistor M69 is connected to node Vn via one end of resistor R2 in the core circuit, the drain of transistor M70 is connected to node Vp via one end of resistor R4 in the core circuit, the drain of transistor M71 is connected to the source of transistor M72, the drain of transistor M72 is connected to node C via the drain of transistor M68, and the sources of transistors M68, M69, M70, and M71 are connected to the power supply terminal VDD; The core circuit includes PMOS transistors M73~M80, NMOS transistors M63~M65, resistors R2, R3, R4, and R5, transistors PNP2 and PNP3, capacitor C1, and operational amplifier OPA1. The current input terminal of operational amplifier OPA1 provides the bias current at node i_opa. The gates of transistors M73, M75, M77, and M79, the output terminal of operational amplifier OPA1, and the gate of transistor M71 are connected to node V. p1, the drain of transistor M73 is connected to the source of transistor M74, the drain of transistor M75 is connected to the source of transistor M76, the drain of transistor M77 is connected to the source of transistor M78, the gates of transistors M74, M76, and M78, one end of capacitor C1, and the gate of transistor M72 are connected to node Vp2. The negative input terminal of op-amp OPA1 and the drain of transistor M74 are connected to node Vn, and the positive input terminal of op-amp OPA1 and the drain of transistor M76 are connected to node Vp. One end of resistor R2 is connected to the transistor... The emitter of transistor PNP2 is connected to node Vn. One end of resistor R3 and one end of resistor R4 are connected to node Vp. The other end of resistor R3 is connected to the emitter of transistor PNP3. The drain of transistor M78 and one end of resistor R5 are connected to the reference voltage node VREF. The gate of transistor M65 is connected to the reference voltage node VREF. The drain of transistor M79 is connected to the drain of transistor M63. The gate and drain of transistor M63 are connected. The gate of transistor M64 is connected to the gate of transistor M63. The drain of transistor M64 is connected to the gate of transistor M80. The drain and gate of transistor M80 are connected to node Vp2. The other end of capacitor C1, the source of transistor M73, the source of transistor M75, the source of transistor M77, the source of transistor M79, and the source of transistor M80 are connected to the power supply terminal VDD. The other end of resistor R2, the base and collector of transistor pnp2, the base and collector of transistor pnp3, the other end of resistor R4, the other end of resistor R5, the source and drain of transistor M65, the source of transistor M63, and the source of transistor M64 are connected to the common terminal GND.

8. A phase-locked loop according to claim 5, characterized in that, In the current source circuit: The current replication circuit includes operational amplifier OPA2, transistors M81~M87, and resistor R6. The reference voltage generated by the bandgap reference circuit at node VREF is connected to the positive input terminal of operational amplifier OPA2. The negative input terminal of operational amplifier OPA2 is connected to the source of transistor M85, and one end of resistor R6 is connected to node F. The output terminal of operational amplifier OPA2 is connected to the gate of transistor M85. The drain of transistor M85, along with the drain and gate of transistor M81, the gate of transistor M82, and the gate of transistor M84, are all connected to node K. The drain of transistor M82 is connected to the crystal... The drain and gate of transistor M86 are connected; the gate of transistor M87 is connected to the gate of transistor M86; the drain of transistor M87, the drain of transistor M84, and the gate of transistor M83 are all connected to node L; the source of transistor M84 is connected to the drain of transistor M83; the sources of transistors M81, M82, and M83 are connected to the power supply terminal VDD; the sources of transistors M86 and M87, along with the other end of resistor R6, are connected to the common terminal GND; the current output circuit includes transistors M88 to M93. transistor The gates of transistors M88 and M89 are connected to node L. The drain of transistor M88 is connected to the source of transistor M90, and the drain of transistor M89 is connected to the source of transistor M91. The gates of transistors M90 and M91 are connected to the gate of transistor M84. The drain of transistor M90 is connected to the drain of transistor M92, and the drain of transistor M91 is connected to the drain of transistor M93. The gate of transistor M92 is used to receive the external control signal Sel. <0> The gate of transistor M93 is used to receive the external control signal Sel. <1> The source of transistor M88 and the source of transistor M89 are connected to the power supply terminal VDD, and the source of transistor M92 and the source of transistor M93 are connected to the output reference current IDC.

9. A phase-locked loop according to claim 4, characterized in that, The digital control module includes a UP digital control circuit and a DN digital control circuit. The UP digital control circuit is used to input UP0 pulse signals, UP1 pulse signals, and UP2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump, so as to control the on and off of each pull-up current transistor. The DN digital control circuit is used to input DN0 pulse signals, DN1 pulse signals, and DN2 pulse signals to the gate of the pull-up current transistor in the multi-channel current output circuit of the charge pump, so as to control the on and off of each pull-down current transistor.

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