A multi-channel ADC module and sampling system

Abstract

The utility model discloses a kind of multi-channel ADC module and sampling system, comprising: at least one ADC conversion unit;At least two inner layer input channels, two inner layer input channels are connected with ADC conversion unit;Outer layer channel control end;Double-layer state machine, including inner layer state machine and outer layer state machine, inner layer state machine contains at least two states, inner layer state machine contains first input, first output and second output, first input is connected the sampling signal output end of ADC conversion unit, first output is connected the input channel switching end of ADC conversion unit, second output is connected the first input of outer layer state machine;Outer layer state machine contains first input and first output, and the first output of outer layer state machine is connected outer layer channel control end.The utility model shortens the time of multi-channel ADC sampling conversion, improves ADC efficiency, improves sampling uniformity and certainty.

Description

Technical Field

[0001] This utility model belongs to the field of MCU technology, and in particular relates to a multi-channel ADC module and sampling system. Background Technology

[0002] General-purpose MCUs typically include an ADC for analog-to-digital conversion, supporting multiple input channels. However, considering factors such as internal trace length, parasitic capacitance, and practicality, the number of ADC input channels in common general-purpose MCUs generally does not exceed 20. For applications with a large number of analog signals, external analog switches can be added, and the MCU software can control general-purpose I / O pins to perform multi-channel switching, such as 2-to-1 or 4-to-1. This is equivalent to enabling the general-purpose MCU to support 2x, 4x, or more times the number of ADC input channels, eliminating the need to design and manufacture a dedicated MCU with the corresponding number of input channels. This is precisely the advantage of general-purpose MCUs, which focus on key common requirements to optimize batch costs while also accommodating additional expansion. The sampling working time allocation of existing multi-channel ADCs is shown in the table below. Here, 1#, 2#, and 3# refer to the ADC input channel codes. When the external analog switch is switched to the next group, although from the MCU's internal perspective it is still channels 1#, 2#, and 3#, the source of the external analog signal is different from that of the previous group's 1#, 2#, and 3#, thus achieving ADC channel expansion.

[0003]

[0004] However, analog switches introduce jitter in the input signal during switching, requiring sampling only after signal stabilization. This increases sampling time and consequently lengthens the ADC conversion cycle (the total time for a single ADC unit to complete one full ADC cycle), resulting in low efficiency when performing analog-to-digital conversion on high-speed analog signals with many channels. Furthermore, software-controlled pin switching of external switches introduces unpredictable delays, leading to uneven and uncertain sampling intervals, which hinders subsequent mathematical analysis of the ADC data. Utility Model Content

[0005] Purpose of the utility model: In order to solve the problem that the sampling time is longer and the ADC efficiency is lower in the existing multi-channel ADC module due to signal jitter caused by switching, the utility model provides a multi-channel ADC module and sampling system.

[0006] Technical solution: A multi-channel ADC module, comprising:

[0007] At least one ADC conversion unit;

[0008] At least two inner input channels, both of which are connected to the ADC conversion unit;

[0009] Outer channel control terminal;

[0010] A two-layer state machine includes an inner state machine and an outer state machine. The inner state machine contains at least two states and includes a first input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the sampling signal output terminal of the ADC conversion unit, the first output terminal is connected to the input channel switching terminal of the ADC conversion unit, and the second output terminal is connected to the first input terminal of the outer state machine. The outer state machine includes a first input terminal and a first output terminal, and the first output terminal of the outer state machine is connected to the outer channel control terminal.

[0011] Furthermore, suppose there are K ADC conversion units, N inner input channels, and M inner state machines, then M = N / K.

[0012] Furthermore, it also includes inner layer input channel pins and outer layer channel control pins. The inner layer input channel is connected to the inner layer input channel pins, and the outer layer channel control pin is connected to the outer layer channel control pins. There are at least two inner layer input channel pins and at least one outer layer channel control pin.

[0013] Furthermore, the outer channel control pin is used to output at least one of binary code and enable signal. When multiple outer control pins output enable signals, only one enable signal is valid.

[0014] Furthermore, the ADC conversion unit includes an advance trigger signal generation module, which is used to output a trigger signal before sampling is completed, and the output terminal of the advance trigger signal generation module is connected to the first input terminal of the inner state machine.

[0015] Furthermore, the dual-level state machine is implemented using a counter, with the inner state machine being the low-order bit of the counter and the outer state machine being the high-order bit of the counter. The counting trigger terminal of the counter is connected to the sampling signal output terminal of the ADC conversion unit, and the low-order bit of the counter is used to reset the counter when it reaches full M and trigger the high-order bit of the counter to increment by 1.

[0016] A sampling system includes a main control chip of the aforementioned multi-channel ADC module and at least one analog switch chip. The main control chip includes an inner input channel pin and an outer channel control pin. The inner input channel pin is connected to one end of the analog switch chip, and the outer channel control pin is connected to the control terminal of the analog switch chip.

[0017] Furthermore, the main control chip is an MCU, and the inner layer input channel pins and outer layer channel control pins reuse the MCU's general-purpose I / O pins.

[0018] Furthermore, the analog switch chip includes a multiplexer, which includes a common terminal and a selection control terminal. The inner input channel pin of the main control chip is connected to the common terminal of the multiplexer, and the outer channel control pin is connected to the selection control terminal of the multiplexer. The outer channel control pin is used to output binary code.

[0019] Furthermore, the analog switch chip includes a multi-channel switch, with at least two multi-channel switches. The main control chip also has at least two outer channel control pins. Each multi-channel chip has an enable control terminal. The inner input channel pin of the main control chip is connected to one end of the multi-channel switch, and the outer channel control pin is connected to the enable control terminal of each analog switch chip. The outer channel control pin is used to output a set of enable signals, of which only one is valid.

[0020] Compared with the prior art, the multi-channel ADC module and sampling system provided by this utility model have the following advantages:

[0021] (1) By using an external analog switch chip through a two-layer state machine, the ADC channels are expanded in multiples with N as the basic unit. The external analog switches are uniformly included in the global scheduling through flexible hardware automatic loop, realizing the automatic switching of all ADC channels. This ensures that each internal channel and each external extended channel can have a uniform sampling period, avoiding the gap of software switching. It is especially convenient for the MCU to perform time-correlated digital calculations on the results of multi-channel ADCs, expanding the application field of general MCUs.

[0022] (2) The inner state machine references the sampling completion signal of the ADC conversion unit to control the ADC switch to switch channels in advance, so that the next ADC input channel can have more signal stabilization time, so that the sampling of the next channel does not need to wait for the signal to stabilize for a longer time, thus solving the problem of needing to lengthen the sampling time when the input signal jitters during switch switching.

[0023] (3) The outer state machine also uses the sampling completion signal of the ADC conversion unit to switch the external analog switch chip in advance, so that the next set of analog signals can have more signal stabilization time. This means that the sampling of the next set does not need to wait for the signal to stabilize for a longer time, which solves the problem that the input signal jitter needs to be extended after the switch when the external analog switch is switched. At the same time, the early switching makes the signal more stable when the ADC is sampled, which is conducive to improving the accuracy of the ADC results.

[0024] (4) This solution only requires the addition of a state machine, and the area is usually no more than one ten-thousandth. It makes full use of various existing resources such as the general IO pins of the general MCU, resulting in a low implementation cost. It improves the efficiency of high-speed analog signals with multiple channels when performing ADC, shortens the total time, and ensures the time uniformity of the sampled data.

[0025] (5) Using a state machine to switch channels allows for arbitrary organization of channel switching order according to requirements, and even changes to the sampling weight of individual channels, with some channels sampling extra, which has strong flexibility. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of the sampling system containing a multi-channel ADC module in Example 1;

[0027] Figure 2 This is a schematic diagram of the sampling system containing a multi-channel ADC module in Example 2;

[0028] Figure 3 This is a schematic diagram of the sampling system containing a multi-channel ADC module in Example 3;

[0029] Figure 4 This is a schematic diagram of the sampling system with a multi-channel ADC module in Example 4. Detailed Implementation

[0030] The present invention will be further explained and described below with reference to the accompanying drawings and specific embodiments.

[0031] Example 1:

[0032] A multi-channel ADC module, such as Figure 1 As shown, it includes:

[0033] At least one ADC conversion unit, such as one ADC conversion unit in this embodiment, but there can actually be multiple ADC conversion units, and multiple ADC conversion units can work in parallel and at the same time.

[0034] There are N inner layer input channels, N≥2, and the inner layer input channels are connected to the ADC conversion unit, for example, N=3 in this embodiment;

[0035] Outer channel control terminal;

[0036] A two-level state machine consists of an inner state machine and an outer state machine. The inner state machine contains M states, which can be cyclically switched, where M ≥ 2. For example, in this embodiment, the inner state machine has three states. If there is only one ADC conversion unit, then M is the number of inner input channels. If there are K ADC conversion units, since K ADC conversion units can work simultaneously, M = N / K. Multiple ADC conversion units are preferably operated in parallel simultaneously, but they can also be intentionally operated slightly staggered.

[0037] The inner state machine includes a first input, a first output, and a second output. These three outputs are used for state transition triggering, state transition result output, and M state transition completion output, respectively. The first input is connected to the sampling signal output of the ADC conversion unit, the first output is connected to the input channel switching terminal of the ADC conversion unit, and the second output is connected to the first input of the outer state machine. When the ADC conversion unit outputs a sampling signal, such as a sampling completion signal, the inner state machine is triggered to switch states once via the first input. Each time the inner state machine switches states, the ADC conversion unit switches its input channel to the next channel via the first output. When the inner state machine completes M state transitions, the outer state machine is triggered to switch states via the second output. The outer state machine includes a first input and a first output. The first output of the outer state machine is connected to the outer channel control terminal. The outer state machine switches states under the trigger of the inner state machine by changing the outer channel control terminal via the first output, thereby switching the outer channel. For the state machine, the switch to the next channel is defined by the user and does not necessarily have to be the next channel in terms of physical layout or name; it can be set to any order.

[0038] The multi-channel ADC module also includes inner-layer input channel pins and outer-layer channel control pins. The inner-layer input channels are connected to the inner-layer input channel pins, and the outer-layer channel control pins are connected to the outer-layer channel control pins. In this embodiment, there are three inner-layer input channel pins, meaning all inner-layer input channels are external pins. In practice, it can also support internal input channels of the chip without corresponding external pins.

[0039] The outer channel control pin is used to output binary code, which is used to control the decoding selection of the externally connected multi-to-one analog switch.

[0040] A sampling system includes a main control chip with a built-in multi-channel ADC module as described above and at least one analog switch chip, such as... Figure 1 The diagram shows three analog switch chips. The main control chip includes inner input channel pins and outer channel control pins. The inner input channel pins are connected to one end of the analog switch chip, and the outer channel control pins are connected to the selection control terminal of the analog switch chip. The main control chip can be an MCU, and the inner input channel pins and outer channel control pins can reuse the MCU's general-purpose I / O pins.

[0041] The analog switch chip includes multiplexers, such as three 8-to-1 switch chips used in this embodiment. The number of chips is determined by the ratio of the number of ADC input channels to the number of channels of a single external analog switch chip. Alternatively, a single chip can contain dual-channel or multi-channel 8-to-1 switches. The inner input channel pins of the main control chip are connected to the common terminal (C1) of the 8-to-1 switch; the outer channel control pins of the main control chip are connected to the selection control terminals (S1, S2, S3) of the 8-to-1 switch. The outer channel control pins output binary codes, which are used to select the outer input channel. For example, the three outer channel control pins can output 000, 001, 010, 011, 100, 101, 110, and 111 in sequence, a total of eight combinations, in a cyclical manner. Of course, another order can also be used. This expands the original N channels to N*2. X This embodiment expands the original three-channel ADC to 3*2 input channels. 3 The number of channels has increased eightfold.

[0042] The multi-channel ADC module of this embodiment can switch channels immediately after sampling, rather than waiting until the end of an ADC conversion cycle. The ADC conversion cycle refers to the total time for a single ADC conversion unit to complete one full ADC cycle. The table below shows the time allocation for the multi-channel ADC module of this embodiment. Since signals may fluctuate during conversion, this embodiment advances the switching time, allowing the signal to gradually stabilize during the previous conversion. When the current sampling begins, the signal is sufficiently stable, improving the accuracy of the ADC results and saving time. Using an external state machine to control the external analog switch chip also avoids the uncertain delays in software-controlled switch switching caused by interrupts and DMA events, improving the uniformity and determinism of the ADC sampling interval.

[0043]

[0044] Example 2:

[0045] Compared to Example 1, Example 2 differs in the content output by the outer channel control pin. In Example 2, the outer channel control pin outputs a set of enable signals to drive the enable control terminal (E1) of the external analog switch chip. There are at least two outer channel control pins, such as four in this example, and under stable conditions, only one of these enable signals is active at any given time, allowing selection of one of the connected external analog switch chips to function, meaning only one external analog switch chip is active at any given time.

[0046] like Figure 2As shown, this embodiment has four analog switch chips and four outer channel control pins of the main control chip. Each analog switch chip has an enable control terminal. The inner input channel pins of the main control chip are connected to one end of the switch of each analog switch chip. The outer channel control pins of the main control chip are respectively connected to the enable control terminals of each analog switch chip. The outer channel control pins output a set of enable signals. In a stable state, only one of the enable signals in this set is active at any given time. When one of the analog switch chips is selected, the inner input channel pins select one of the multiple channels connected to that analog switch chip. For example, the four channel control pins output four combinations of 0001, 0010, 0100, and 1000 in sequence and cycle through them. Of course, they can also be in another order. All four or four groups of external analog switch chips have high-level active enable control terminals (the number of analog switch chips is determined by the ratio of the number of ADC input channels to the number of channels of a single external analog switch chip). This expands the original N channels to N*X input channels. In this embodiment, the original three-channel ADC is expanded to 3*4 channels, which means the number of channels is increased fourfold.

[0047] Typically, the inner state machine switches states when the ADC conversion unit completes sampling. Alternatively, the inner state machine can be switched a certain time T1 before the ADC conversion unit completes sampling; T1 is typically no more than 20 nanoseconds. Specifically, the ADC conversion unit includes an advance trigger signal generation module, which outputs a trigger signal before sampling is complete, such as triggering the inner state machine to switch states T1 seconds before sampling is complete. This takes into account the execution time of ADC switching, further striving for earlier switching and earlier signal stabilization, thereby further shortening the sampling period and improving sampling efficiency.

[0048] Example 3:

[0049] Example 3 is a combination of Example 1 and Example 2, such as... Figure 3 As shown, there are four outer channel control pins. Two are used to output binary codes, and the other two are used to output two enable signals. These pins can select which external analog switch chip is active, or which channel of that analog switch chip is activated. In this embodiment, there are four outer channel control pins. The lower two outer channel control pins, as in Embodiment 1, are connected to the channel selection control terminals of the external analog switch chip, which is a 4-to-1 analog switch. The higher two outer channel control pins, as in Embodiment 2, are used for enabling two or more sets of analog switch chips. Each inner input channel pin requires two external analog switches, so in this embodiment, the three inner input channel pins require a total of six analog switches. This expands the original N channels to N*2*2. XIn this embodiment, the original three-channel ADC is expanded to 3*8 channels, which means the number of channels is increased eightfold.

[0050] Example 4:

[0051] The two-layer state machine in Example 4 is implemented using a counter. The inner state machine is the low-order bit of the counter, and the outer state machine is the high-order bit of the counter. The counting trigger terminal of the counter is connected to the sampling signal output terminal of the ADC conversion unit. When the low-order bit of the counter reaches M, it automatically resets and restarts the cycle, while simultaneously triggering the high-order bit of the counter to increment by 1.

[0052] like Figure 4 As shown, the system consists of one ADC conversion unit, eight inner-layer input channel pins, and three outer-layer channel control pins for different encoding methods. A 6-bit counter can be used; the lower three bits of the counter act as the inner-layer state machine, automatically resetting to zero and restarting the cycle when the count reaches eight. The higher three bits of the counter directly serve as the channel control pins for the encoding method. Four dual-channel 8-to-1 analog switch chips are connected externally, each corresponding to one of the eight ADC input channels. A complete cycle of the 6-bit counter perfectly achieves the cycling of 64 ADC channels. If there are two ADC conversion units, the eight ADC input channels can be allocated to these two units, and the counter can... Using a 5-bit counter, the lower 2 bits act as an inner state machine, automatically resetting to zero and restarting the cycle when it reaches 4 bits. A complete cycle of the 5-bit counter can also cycle through 64 ADC channels. If there are 5 ADC input channels, the lower 3 bits of the counter should be set to automatically reset to zero and restart the cycle when it reaches 5 bits. If the outer channel control pin is connected to the enable control pin of an external analog switch chip, the higher 3 bits of the counter need to be decoded to 00000001, 00000010, ... up to 10000000 before outputting a high-level enable pin. If it's a low-level enable, the decoder needs to be inverted before outputting. For the counter scheme, the next channel is preferably the one indicated by its name; otherwise, additional circuitry is needed to change the correspondence.

[0053] In comparison, using a counter to implement state switching is simpler, while the pure state machine schemes in Examples 1 to 3 are more flexible, allowing for arbitrary organization of channel switching order, and even enabling additional sampling weights for individual channels.

Claims

1. A multi-channel ADC module, characterized in that, include: At least one ADC conversion unit; At least two inner input channels, both of which are connected to the ADC conversion unit; Outer channel control terminal; A two-layer state machine includes an inner state machine and an outer state machine. The inner state machine contains at least two states and includes a first input terminal, a first output terminal, and a second output terminal. The first input terminal is connected to the sampling signal output terminal of the ADC conversion unit, the first output terminal is connected to the input channel switching terminal of the ADC conversion unit, and the second output terminal is connected to the first input terminal of the outer state machine. The outer state machine includes a first input terminal and a first output terminal, and the first output terminal of the outer state machine is connected to the outer channel control terminal.

2. The multi-channel ADC module according to claim 1, characterized in that, If there are K ADC conversion units, N inner input channels, and M inner state machines, then M = N / K.

3. The multi-channel ADC module according to claim 1 or 2, characterized in that, It also includes inner layer input channel pins and outer layer channel control pins. The inner layer input channel is connected to the inner layer input channel pins, and the outer layer channel control pin is connected to the outer layer channel control pins. There are at least two inner layer input channel pins and at least one outer layer channel control pin.

4. The multi-channel ADC module according to claim 3, characterized in that, The outer channel control pin is used to output at least one of binary code and enable signal. When multiple outer control pins output enable signals, only one enable signal is valid.

5. The multi-channel ADC module according to claim 1 or 2, characterized in that, The ADC conversion unit includes an advance trigger signal generation module, which is used to output a trigger signal before sampling is completed. The output terminal of the advance trigger signal generation module is connected to the first input terminal of the inner state machine.

6. The multi-channel ADC module according to claim 1 or 2, characterized in that, The dual-level state machine is implemented using a counter. The inner state machine is the low-order bit of the counter, and the outer state machine is the high-order bit of the counter. The counting trigger terminal of the counter is connected to the sampling signal output terminal of the ADC conversion unit. The low-order bit of the counter is used to reset the counter when it reaches the maximum count M and trigger the high-order bit of the counter to increment by 1.

7. A sampling system, characterized in that, It includes a main control chip with a built-in multi-channel ADC module as described in any one of claims 1-6 and at least one analog switch chip. The main control chip includes an inner input channel pin and an outer channel control pin. The inner input channel pin is connected to one end of the analog switch chip, and the outer channel control pin is connected to the control terminal of the analog switch chip.

8. The sampling system according to claim 7, characterized in that, The main control chip is an MCU, and the inner layer input channel pins and outer layer channel control pins reuse the general-purpose I / O pins of the MCU.

9. The sampling system according to claim 7 or 8, characterized in that, The analog switch chip includes a multiplexer, which has a common terminal and a selection control terminal. The inner input channel pin of the main control chip is connected to the common terminal of the multiplexer, and the outer channel control pin is connected to the selection control terminal of the multiplexer. The outer channel control pin is used to output binary code.

10. The sampling system according to claim 7 or 8, characterized in that, The analog switch chip includes a multi-channel switch, with at least two multi-channel switches. The main control chip also has at least two outer channel control pins. Each multi-channel chip has an enable control terminal. The inner input channel pin of the main control chip is connected to one end of the multi-channel switch, and the outer channel control pin is connected to the enable control terminal of each analog switch chip. The outer channel control pin is used to output a set of enable signals, of which only one is valid.

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