A power supply circuit and electronic device

Abstract

The application relates to the communication field and discloses a power supply circuit and electronic equipment. The power supply circuit comprises a power management chip, a filter, an envelope tracking (ET) power amplifier and an average power tracking (APT) power amplifier. The power management chip comprises a first channel, a second channel and a third channel. The power management chip is connected with the envelope tracking (ET) power amplifier through the first channel. The average power tracking (APT) power amplifier comprises a first pin and a second pin. The power management chip is connected with the first pin through the second channel, and the power management chip is connected with the second pin through the third channel. The filter is connected with the output end of the second channel, and the output end of the filter is connected with the first pin. Concurrent control of the envelope tracking (ET) power amplifier and the average power tracking (APT) power amplifier is realized by using the same power chip, the expansion of the communication frequency band range is realized, and the cost is saved while the space occupation of the power supply module is reduced.

Description

Technical Field

[0001] This application relates to the field of communications, and in particular to a power supply circuit and electronic device. Background Technology

[0002] With the widespread adoption of fifth-generation mobile communication technology, 5G communication modules need to support frequency bands from 450MHz to 6GHz. To achieve coverage of all frequency bands, modern RF front-end architectures typically require the simultaneous use of two different types of power amplifiers. For example, envelope tracking (ET) power amplifiers are used to cover the sub-3GHz band; average power tracking (APT) power amplifiers are used to cover the C-band band.

[0003] Because different types of power amplifiers use different power supply methods, power supply chips corresponding to envelope tracking and average power tracking methods are needed to power each type of power amplifier to avoid noise and other issues affecting signal quality. However, since power supply chips are expensive, using two different power supply chips in an electronic device increases costs and occupies more space in the power supply module. Utility Model Content

[0004] The purpose of this application is to provide a power supply circuit and electronic device that uses the same power chip to achieve concurrent control of envelope tracking (ET) power amplifier and average power tracking (APT) power amplifier, thereby expanding the communication frequency band range, saving costs and reducing the space occupied by the power supply module.

[0005] To address the aforementioned technical problems, embodiments of this application provide a power supply circuit, including: a power management chip, a filter, an envelope tracking (ET) power amplifier, and an average power tracking (APT) power amplifier; the power management chip includes: a first channel, a second channel, and a third channel; the power management chip is connected to the envelope tracking (ET) power amplifier through the first channel; the average power tracking (APT) power amplifier includes: a first pin and a second pin; the power management chip is connected to the first pin through the second channel, and the power management chip is connected to the second pin through the third channel; the filter is connected to the output terminal of the second channel, and the output terminal of the filter is connected to the first pin.

[0006] Embodiments of this application also provide an electronic device, including the power supply circuit described above.

[0007] Compared to related technologies, the power supply circuit in this embodiment includes a power management chip, a filter, an envelope tracking (ET) power amplifier, and an average power tracking (APT) power amplifier. The power management chip supplies power to the ET power amplifier via a first channel, and supplies power to the APT power amplifier via second and third channels, respectively, connecting to its first and second pins. Because of the different power supply channels, concurrent control of both the ET and APT power amplifiers can be achieved using the same power management chip, enabling shared power supply. This allows for the expansion of the communication frequency band using two different types of power amplifiers. Using a single power management chip to power both types of amplifiers reduces the number of power management chips required in the power supply circuit, saving costs and reducing space occupied by the power supply module. A filter is connected to the output of the second channel. The filter can filter out high-frequency noise generated when the power management chip supplies power to the APT power amplifier, thereby improving signal quality.

[0008] Additionally, the filter includes a ferrite bead filter and / or a Π-type filter; in the case where the filter includes a ferrite bead filter and a Π-type filter, the ferrite bead filter and the Π-type filter are connected in series.

[0009] In addition, the resistance of the ferrite bead filter is 120Ω.

[0010] In addition, the capacitance level of the Π-type filter is either picofarad or nanofarad.

[0011] In addition, the power supply circuit also includes: a timing controller; the timing controller is connected to the input terminal of the power management chip; the timing controller is used to control the time when the power management chip sends power supply commands through the first channel, the second channel and the third channel, and the first time of sending power supply commands through the first channel is later than the second time of sending power supply commands through the second channel and the third channel.

[0012] In addition, the timing controller is also used to control the time when the power management chip sends power-off commands through the first channel, the second channel and the third channel, and the third time when the power-off command is sent through the first channel is earlier than the fourth time when the power-off command is sent through the second channel and the third channel.

[0013] In addition, the power supply circuit also includes: a first grounding terminal and a second grounding terminal; the first grounding terminal is connected to the first channel, and the second grounding terminal is connected to the second channel and the third channel; the first grounding terminal and the second grounding terminal are spaced apart.

[0014] In addition, the distance between the first grounding terminal and the second grounding terminal is greater than or equal to 2 mm.

[0015] In addition, the power supply circuit also includes a bridging component; the first grounding terminal and the second grounding terminal are connected through the bridging component. Attached Figure Description

[0016] One or more embodiments are illustrated by way of example with reference numerals in the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0017] Figure 1 This is a schematic diagram of a power supply circuit according to the first embodiment of this application; Figure 2 This is a schematic diagram of a power supply circuit according to the second embodiment of this application; Figure 3 This is a schematic diagram of a power supply circuit according to the third embodiment of this application; Figure 4 This is a schematic diagram of a power supply circuit according to the fourth embodiment of this application. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the various embodiments of this application will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will understand that many technical details have been presented in the various embodiments of this application to enable readers to better understand this application. However, the technical solutions claimed in this application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0019] The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of this application. The various embodiments can be combined with and referenced by each other without contradiction.

[0020] The first embodiment of this application relates to a power supply circuit, such as Figure 1 As shown, it includes: a power management chip, a filter, an envelope tracking (ET) power amplifier, and an average power tracking (APT) power amplifier; the power management chip includes: a first channel, a second channel, and a third channel; the power management chip is connected to the envelope tracking (ET) power amplifier through the first channel; the average power tracking (APT) power amplifier includes: a first pin and a second pin; the power management chip is connected to the first pin through the second channel, and the power management chip is connected to the second pin through the third channel; the filter is connected to the output of the second channel, and the output of the filter is connected to the first pin.

[0021] Compared to related technologies, the power supply circuit in this embodiment includes a power management chip, a filter, an envelope tracking (ET) power amplifier, and an average power tracking (APT) power amplifier. The power management chip supplies power to the ET power amplifier via a first channel, and supplies power to the APT power amplifier via second and third channels, respectively, connecting to its first and second pins. Because of the different power supply channels, concurrent control of both the ET and APT power amplifiers can be achieved using the same power management chip, enabling shared power supply. This allows for the expansion of the communication frequency band using two different types of power amplifiers. Using a single power management chip to power both types of amplifiers reduces the number of power management chips required in the power supply circuit, saving costs and reducing space occupied by the power supply module. A filter is connected to the output of the second channel. The filter can filter out high-frequency noise generated when the power management chip supplies power to the APT power amplifier, thereby improving signal quality.

[0022] The filter can be a ferrite bead filter or a Π-type filter, or a ferrite bead filter and a Π-type filter connected in series.

[0023] When the filter is a ferrite bead filter, the ferrite bead filter presents high impedance to high frequencies (e.g., signal frequencies greater than or equal to 1 GHz) and low impedance to DC and low-frequency APT control signals. Therefore, it can effectively block high-frequency noise generated by the power management chip, effectively eliminate the ripple of the power supply signal (VCC) caused by high-frequency noise, and does not affect the passage of normal low-frequency and DC signals.

[0024] In the case of a Π-type filter, the filter consists of two capacitors and one inductor. One capacitor short-circuits some high-frequency noise to ground, and the inductor presents high impedance to high-frequency noise, preventing it from passing through. The other capacitor further filters out residual high-frequency noise, ensuring effective noise removal.

[0025] In cases where the filter includes both a ferrite bead filter and a Π-type filter, the ferrite bead filter and the Π-type filter are connected in series. Alternatively, the ferrite bead can be used as the inductor of the Π-type filter to achieve multiple filtering of high-frequency noise.

[0026] The relevant parameters of the filter are set as follows: the resistance of the ferrite bead filter is 120Ω. The capacitance level of the Π-type filter is either picofarad (PF) or nanofarad (NF).

[0027] The second embodiment of this application relates to a power supply circuit. Compared with the first embodiment, the power supply circuit further includes a timing controller for controlling the timing of power supply commands and power-off commands sent by the power management chip to different channels.

[0028] like Figure 2 As shown, the power supply circuit includes: a timing controller; the timing controller is connected to the input terminal of the power management chip; the timing controller is used to control the timing of the power management chip sending power supply commands through the first channel, the second channel and the third channel, and the first time of sending the power supply command through the first channel is later than the second time of sending the power supply command through the second channel and the third channel.

[0029] Because envelope tracking (ET) power amplifiers and average power tracking (APT) power amplifiers have different response speeds—ET power amplifiers can achieve microsecond (μs) level response speeds, while APT power amplifiers can achieve millisecond (ms) level response speeds—when the power management chip simultaneously sends power supply commands to both the envelope tracking (ET) power amplifier and the average power tracking (APT) power amplifier, the APT power amplifier may still be in an unstable state while the ET power amplifier has already started working, due to the slower startup speed of the APT power amplifier, resulting in an unstable output signal.

[0030] The timing controller ensures, to the greatest extent possible, that the envelope tracking (ET) power amplifier and the average power tracking (APT) power amplifier begin stable operation at the same time by controlling the timing of power supply commands sent to different channels. The power supply command sent to the slower-responding APT power amplifier is sent earlier than the power supply command sent to the faster-responding envelope tracking (ET) power amplifier. When configuring the timing controller, a cross-protocol timing controller can be used to configure the response time of the first channel to be less than or equal to 120 nanoseconds (ns), and the voltage switching delay of the second and third channels to be less than or equal to 200 microseconds (μs). By using GPIO or I²C commands from the power management chip, power is supplied to the second and third channels for 150 microseconds (μs) before power is supplied to the first channel, thus avoiding timing conflicts between the envelope tracking (ET) power amplifier and the average power tracking (APT) power amplifier during power-up.

[0031] Similar to the case of powering down envelope tracking (ET) power amplifiers and average power tracking (APT) power amplifiers, the timing controller is also used to control the timing of power-down commands sent by the power management chip through the first, second, and third channels, with the third time of sending the power-down command through the first channel being earlier than the fourth time of sending the power-down command through the second and third channels.

[0032] When configuring the timing controller, a cross-protocol timing controller can be used to configure the response time of the first channel to be less than or equal to 120 nanoseconds (ns), and the voltage switching delay of the second and third channels to be less than or equal to 200 microseconds (μs). After determining that the power supply to the first channel is off, the power management chip maintains the power supply to the second and third channels for more than 50 microseconds (μs), then uses a low-dropout linear regulator (LDO) to step down the voltage of the third channel to a safe value of 1.8V, and finally disconnects the power to the second and third channels. This allows the average power tracking (APT) power amplifier to be powered off at a lower, safe voltage, preventing component damage caused by excessive voltage.

[0033] The first, second, and third channels mentioned above can be understood as follows: the first channel is the ET Buck channel, the second channel is the APT Buck channel, and the third channel is the LDO channel. The LDO channel and the APT Buck channel work together to form the complete power supply for the average power tracking APT power amplifier. Among them, the Buck channel is responsible for the high-current, high-efficiency main power supply (VCC1), and the LDO channel is responsible for the low-noise auxiliary power supply (VCC2).

[0034] In the second embodiment, the timing controller enables the APT power supply to start early and the ET power supply to be turned off with a delayed voltage reduction, thus avoiding timing conflicts between the APT power supply and the ET power supply.

[0035] The third embodiment of this application relates to a power supply circuit, which, compared with the first and second embodiments, is as follows: Figure 3 As shown, the power supply circuit also includes: a first ground terminal and a second ground terminal; the first ground terminal is connected to the first channel, and the second ground terminal is connected to the second channel and the third channel; the first ground terminal and the second ground terminal are spaced apart. By using a split ground plane design, interference between the envelope tracking ET power supply and the envelope tracking ET power supply can be reduced.

[0036] The distance between the first grounding terminal and the second grounding terminal is greater than or equal to 2 mm. That is, when the first grounding terminal and the second grounding terminal are set on the same circuit board, the positions of the first grounding terminal and the second grounding terminal are spaced apart from each other, and the distance is greater than or equal to 2 mm.

[0037] In addition, the power supply circuit also includes a bridging component; the first ground terminal and the second ground terminal are connected through the bridging component. The bridging component can be a 0Ω resistor, connecting the single-point first ground terminal to the second ground terminal, which serves as the main ground plane. This connection method can reduce noise interference, specifically by approximately 6dB. Furthermore, upon detecting an interference signal, the bridging component is disconnected to determine if the interference signal disappears, thereby identifying whether the interference signal is generated by the envelope tracking ET power supply. If the interference signal disappears upon disconnection of the bridging component, then the interference signal was generated by the envelope tracking ET power supply, thus pinpointing the source of the interference.

[0038] In addition, the power lines in the APT power supply path can be wrapped with a grounding shield to further prevent external signals from interfering with the APT power supply. The distance between the power lines and the grounding shield is greater than or equal to three times the width of the power lines.

[0039] Compared with related technologies, this embodiment reduces the interference of ET power supply to APT power supply by setting the first grounding terminal and the second grounding terminal, as well as setting the grounding shielding layer, thus ensuring the concurrent control of ET power supply and APT power supply.

[0040] The fourth embodiment of this application relates to a power supply circuit, which, compared with the first to third embodiments, is as follows: Figure 4 As shown, the power supply circuit also includes an RF front-end chip.

[0041] The RF front-end chip is connected to the timing controller, and the 400MHz envelope signal channel of the RF front-end chip is directly connected to the first channel (ET Buck channel). The first channel is configured in high-speed ET mode, with a slew rate of 400V / μs and a bandwidth of 30MHz to support 5G envelope tracking.

[0042] During power supply, the RF front-end chip sends synchronization signals and control commands to the timing controller. The synchronization signal provides a time reference for the timing controller, ensuring that it accurately controls the power management chip to send corresponding power-on and power-off commands to each channel at the appropriate time. The control commands instruct the timing controller and power management chip on the configured circuit parameters such as voltage, power, and operating mode, ensuring that the power management chip outputs the required voltage and guarantees appropriate power or frequency band.

[0043] The power management chip mentioned in the first to fourth embodiments above can be the QET5100 chip, the envelope tracking (ET) power amplifier can be the S55281-11, and the average power tracking (APT) power amplifier can be the QPA5581. The timing controller is specifically a processor that integrates software programs for implementing timing control functions.

[0044] In practical applications, the solutions of the first to fourth embodiments described above can be freely combined, and the combined solutions have the technical effects corresponding to the combined solutions.

[0045] Another feasible embodiment of this application relates to an electronic device, including the power supply circuit as described above.

[0046] Compared with related technologies, the electronic device provided in this application embodiment is equipped with the power supply circuit provided in the aforementioned embodiment. Therefore, it also has the technical effects provided in the aforementioned embodiment, and will not be described in detail here.

[0047] Those skilled in the art will understand that the above embodiments are specific embodiments for implementing this application, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of this application.

Claims

1. A power supply circuit, characterized in that, include: Power management chips, filters, envelope tracking (ET) power amplifiers and average power tracking (APT) power amplifiers; The power management chip includes: a first channel, a second channel, and a third channel; The power management chip is connected to the envelope tracking ET power amplifier through the first channel; The average power tracking (APT) power amplifier includes: a first pin and a second pin; The power management chip is connected to the first pin through the second channel, and the power management chip is connected to the second pin through the third channel; The filter is connected to the output of the second channel, and the output of the filter is connected to the first pin.

2. The power supply circuit according to claim 1, characterized in that, The filter includes: a ferrite bead filter and / or a Π-type filter; In the case where the filter includes a ferrite bead filter and a Π-type filter, the ferrite bead filter and the Π-type filter are connected in series.

3. The power supply circuit according to claim 2, characterized in that, The magnetic bead resistance of the filter is 120Ω.

4. The power supply circuit according to claim 2, characterized in that, The capacitance level of the Π-type filter is either picofarad or nanofarad.

5. The power supply circuit according to any one of claims 1 to 4, characterized in that, Also includes: Timing controller; The timing controller is connected to the input terminal of the power management chip; The timing controller is used to control the timing of the power management chip sending power supply commands through the first channel, the second channel, and the third channel, and the first time of sending the power supply command through the first channel is later than the second time of sending the power supply command through the second channel and the third channel.

6. The power supply circuit according to claim 5, characterized in that, The timing controller is also used to control the timing of the power management chip sending power-off commands through the first channel, the second channel, and the third channel, and the third time of sending the power-off command through the first channel is earlier than the fourth time of sending the power-off command through the second channel and the third channel.

7. The power supply circuit according to claim 1, characterized in that, Also includes: First grounding terminal and second grounding terminal; The first grounding terminal is connected to the first channel, and the second grounding terminal is connected to the second channel and the third channel; The first grounding terminal and the second grounding terminal are spaced apart.

8. The power supply circuit according to claim 7, characterized in that, The distance between the first grounding terminal and the second grounding terminal is greater than or equal to 2 mm.

9. The power supply circuit according to claim 7, characterized in that, Also includes: Bridging components; The first grounding terminal and the second grounding terminal are connected by the bridging component.

10. An electronic device, characterized in that, include: The power supply circuit as described in any one of claims 1 to 9.

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