Zero-downtime multi-mode network security isolation device

Abstract

The utility model discloses a zero interruption multi -mode network security isolation device, including the case, and be located the front panel control unit of case front end, be located the modularization subcard bin of case inside, backboard logic circuit, three level or door logic synthetic unit, hardware Bypass relay array, communication module bin, double main control unit, hardware watchdog circuit and power -down detection circuit, the front panel control unit is equipped with physical Bypass switch and network port, the utility model discloses network security isolation device can complete subcard hot plug mode switching in the short time in the field, and relay switch is less than or equal to 50ms, whole process zero interruption, improve work efficiency and guarantee network stability. When main control unit failure or power drop, hardware Bypass mechanism can respond within 50ms, ensure that the service does not lose packet. The hardware watchdog of independent 5V DC-DC power supply automatically triggers the relay straight -through after the whole machine power -down, need not field intervention, reduce maintenance cost. 1U / 2U case is compatible with gigabit / terabit interface, and it is convenient for subsequent smooth upgrade.

Description

Technical Field

[0001] This utility model patent relates to the field of network security equipment hardware structure, and in particular to a zero-interruption multi-mode network security isolation device. Background Technology

[0002] Existing network security isolation devices (such as SysKeeper-2000, ASM6000 series, etc.) have the following shortcomings: The network port is fixed, and switching the working mode (bridging, policy routing, MVG, 802.1x) requires replacing the entire machine or powering off and restarting, which will cause service interruption. There is no hardware-level escape mechanism when the main control unit fails at a single point, and the network interruption time is greater than minutes. The lack of off-band management channels results in high on-site maintenance costs. There is no unified hardware bypass relay array inside the chassis. Currently, software bypass relies on the CPU, which results in large switching latency and is unreliable. Utility Model Content

[0003] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a zero-interruption multi-mode network security isolation device.

[0004] To address the problems of existing technologies, this utility model discloses a zero-interruption multi-mode network security isolation device, including a chassis and a front panel control unit located at the front of the chassis. Inside the chassis are a modular sub-card compartment, a backplane logic circuit, a three-level OR gate logic synthesis unit, a hardware Bypass relay array, a communication module compartment, a dual main control unit, a hardware watchdog circuit, and a power-down detection circuit. The front panel control unit includes an OLED status screen, a physical Bypass switch, and a network port. The physical Bypass switch is connected to the three-level OR gate logic synthesis unit, which is connected to the hardware Bypass relay array. The hardware Bypass relay array is connected to the network port. The dual main control unit, the hardware watchdog circuit, and the power-down detection circuit are all connected to the three-level OR gate logic synthesis unit. The dual main control unit is connected to the reset pulse port of the hardware watchdog circuit. The communication module compartment is connected to the dual main control unit. The modular sub-card compartment is connected to the backplane logic circuit, and the backplane logic circuit is connected to the OLED status screen.

[0005] Furthermore, the number of physical bypass switches is three; the three-level OR gate logic synthesis unit is composed of three cascaded 74HCT32 four-channel two-input OR gate chips, and the OR gate circuits of each chip together form a first-level logic; the signal output terminals (Bypass_SW1, Bypass_SW2, Bypass_SW3) of the three physical bypass switches are respectively connected to the input terminals of the corresponding OR gate circuits in the third-level logic.

[0006] Furthermore, the number of network ports is six, and the hardware Bypass relay array includes three double-pole double-throw relay circuits, each of which is connected to two network ports.

[0007] Furthermore, each double-pole double-throw relay circuit includes a TQ2-5V double-pole double-throw relay, an SMAJ5.0A unidirectional TVS diode, a PC817 optocoupler, a current-limiting resistor R8, and a 2N3904 transistor. The TQ2-5V double-pole double-throw relay is connected to two network ports, and the SMAJ5.0A unidirectional TVS diode is connected in parallel across the coil of the TQ2-5V double-pole double-throw relay. The PC817 optocoupler is connected to the base of the 2N3904 transistor through the current-limiting resistor R8. The emitter of the 2N3904 transistor is grounded, and the collector of the 2N3904 transistor is connected to the positive terminal of the SMAJ5.0A unidirectional TVS diode.

[0008] Furthermore, the power-down detection circuit includes a TL431 parallel regulator, an LM393 dual-channel voltage comparator, resistors R1, R2, R3, R4, and R7, and capacitors C1 and C2. The REF terminal of the TL431 parallel regulator is connected to resistors R3 and R4 respectively. The power supply voltage VCC is divided by resistors R1 and R2, and the sampling point is connected to the inverting terminal of the LM393 dual-channel voltage comparator. Capacitor C1 is connected in parallel with resistor R4, and capacitor C2 is connected in parallel with capacitor R2. Resistor R7 establishes a positive feedback path from the output terminal of the LM393 dual-channel voltage comparator to the inverting terminal.

[0009] Furthermore, the hardware watchdog circuit includes a CD4060 oscillator, a 2N3906 transistor, resistors R13 and R14, and an RC network of the circuit. The collector of the 2N3906 transistor is connected to the reset pulse port of the CD4060 oscillator. Resistors R13 and R14 provide base bias for the 2N3906 transistor, and the RC network of the circuit is connected to the CD4060 oscillator.

[0010] Furthermore, the modular daughter card slot is connected to the backplane logic circuit via a PCIe x8 gold finger, and outputs the daughter card type code to the backplane logic circuit via a 3-bit hardware ID bus.

[0011] Furthermore, the backplane logic circuit is equipped with a 74HC138 decoder, which is used to convert the sub-card ID code into a type signal and transmit it to the OLED status screen of the front panel control unit through the display data line for real-time display of the sub-card type.

[0012] Furthermore, the communication module compartment is connected to the dual main control units via a Mini-PCIe bus to form an independent out-of-band management channel; the communication module compartment is also equipped with 4G / 5G / Wi-Fi / LoRa modules, which are powered by independent 5V DC-DC.

[0013] Furthermore, the dual master control unit includes master control unit A and master control unit B, which are interconnected via a backplane PCIe x4 and GPIO heartbeat line.

[0014] The beneficial effects of this utility model are: This utility model provides a network security isolation device that can switch between multiple network access modes without restarting, disassembling, or disconnecting from the network, and has a hardware-level fault escape channel; It can quickly switch between daughter card hot-swap modes on-site, with relay switching within ≤50 ms and zero interruption throughout the process, greatly improving work efficiency and ensuring network stability. Secondly, in the event of a main control unit failure or power drop, the hardware bypass mechanism can respond within 50 ms, ensuring no packet loss. Furthermore, the independent 5V DC-DC powered hardware watchdog can automatically trigger relay pass-through after a power outage, requiring no on-site intervention and significantly reducing maintenance costs. The 1U / 2U chassis is compatible with Gigabit / 10 Gigabit interfaces, facilitating smooth future upgrades. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of the overall hardware topology of this utility model; Figure 2 This is a schematic diagram of the front panel control unit of this utility model; Figure 3 This is a schematic diagram of the modular sub-card compartment sub-card A connection of this utility model; Figure 4 This is a schematic diagram of the modular sub-card compartment sub-card B connection of this utility model; Figure 5 This is a schematic diagram of the modular sub-card compartment sub-card C connection of this utility model; Figure 6 This is a schematic diagram of the power failure detection circuit, double-pole double-throw relay circuit, and OR gate circuit of this utility model; Figure 7 This is a schematic diagram of a single relay signal control according to this utility model; Figure 8 This is a schematic diagram of the three sets of relay signal control of this utility model; Figure 9 This is a schematic diagram of the dual main control unit and communication module compartment of this utility model; Figure 10 This is a schematic diagram of the hardware watchdog circuit of this utility model. Detailed Implementation

[0016] The present invention will be further described below with reference to the accompanying drawings. The following embodiments are only used to more clearly illustrate the technical solution of the present invention, and should not be used to limit the scope of protection of the present invention.

[0017] This utility model discloses a zero-interruption multi-mode network security isolation device, including a chassis, a front panel control unit located at the front of the chassis, and a modular sub-card compartment, backplane logic circuit, three-level OR gate logic synthesis unit, hardware Bypass relay array, communication module compartment, dual main control unit, hardware watchdog circuit and power failure detection circuit located inside the chassis; the front panel control unit is equipped with an OLED status screen, physical Bypass switch and network port; the chassis is a standard 1U / 2U 19-inch chassis.

[0018] like Figure 1 The diagram illustrates the physical connections and signal flow between the various functional modules: The modular daughter card compartment allows hot-swappable daughter cards to connect to the backplane via PCIe x8 gold fingers and output daughter card type codes to the backplane logic circuit via a 3-bit hardware ID bus (CARD_ID[2:0]).

[0019] The backplane logic circuit (including a 74HC138 decoder) converts the daughter card ID code into a type signal and transmits it to the OLED status screen of the front panel control unit via a display data line (such as SPI / I²C) for real-time display of the daughter card type.

[0020] The communication module compartment is connected to the dual main control units via a Mini-PCIe bus, forming an independent out-of-band management channel.

[0021] The dual master control units achieve state synchronization through the GPIO heartbeat line and output three master control bypass control signals (GPIO0, GPIO1, GPIO2) to the three-level OR gate logic synthesis unit respectively.

[0022] The power failure detection circuit outputs the POWER_FAIL signal line, the hardware watchdog circuit outputs the Bypass_CTL signal line, and the front panel physical Bypass switch outputs three Bypass_SW (Bypass_SW1, Bypass_SW2, Bypass_SW3) signal lines. These three, along with the main control GPIO signal, are input to the three-level OR gate logic synthesis unit.

[0023] The three-level OR gate logic synthesis unit outputs three relay drive signals (K1_DRV, K2_DRV, K3_DRV), which drive three independent hardware bypass relay arrays (K1, K2, K3) respectively, realizing hardware-level bypass control of the network port pairs (ETH0 / 1, ETH2 / 3, ETH4 / 5).

[0024] like Figure 2 As shown, the front panel control unit includes multiple physical bypass switches, and each physical bypass switch corresponds one-to-one with a hardware bypass relay array. Each physical bypass switch is configured to receive user operations and independently output a forced pass-through signal or an automatic control signal to the priority control circuit of its corresponding set of hardware bypass relays, wherein the forced pass-through signal has the highest priority; the front panel control unit is also equipped with a Console port RJ45 (RS-232 serial port maintenance port), dual USB 3.0 ports (Host / Device maintenance ports, which do not forward service data) and an indicator light area.

[0025] like Figures 3-5 As shown, the modular daughter card slot allows daughter cards to be inserted into the backplane via PCIe x8 gold fingers, supporting three sizes: Sub-card A: 4 x Gigabit RJ45 Ethernet ports for bridging / transparent mode; Sub-card B: 2 x Gigabit SFP optical ports + 2 x Gigabit RJ45 electrical ports, used for policy routing / MVG mode; Sub-card C: 2 x 10 Gigabit SFP+ optical ports, for high-bandwidth scenarios.

[0026] The daughter card replacement time is less than 5 seconds, no power interruption is required, and the interface mode is automatically identified by the pin level of the daughter card hardware ID.

[0027] All daughter cards are 167 mm long and 111 mm high, conforming to the standard half-height PCIe card size.

[0028] like Figure 6 The schematic diagram of the hardware bypass relay array (three isomorphic groups) is shown below: Three identical sets of double-pole double-throw (DPDT) relays are used, corresponding to port pairs ETH0 / 1, ETH2 / 3, and ETH4 / 5 respectively, and connected to the six physical sockets (network ports) of the front panel control unit RJ45-0 to RJ45-5. Adjacent ports share one set of relays.

[0029] The complete drive circuit diagram for a single Bypass relay includes a power-down detection circuit, an OR gate circuit (a three-level OR gate logic synthesis unit), and a double-pole double-throw relay circuit (hardware Bypass relay).

[0030] Power-down detection circuit: Composed of a TL431 parallel voltage regulator and an LM393 dual-channel voltage comparator. The REF terminal of the TL431 parallel voltage regulator is divided by resistors R3 and R4, resulting in a cathode regulated output of 2.495V × (R3 + R4) / R4 ≈ 3.3V, which serves as the precise reference for the non-inverting input of the LM393 dual-channel voltage comparator. The power supply voltage VCC is divided by resistors R1 and R2, and the sampling point is connected to the inverting input of the LM393 dual-channel voltage comparator. Capacitors C1 and C2 act as high-frequency filters. Resistor R7 establishes a positive feedback path from the output to the inverting input, creating hysteresis to suppress false triggering caused by input signal jitter. By comparing the voltages at the non-inverting and inverting inputs, the power-down detection signal is obtained at the output of the LM393 dual-channel voltage comparator. When VCC drops <10%, the voltage divider point of resistors R1 and R2 is higher than 3.3V, the non-inverting input is lower than the inverting input, the output transistor inside the LM393 dual voltage comparator is cut off, and the output is pulled high through the pull-up resistor. When VCC drops ≥10%, the voltage divider point of resistors R1 and R2 is lower than 3.3V, the inverting input is lower than the non-inverting input, the output transistor inside the LM393 dual voltage comparator is turned on, and the output is forced low. Timing simulation shows that the high-to-low switching delay of the LM393 dual voltage comparator output is approximately 60 ns.

[0031] OR gate circuit: The three-level OR gate logic synthesis unit is composed of three cascaded 74HCT32 four-channel two-input OR gate chips (U3, U4, U5) to form a three-level logic. The first-level logic (U3) performs a logical OR operation on the main control GPIO signal (such as GPIO0) and the power-down detection signal (POWER_FAIL). The output signal of the first level is connected to the second-level logic (U4), which performs a logical OR operation on the signal output by the hardware watchdog forced pass-through circuit (BYPASS_CTL). The output signal of the second level is then connected to the third-level logic (U5), which performs a logical OR operation on the physical Bypass switch signal (such as Bypass_SW1). The signal output by the third-level logic (K1_DRV) serves as the final trigger signal, used to drive the subsequent relay drive circuit.

[0032] The priority settings for the three-level OR gate logic synthesis unit are as follows: the physical Bypass switch signal has the highest priority; as long as it is high, regardless of the status of other signals, the third-level OR gate (U5) will directly output a high level (K1_DRV). The BYPASS_CTL signal has the next highest priority, higher than the main control GPIO signals. The typical propagation delay of each 74HCT32 chip is approximately 27 ns, ensuring fast response to obstacle signals.

[0033] (Note: The diagram only shows the three-level OR gate synthesis unit corresponding to the first group of relays (K1). The circuit structure of the other two groups of units is exactly the same.) Double-pole double-throw relay circuit: A TQ2-5V double-pole double-throw relay is used to control the two paths ETH0 and ETH1. Its inherent pull-in time and inherent release time (without diodes in parallel) are both approximately 4ms. The control signal output from the OR gate first achieves safety isolation through a PC817 optocoupler, and then drives a 2N3904 transistor through a current-limiting resistor R8, causing the 2N3904 transistor to operate in the saturation or cutoff region. The on / off state of the relay coil is controlled by the switching of the collector current, completing the full-link function of isolation, amplification, and switching control. An SMAJ5.0A unidirectional TVS diode connected in parallel across the coil clamps the reverse induced voltage to approximately 9V at the moment of power failure, reducing switching delay and protecting the 2N3904 transistor. When the control signal is low or power is off, the 2N3904 transistor is cut off, the coil is de-energized, and ETH0 and ETH1 are directly connected to ETH0' and ETH1' respectively. When the control signal is high, 2N3904 is turned on, the relay coil is energized, and ETH0 and ETH1 are switched to the normally open terminals BYPASS1 and BYPASS2, realizing power-off pass-through.

[0034] like Figure 7 and Figure 8 As shown, each array contains double-pole double-throw relays (K1, K2, K3), corresponding to port pairs ETH0 / 1, ETH2 / 3, and ETH4 / 5, respectively.

[0035] Its driving circuit consists of: a. Power failure detection circuit: It adopts a TL431 parallel regulator and an LM393 dual voltage comparator. When the power supply voltage drops by ≥10%, it outputs a high-level trigger signal. b. Three-level OR gate circuit: Three 74HCT32 OR gate chips are cascaded to perform logical OR operation on the main control GPIO signal, power failure detection signal, hardware watchdog BYPASS_CTL signal and physical Bypass switch signal; c. Relay drive circuit: The TQ2-5V relay coil is driven by a 2N3904 transistor. An SMAJ5.0A TVS diode is connected in parallel across the coil to suppress reverse peak voltage. The switching time is ≤50ms, and no MCU is involved in the control throughout the process.

[0036] The relay coil is driven by a three-stage OR gate: The first-level 74HCT32: performs a logical OR operation between the "main control GPIO" and the "power failure detection signal (POWER FAIL)"; The second stage 74HCT32: performs a logical OR operation between the output of the first stage and the "hardware watchdog BYPASS_CTL signal"; Level 3 74HCT32: Performs a logical OR operation between the Level 2 output and the "Physical Bypass Switch (Bypass_SW)"; the Physical Bypass Switch signal line is connected to the OR gate without any controllable logic to form the highest priority; Switching time ≤ 50 ms; Supports dual pass-through modes: Power failure direct connection: Coil de-energized → normally closed contact closes → link is directly connected; Forced bypass: The physical bypass switch is set to the "up" position → skipping the first two levels of logic, directly energizing the coil through the third-level OR gate → normally open contact closes → link bypass.

[0037] The three independent hardware bypass relay arrays are each controlled independently by three GPIO signal lines of the main control unit. Each GPIO signal, along with the power-down detection signal, hardware watchdog signal, and physical bypass switch signal, is combined through a three-level OR gate circuit to drive the relay.

[0038] like Figure 9 As shown, a top view of the internal structure of the chassis (dual main control units + communication module compartment): Dual master control units: Master control unit A and master control unit B are interconnected via backplane PCIe x4 and GPIO heartbeat lines for hardware status synchronization; relay switching is driven only by three levels of hardware or gates.

[0039] Communication module compartment: The Mini-PCIe slot supports 4G / 5G / Wi-Fi / LoRa modules. The modules are installed vertically, with the SMA antenna extending out of the rear panel. The modules are powered by an independent 5V DC-DC power supply (input 12V main power supply, output isolated from the main controller). During power failure, the 4G module remains in standby mode and is forced to pass through via a hardware watchdog (CD4060 timeout → BYPASS_CTL trigger).

[0040] Relay array: Three sets of DPDT relays are attached to the network port PCB and controlled by BYPASS_CTL (3 GPIOs), with a switching time of ≤ 50 ms.

[0041] Size and heat dissipation: 440 mm × 44 mm (1U) or 88 mm (2U) in outline, with front and rear exhaust airflow, and all components are located within the airflow channel.

[0042] like Figure 10 As shown, the hardware watchdog circuit implements the watchdog function through a CD4060 oscillator and a 2N3906 transistor. The core function of the circuit is to receive low pulses from the main controller, pull the RESET signal high through the 2N3906 transistor, clear the count of the CD4060 oscillator, and ensure the timer restarts. Resistors R13 and R14 provide base bias for the 2N3906 transistor, causing it to conduct when CLK_IN is low, thereby triggering a reset. The RC network of the circuit (composed of resistors R11 and R12, and capacitor C3) sets the oscillation period. This clock frequency setting causes the Q14 pin of the CD4060 oscillator to output a high level after approximately 120 seconds, triggering the BYPASS_CTL output to a high level and initiating the forced pass-through mechanism, ensuring that pass-through can still be triggered when the entire device is powered off. Example

[0043] This device is deployed in Zone II ↔ Zone III of the power monitoring system.

[0044] 1. Sub-card replacement When the maintenance personnel open the chassis cover, remove sub-card A, and insert sub-card B: Hardware identification: The 3-bit hardware ID pin output level combination of the daughter card gold finger (such as "010" corresponding to daughter card B) is directly input to the backplane hard-wired logic circuit.

[0045] 2) Signal decoding and display: The 74HC138 decoder on the back panel converts the ID combination into a daughter card type signal, which is then driven by the 74LVC245 level conversion chip to display "Daughter card B has been recognized" on the OLED screen.

[0046] 3) Link switching: The decoder output generates a 50ms high-level pulse through an RC delay circuit (R=10kΩ±5%, C=4.7μF±10%) → the 2N3904 transistor is cut off → the TQ2-5V relay coil is de-energized → the normally closed contact is closed, realizing zero-interruption switching.

[0047] 2. Escape from main control failure (Level 3 pure hardware or gate control) 1) Signal source priority – Three physical bypass switches (Bypass_SW, highest priority) – Hardware watchdog BYPASS_CTL (secondary priority) – Power failure detection POWER_FAIL and main controller GPIO (lowest priority) The main control unit controls three sets of DPDT relays via three independent GPIO signal lines (GPIO0 / 1 / 2). Each GPIO signal is synthesized through a three-stage OR gate logic to drive the corresponding relay coil. During normal operation: Output high level (3.3V / 5V): Maintain link isolation. Output low level (0V): Triggers link shoot-through 2) Logic composition: Level 1 74HCT32: Main controller GPIO OR POWER_FAIL.

[0048] Second stage 74HCT32: First stage output OR BYPASS_CTL.

[0049] Level 3 74HCT32: Level 2 output OR Bypass_SW.

[0050] 3) Driver execution Third-stage output → 2N3904 saturation → TQ2-5V relay action (≤50ms, including 4ms transistor delay + 6ms relay engagement time).

[0051] 3. Hardware watchdog for communication module compartment forces pass-through The hardware watchdog circuit of the communication module compartment is designed based on the CD4060 oscillator. The main controller needs to send a low-level reset pulse every 2 seconds. If no pulse is received within 2 consecutive minutes, the Q14 pin triggers the BYPASS_CTL to output a high level, forcing the relay to switch to the pass-through state.

[0052] Independent power supply design: The watchdog circuit is powered by a 12V to 5V DC-DC module, and the output is isolated from the main controller; the module has a built-in 10,000μF energy storage capacitor (supports a load of 10mA for ≥120 seconds) to ensure that the pass-through action is completed after power failure.

[0053] 4. Relay Group Control Logic 1) Hardware control architecture The three sets of DPDT relays (ETH0 / 1, ETH2 / 3, ETH4 / 5) are independently controlled by the main controller's GPIO0 / 1 / 2 respectively: GPIO0 → drives the ETH0 / 1 relay (K1) via a three-stage OR gate. GPIO1 → Drives ETH2 / 3 relay (K2) GPIO2 → Drives ETH4 / 5 relay (K3) Note: Each control circuit group includes... Figure 6 The power-down detection (TL431+LM393), three-stage OR gate (74HCT32×3), and relay drive circuit (2N3904+TQ2-5V) shown ensure synchronous operation at the hardware level.

[0054] 2) Implementation of business isolation ETH0 / 1: Connecting power generation control operations (Zone II → Zone III) Default mode: Hardware isolation (master controller GPIO0 = high level) Emergency bypass: triggered by physical bypass switch overload or watchdog timeout. ETH2 / 3: Carries video surveillance data and supports on-demand pass-through in policy routing mode; ETH4 / 5: Dedicated management channel, automatically bypassed in case of power failure (POWER_FAIL takes precedence).

[0055] 3) Fault isolation verification Actual testing shows that when daughter card A (4 x Gigabit RJ45) is inserted, the system can recognize and enable both ETH0 / 1 and ETH2 / 3 ports. At this time, if a short circuit fault is artificially injected into the ETH2 / 3 port pair, only the corresponding relay group (K2) triggers a protective pass-through (response time ≤ 50ms); ETH0 / 1 remains in normal working condition; operating the corresponding physical bypass switch (Bypass_SW1) can still force the ETH0 / 1 port pair into the pass-through state with the highest priority, unaffected by any other signals.

[0056] When daughter card B (2×SFP + 2×RJ45) is inserted, the system only enables ETH0 / 1 and ETH2 / 3, and the fault isolation behavior is the same as described above.

[0057] 5. Indicator light status (direct hardware connection) PWR (green): Directly driven by 12V power supply, it lights up under normal conditions.

[0058] BYPASS (yellow): The output of the third-stage OR gate is driven by a 220Ω current-limiting resistor.

[0059] HA (dual-color): 74HC74 latch master / slave status (red: master controller A is faulty, green: master controller B is active).

[0060] ALM (Red): 74HCT32 OR gate triggered by priority: 1) Physical Bypass Switch Force Signal (Highest Priority) 2) Hardware watchdog timeout signal (BYPASS_CTL) 3) Dual master control heartbeat signal loss.

[0061] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Additionally, in the description of this utility model, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, in the accompanying drawings of this utility model, the filling pattern is only used to distinguish the layers and is not used for any other limitation.

[0062] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A zero-interruption multi-mode network security isolation device, characterized in that, The system includes a chassis, a front panel control unit located at the front of the chassis, and modular sub-card compartments, backplane logic circuits, a three-level OR gate logic synthesis unit, a hardware bypass relay array, a communication module compartment, dual main control units, a hardware watchdog circuit, and a power-down detection circuit located inside the chassis. The front panel control unit has an OLED status screen, a physical bypass switch, and a network port. The physical bypass switch is connected to the three-level OR gate logic synthesis unit, which is connected to the hardware bypass relay array. The hardware bypass relay array is connected to the network port. The dual main control units, the hardware watchdog circuit, and the power-down detection circuit are all connected to the three-level OR gate logic synthesis unit. The dual main control units are connected to the reset pulse port of the hardware watchdog circuit. The communication module compartment is connected to the dual main control units. The modular sub-card compartment is connected to the backplane logic circuit, and the backplane logic circuit is connected to the OLED status screen.

2. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The number of physical bypass switches is three; the three-level OR gate logic synthesis unit is composed of three cascaded 74HCT32 four-channel two-input OR gate chips, and the OR gate circuits of each chip together form a first-level logic; the signal output terminals of the three physical bypass switches are respectively connected to the input terminals of the corresponding OR gate circuits in the third-level logic.

3. The zero-interruption multi-mode network security isolation device according to claim 2, characterized in that, The number of network ports is six, and the hardware Bypass relay array includes three double-pole double-throw relay circuits, each of which is connected to two network ports.

4. The zero-interruption multi-mode network security isolation device according to claim 3, characterized in that, Each double-pole double-throw relay circuit includes a TQ2-5V double-pole double-throw relay, an SMAJ5.0A unidirectional TVS diode, a PC817 optocoupler, a current-limiting resistor R8, and a 2N3904 transistor. The TQ2-5V double-pole double-throw relay is connected to two network ports, and the SMAJ5.0A unidirectional TVS diode is connected in parallel across the coil of the TQ2-5V double-pole double-throw relay. The PC817 optocoupler is connected to the base of the 2N3904 transistor through the current-limiting resistor R8. The emitter of the 2N3904 transistor is grounded, and the collector of the 2N3904 transistor is connected to the positive terminal of the SMAJ5.0A unidirectional TVS diode.

5. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The power failure detection circuit includes a TL431 parallel regulator, an LM393 dual-channel voltage comparator, resistors R1, R2, R3, R4, and R7, and capacitors C1 and C2. The REF terminal of the TL431 parallel regulator is connected to resistors R3 and R4 respectively. The power supply voltage VCC is divided by resistors R1 and R2, and the sampling point is connected to the inverting terminal of the LM393 dual-channel voltage comparator. Capacitor C1 is connected in parallel with resistor R4, and capacitor C2 is connected in parallel with capacitor R2. Resistor R7 establishes a positive feedback path from the output terminal of the LM393 dual-channel voltage comparator to the inverting terminal.

6. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The hardware watchdog circuit includes a CD4060 oscillator, a 2N3906 transistor, resistors R13 and R14, and an RC network. The collector of the 2N3906 transistor is connected to the reset pulse port of the CD4060 oscillator. Resistors R13 and R14 provide base bias for the 2N3906 transistor. The RC network of the circuit is connected to the CD4060 oscillator.

7. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The modular daughter card compartment is connected to the backplane logic circuit via a PCIe x8 gold finger and outputs the daughter card type code to the backplane logic circuit via a 3-bit hardware ID bus.

8. The zero-interruption multi-mode network security isolation device according to claim 7, characterized in that, The backplane logic circuit is equipped with a 74HC138 decoder, which is used to convert the sub-card ID code into a type signal and transmit it to the OLED status screen of the front panel control unit through the display data line for real-time display of the sub-card type.

9. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The communication module compartment is connected to the dual main control units via a Mini-PCIe bus, forming an independent out-of-band management channel; the communication module compartment is also equipped with 4G / 5G / Wi-Fi / LoRa modules, which are powered by independent 5V DC-DC.

10. The zero-interruption multi-mode network security isolation device according to claim 1, characterized in that, The dual master control unit includes master control unit A and master control unit B, which are interconnected via PCIe x4 and GPIO heartbeat lines on the backplane.

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