Ethernet data packet capturing, analyzing and forwarding device

Abstract

The present disclosure provides an Ethernet data packet capturing, analyzing and forwarding device, comprising an Ethernet mirroring module, a first Ethernet protocol interface module, an embedded host module, a second Ethernet protocol interface module and a CANFD interface module. The embedded host module is used as the control core of the Ethernet data packet capturing, analyzing and forwarding device. The Ethernet mirroring module is used to capture and obtain the Ethernet data of the measured Ethernet communication equipment. The captured data is analyzed and converted by the logic analysis and data processing of the host module, and then is forwarded through the Ethernet mode or the CANFD mode. The Ethernet data packet capturing, analyzing and forwarding device has the advantages of simple circuit structure, small size, low power consumption, flexible external interface, low cost and the like.

Description

Technical Field

[0001] This disclosure relates to the field of Ethernet communication technology, and in particular to an Ethernet data packet capture, parsing and forwarding device. Background Technology

[0002] Ethernet communication is a massive data exchange process, playing a crucial role, especially in today's interconnected network era. The bit error rate (BER) of data exchange between various communication devices is a critical indicator for evaluating Ethernet communication quality. To ensure the reliability of communication equipment, extensive testing and verification of Ethernet communication are necessary, along with evaluation of Ethernet communication data. To assess the BER of each communication device, packet capture of Ethernet communication data is required, followed by further analysis and forwarding to ultimately evaluate the quality of Ethernet communication.

[0003] In the testing of Ethernet communication products, to evaluate the bit error rate of data exchange among various communication devices, it is necessary to acquire Ethernet data from each device in real time during Ethernet communication. Typically, this requires specialized equipment, such as network analyzers or network packet capture tools (Wireshark). These acquisition devices are complex, bulky, and inconvenient to integrate, and the acquired Ethernet data is stored internally without forwarding capabilities. Utility Model Content

[0004] The purpose of this disclosure is to provide an Ethernet data packet capture, parsing, and forwarding device to solve the problems existing in the prior art.

[0005] The embodiments of this disclosure adopt the following technical solution: an Ethernet data packet capture, parsing and forwarding device, comprising: an Ethernet mirroring module, used to capture Ethernet data packets output by a communication device, and perform mirroring processing on the Ethernet data packets to output mirrored data packets; a first Ethernet protocol interface module, used to receive the mirrored data packets, and perform decapsulation processing on the mirrored data packets based on the Ethernet protocol to output decapsulated data units; an embedded main control module, used to receive the decapsulated data units, and parse the decapsulated data units to output data units to be encapsulated to a second Ethernet protocol interface module or a CANFD interface module; a second Ethernet protocol interface module, used to encapsulate the data units to be encapsulated based on the Ethernet protocol to form Ethernet data packets for output; and a CANFD interface module, used to encapsulate the data units to be encapsulated based on the CANFD protocol to form CANFD data packets for output.

[0006] In some embodiments, the Ethernet mirroring module includes: at least one RJ45 interface, an isolation transformer, and a switch chip; wherein the RJ45 interface is connected to the primary end of the isolation transformer, the secondary end of the isolation transformer is connected to the input pin of the switch chip, and the output pin of the switch chip is connected to the first Ethernet protocol interface module.

[0007] In some embodiments, the switch chip is model FC2012NL.

[0008] In some embodiments, the first Ethernet protocol interface module includes: a first Ethernet protocol interface chip, wherein the input pins of the first Ethernet protocol interface chip are connected to the output pins of the switch chip, and the output pins of the first Ethernet protocol interface chip are connected to the embedded main control module.

[0009] In some embodiments, the embedded master control module includes: a microprocessor, a reset circuit, and a clock circuit; wherein, the input pin of the microprocessor is connected to the output pin of a first Ethernet protocol interface chip, the output pin of the microprocessor is connected to a second Ethernet protocol interface module and the CANFD interface module, the clock circuit is used to provide a clock signal to the microprocessor, and the reset circuit is used to perform a reset operation on the microprocessor.

[0010] In some embodiments, the microprocessor is model SM9B000MBL.

[0011] In some embodiments, the second Ethernet protocol interface module includes: a second Ethernet protocol interface chip, wherein the input pins of the second Ethernet protocol interface chip are connected to the output pins of the microprocessor, and the output pins of the second Ethernet protocol interface chip are connected to an RJ45 interface.

[0012] In some embodiments, both the first Ethernet protocol interface chip and the second Ethernet protocol interface chip are of model SM5100.

[0013] In some embodiments, the CANFD interface module includes: a CANFD controller, a CANFD interface chip, and a CANFD interface, wherein the input pins of the CANFD interface chip are connected to the output pins of the microprocessor, the output pins of the CANFD interface chip are connected to the input pins of the CANFD controller, and the CANFD interface is connected to the output pins of the CANFD controller.

[0014] In some embodiments, the CANFD controller is model MCP2517FD-H / SL.

[0015] The beneficial effects of this disclosure are as follows: by using an embedded main control module as the core of Ethernet data capture, parsing and forwarding control, and by using an Ethernet mirroring module to capture packets to obtain Ethernet data from the Ethernet communication device under test, the main control module performs logical analysis and data processing to parse and convert the captured data, and forwards it via Ethernet or CANFD. The Ethernet data capture, parsing and forwarding device disclosed herein has the advantages of simple circuit structure, small size, low power consumption, flexible external interface and low cost. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in one or more embodiments of this specification or in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the Ethernet data packet capture, parsing, and forwarding device in an embodiment of this disclosure; Figure 2 This is a schematic diagram of the Ethernet mirroring module in an embodiment of this disclosure; Figure 3 This is a circuit schematic diagram of the switch chip in an embodiment of this disclosure; Figure 4 This is a schematic diagram of the structure of the first Ethernet protocol interface module in an embodiment of this disclosure; Figure 5 This is a circuit schematic diagram of the Ethernet protocol interface chip in an embodiment of this disclosure; Figure 6 This is a circuit schematic diagram of the Ethernet matching resistor network in an embodiment of this disclosure; Figure 7 This is a circuit diagram of the Ethernet transformer in an embodiment of this disclosure; Figure 8 This is a schematic diagram of the embedded main control module in an embodiment of this disclosure; Figure 9 This is a circuit schematic diagram of the microprocessor in an embodiment of this disclosure; Figure 10 This is a circuit diagram of the reset circuit of the embedded main control module in an embodiment of this disclosure; Figure 11 This is a circuit schematic diagram of the clock circuit of the embedded main control module in an embodiment of this disclosure; Figure 12 This is a circuit diagram of the startup selection circuit of the embedded main control module in an embodiment of this disclosure; Figure 13This is a circuit schematic diagram of the debugging interface circuit of the embedded main control module in this embodiment of the present disclosure; Figure 14 This is a schematic diagram of the structure of the second Ethernet protocol interface module in an embodiment of this disclosure; Figure 15 This is a schematic diagram of the CANFD interface module in an embodiment of this disclosure; Figure 16 This is a circuit schematic diagram of the CANFD controller in an embodiment of this disclosure; Figure 17 This is a circuit schematic diagram of the CANFD interface chip in an embodiment of this disclosure; Figure 18 This is a circuit schematic diagram of the clock circuit of the CANFD in an embodiment of this disclosure. Detailed Implementation

[0018] To enable those skilled in the art to better understand the technical solutions in one or more embodiments of this specification, the technical solutions in one or more embodiments of this specification will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, and not all of the embodiments. Based on one or more embodiments of this specification, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of this document.

[0019] Ethernet communication is a massive data exchange process, playing a crucial role, especially in today's interconnected network era. The bit error rate (BER) of data exchange between various communication devices is a critical indicator for evaluating Ethernet communication quality. To ensure the reliability of communication equipment, extensive testing and verification of Ethernet communication are necessary, along with evaluation of Ethernet communication data. To assess the BER of each communication device, packet capture of Ethernet communication data is required, followed by further analysis and forwarding to ultimately evaluate the quality of Ethernet communication.

[0020] In the testing of Ethernet communication products, to evaluate the bit error rate of data exchange among various communication devices, it is necessary to acquire Ethernet data from each device in real time during Ethernet communication. Typically, this requires specialized equipment, such as network analyzers or network packet capture tools (Wireshark). These acquisition devices are complex, bulky, and inconvenient to integrate, and the acquired Ethernet data is stored internally without forwarding capabilities.

[0021] To address the aforementioned problems, this disclosure provides an Ethernet data packet capture, parsing, and forwarding device, the structural diagram of which is shown below. Figure 1 As shown, it mainly includes the following modules: an Ethernet mirroring module 10, a first Ethernet protocol interface module 20, an embedded main control module 30, a second Ethernet protocol interface module 40, and a CANFD interface module 50; wherein, the Ethernet mirroring module 10 is used to capture Ethernet data packets output by the communication device, perform mirroring processing on the Ethernet data packets, and output mirrored data packets; the first Ethernet protocol interface module 20 is used to receive mirrored data packets, perform decapsulation processing on the mirrored data packets based on the Ethernet protocol, and output decapsulated data units; the embedded main control module 30 is used to receive decapsulated data units, parse the decapsulated data units, and output data units to be encapsulated to the second Ethernet protocol interface module 40 or the CANFD interface module 50; the second Ethernet protocol interface module 40 is used to encapsulate the data units to be encapsulated based on the Ethernet protocol to form Ethernet data packets for output; the CANFD interface module 50 is used to encapsulate the data units to be encapsulated based on the CANFD protocol to form CANFD data packets for output.

[0022] In this embodiment, the communication device to be detected communicates with the Ethernet mirroring module 10 via an RJ45 interface, so that the Ethernet mirroring module 10 captures the Ethernet data packets output by the communication device and outputs the mirrored data packets to the first Ethernet protocol interface module 20 through the mirroring processing of the Ethernet mirroring module 10. The first Ethernet protocol interface module 20 decapsulates the mirrored data packets and decapsulates them into decapsulated data units that can be directly processed by the embedded main control module 30. The embedded main control module 30 directly parses the decapsulated data units, including but not limited to performing message parsing processing such as link layer parsing, network layer parsing, transport layer parsing, and deep message inspection. Then, it forms a data unit to be encapsulated and forwards the data unit to be encapsulated to the second Ethernet protocol interface module 40 or CANFD interface module 50 according to the destination information carried in the message. When the second Ethernet protocol interface module 40 or CANFD interface module 50 receives the data unit to be encapsulated, it encapsulates the data unit to be encapsulated into an Ethernet data packet or a CANFD data packet according to its corresponding protocol and outputs it.

[0023] Specifically, Figure 2 A schematic diagram of the Ethernet mirroring module 10 is shown, which includes: at least one RJ45 interface ( Figure 2The module includes two RJ45 interfaces, IN1 and IN2, an isolation transformer 11, and a switch chip 12. The RJ45 interfaces are connected to the primary side of the isolation transformer 11, the secondary side of the isolation transformer 11 is connected to the input pin of the switch chip 12, and the output pin of the switch chip 12 is connected to the first Ethernet protocol interface module 20. In actual operation, the Ethernet mirroring module 10 receives Ethernet packets through the RJ45 interfaces. The Ethernet packets are mirrored when passing through the switch chip 12, and the mirrored packets are output through the output pin of the switch chip 12 as an RJ45 mirroring interface. In some embodiments, the switch chip 12 can be implemented using a chip of model FC2012NL, such as... Figure 3 As shown; in addition, the Ethernet mirroring module 10 may also include peripheral circuits such as a reset circuit 13, a power conversion circuit 14, a clock circuit 15, and a download interface circuit 16. The above peripheral circuits can directly use conventional circuit modules that are compatible with the switch chip. This embodiment does not limit their specific circuit structure.

[0024] Figure 4 A schematic diagram of the structure of the first Ethernet protocol interface module 20 is shown. It mainly includes a first Ethernet protocol interface chip 21. The input pins of the first Ethernet protocol interface chip 21 are connected to the output pins of the switch chip 12, and the output pins of the first Ethernet protocol interface chip 21 are connected to the embedded main control module 30 to achieve decapsulation and encapsulation of Ethernet data packets through the Ethernet protocol interface chip 21. In this embodiment, the first Ethernet protocol interface chip 21 can be selected as an SM5100 Ethernet protocol interface chip, such as... Figure 5 As shown; in addition, the first Ethernet protocol interface module 20 functions in conjunction with the first Ethernet protocol interface chip 21, such as... Figure 4 As shown, the first Ethernet protocol interface module 20 should also include peripheral circuits such as a reset circuit 22, a power conversion circuit 23, an isolation transformer 24, a clock circuit 25, a working mode selection circuit 26, and an internal communication interface circuit 27 for the first Ethernet protocol interface chip 21. These peripheral circuits can directly use conventional circuit modules compatible with the Ethernet protocol interface chip; this embodiment does not limit their specific circuit structure. Furthermore, Figure 6 The circuit schematic of an Ethernet matching resistor network is also shown, which is used to match the impedance of Ethernet cabling to improve the stability of a signal transmission. Figure 7 The circuit diagram of the Ethernet transformer is also shown. In the first Ethernet protocol interface module 20, the Ethernet transformer can also isolate electrical signals to improve the anti-interference ability and transmission stability of Ethernet signals.

[0025] Figure 8A schematic diagram of the embedded main control module 30 is shown, which mainly includes a microprocessor 31, a reset circuit 32, and a clock circuit 33. The input pins of the microprocessor 31 are connected to the output pins of the first Ethernet protocol interface chip 21, and the output pins of the microprocessor 31 are connected to the second Ethernet protocol interface module 40 and the CANFD interface module 50. The clock circuit 33 provides a clock signal to the microprocessor, and the reset circuit 32 performs a reset operation on the microprocessor. In addition, the embedded main control module 30 may also include peripheral circuits such as a power supply circuit 34, a boot selection circuit 35, a flash circuit 36, an SDRAM circuit 37, a debug interface circuit 38, and an internal communication interface circuit 39, to cooperate with the microprocessor 31 as the control core of the Ethernet data capture, parsing, and forwarding device, realizing functions such as Ethernet packet capture data parsing and forwarding.

[0026] In some embodiments, the microprocessor 31 may be an embedded processor system-on-a-chip (SoC), model SM9B000MBL, such as... Figure 9 As shown, this chip is a 32-bit RISC high-performance microcontroller chip that follows the ARM architecture. It has a 400MHz SOC clock frequency, low power consumption, a maximum current of 300mA, and simple peripheral circuitry. For example, Figure 10 A circuit schematic of the reset circuit 32 is shown. Figure 11 A circuit schematic of clock circuit 33 is shown. Figure 12 This shows a circuit schematic of the start selection circuit 35. Figure 13 The diagram illustrates a circuit schematic for the debugging interface circuit 38, all of which utilize simple chips and conventional electronic components such as resistors and capacitors to achieve their respective functions. It should be noted that the above... Figures 10 to 13 The circuit schematic shown is only one implementation of the corresponding circuit and does not limit other circuit implementations. Furthermore, other circuits not shown in the attached figures can also be implemented using conventional circuit structures or devices, and this embodiment does not impose any restrictions.

[0027] Similar to the first Ethernet protocol interface module 20, the second Ethernet protocol interface module 40 mainly includes a second Ethernet protocol interface chip 41. The difference is that the first Ethernet protocol interface chip 21 is used for decapsulating Ethernet data packets in this embodiment, while the input pin of the second Ethernet protocol interface chip 41 is connected to the output pin of the microprocessor to receive the data unit to be encapsulated output by the microprocessor, and encapsulate it into an Ethernet data packet based on the Ethernet protocol for output. At the same time, in order to facilitate the forwarding of data packets to other devices, the output pin of the second Ethernet protocol interface chip 41 is connected to an RJ45 interface. Figure 14The diagram shows the structure of the second Ethernet protocol interface module 40. In addition to the second Ethernet protocol interface chip 41, it also includes peripheral circuits related to the second Ethernet protocol interface chip 41, such as a reset circuit 42, a power conversion circuit 43, an isolation transformer 44, a clock circuit 45, a working mode selection circuit 46, and an internal communication interface circuit 47.

[0028] In practical implementation, the second Ethernet protocol interface chip 41 can be an Ethernet protocol interface chip of the same model as the first Ethernet protocol interface chip 21, namely the SM5100. Figure 5 As shown, and in Figure 5 The diagram also shows the connection between pins 75 and 76 of the SM5100 and the RJ45 interface. For the second Ethernet protocol interface chip 41, its output Ethernet data packets can be output to the destination device through the RJ45 interface, while for the first Ethernet protocol interface chip 21, it does not need to be connected to the RJ45 interface.

[0029] The CANFD interface module 50 mainly includes a CANFD controller 51, a CANFD interface chip 52, and a CANFD interface 53. The input pins of the CANFD interface chip 52 are connected to the output pins of the microprocessor 31, the output pins of the CANFD interface chip 52 are connected to the input pins of the CANFD controller 51, and the CANFD interface 53 is connected to the output pins of the CANFD controller 51. The CANFD interface module 50 may also include peripheral circuits such as a power conversion circuit 54, a clock circuit 55, and an internal communication interface circuit 56. Figure 15 As shown, the CANFD interface chip 52 enables high-speed reception of data units to be encapsulated. The aforementioned peripheral circuitry, in conjunction with the CANFD controller 51, encapsulates the data units to be encapsulated according to the CANFD protocol to form CANFD data packets, and then forwards them through the CANFD interface 53. In some embodiments, the CANFD controller 51 is model MCP2517FD-H / SL, and its circuit schematic is shown below. Figure 16 As shown, the CANFD interface chip 52 is model TJA1057T, and its circuit schematic is as follows. Figure 17 As shown, the schematic diagram of the CANFD clock circuit 55 is as follows. Figure 18 As shown.

[0030] It should be noted that in this embodiment, the input and output pins of all hardware structures are the pins that actually perform data input and output when implementing their own functions. Which pin is specifically used can be determined based on the device model and its connection relationship with other devices; this embodiment does not impose any restrictions. Furthermore, the accompanying drawings only show circuit schematics of a portion of the hardware structures in each module. The parts not shown can be directly implemented using conventional circuits that implement the corresponding functions in the respective modules, and this embodiment does not provide specific explanations.

[0031] This embodiment uses an embedded main control module as the core of Ethernet data capture, parsing, and forwarding control. It uses an Ethernet mirroring module to capture packets and obtain Ethernet data from the Ethernet communication device under test. After logical analysis and data processing by the main control module, the captured data is parsed and converted, and then forwarded via Ethernet or CANFD. The Ethernet data capture, parsing, and forwarding device disclosed herein has the advantages of simple circuit structure, small size, low power consumption, flexible external interface, and low cost.

[0032] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An Ethernet data packet capture, parsing, and forwarding device, characterized in that, include: The Ethernet mirroring module is used to capture Ethernet data packets output by communication devices, mirror the Ethernet data packets, and output mirrored data packets. The first Ethernet protocol interface module is used to receive the mirrored data packet, perform decapsulation processing on the mirrored data packet based on the Ethernet protocol, and output decapsulated data unit. An embedded main control module is used to receive the decapsulated data unit, parse the decapsulated data unit, and output the data unit to be encapsulated to the second Ethernet protocol interface module or CANFD interface module. The second Ethernet protocol interface module is used to encapsulate the data unit to be encapsulated based on the Ethernet protocol, forming an Ethernet data packet output. The CANFD interface module is used to encapsulate the data unit to be encapsulated based on the CANFD protocol, forming a CANFD data packet output.

2. The Ethernet data packet capture, parsing, and forwarding device according to claim 1, characterized in that, The Ethernet mirroring module includes: at least one RJ45 interface, an isolation transformer, and a switch chip; wherein the RJ45 interface is connected to the primary end of the isolation transformer, the secondary end of the isolation transformer is connected to the input pin of the switch chip, and the output pin of the switch chip is connected to the first Ethernet protocol interface module.

3. The Ethernet data packet capture, parsing, and forwarding device according to claim 2, characterized in that, The model number of the switch chip is FC2012NL.

4. The Ethernet data packet capture, parsing, and forwarding device according to claim 2, characterized in that, The first Ethernet protocol interface module includes: a first Ethernet protocol interface chip, wherein the input pins of the first Ethernet protocol interface chip are connected to the output pins of the switch chip, and the output pins of the first Ethernet protocol interface chip are connected to the embedded main control module.

5. The Ethernet data packet capture, parsing, and forwarding device according to claim 4, characterized in that, The embedded main control module includes a microprocessor, a reset circuit, and a clock circuit. The input pins of the microprocessor are connected to the output pins of the first Ethernet protocol interface chip, and the output pins of the microprocessor are connected to the second Ethernet protocol interface module and the CANFD interface module. The clock circuit is used to provide a clock signal to the microprocessor, and the reset circuit is used to reset the microprocessor.

6. The Ethernet data packet capture, parsing, and forwarding device according to claim 5, characterized in that, The microprocessor is model SM9B000MBL.

7. The Ethernet data packet capture, parsing, and forwarding device according to claim 6, characterized in that, The second Ethernet protocol interface module includes: a second Ethernet protocol interface chip, wherein the input pins of the second Ethernet protocol interface chip are connected to the output pins of the microprocessor, and the output pins of the second Ethernet protocol interface chip are connected to an RJ45 interface.

8. The Ethernet data packet capture, parsing, and forwarding device according to claim 6, characterized in that, Both the first Ethernet protocol interface chip and the second Ethernet protocol interface chip are model SM5100.

9. The Ethernet data packet capture, parsing, and forwarding device according to claim 7, characterized in that, The CANFD interface module includes a CANFD controller, a CANFD interface chip, and a CANFD interface. The input pins of the CANFD interface chip are connected to the output pins of the microprocessor, the output pins of the CANFD interface chip are connected to the input pins of the CANFD controller, and the CANFD interface is connected to the output pins of the CANFD controller.

10. The Ethernet data packet capture, parsing, and forwarding device according to claim 9, characterized in that, The CANFD controller is model MCP2517FD-H / SL.

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