An image sensor dark current test structure and a dark current test semiconductor structure

Abstract

The utility model discloses a simple image sensor dark current test structure is constituted through the composition of image sensor dark current test structure, namely capacitor C and multiple parallelly arranged pixel units, only need to control the switch of transmission transistor, save timing circuit and amplifier circuit, reduce the complexity of dark current test, and the Fab section in situ monitoring is realized, namely need not CP test machine, directly monitor dark current in Fab process line, realize the direct measurement of BEOL capacitor charge, can track the pollution source fast, make the problem batch interception time advance 2-3 weeks, reduce 30% production loss, and can directly calculate dark electron number through capacitor charge difference, to realize the ability of FAB end measurement dark electron number.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor manufacturing technology, and in particular to an image sensor dark current testing structure and a dark current testing semiconductor structure. Background Technology

[0002] In the manufacturing process of CIS (CMOS Image Sensor), photodiodes (PPDs) can generate non-photogenerated free electrons, or dark current, under dark conditions due to material defects, process contamination, or structural stress. An abnormal increase in dark current causes the sensor to output a high-level signal even in the absence of light, which manifests as abnormal white pixels (WP) in the image, severely affecting image quality.

[0003] Current industry standards utilize Circuit Probing (CP) testing with a 4T pixel structure to detect dark current. This technology relies on a traditional 4T pixel structure: a photodiode (PPD), a transmission transistor (TX), a floating diffusion node (FD), and a source follower (SF). The PPD accumulates dark charge. When the TX is turned on, electrons flow to the FD for charge storage. After current amplification by the SF, Vout is read to obtain the voltage change ∆V at the FD, and the charge change ∆Q at the FD is deduced from this voltage reading. Precise timing control of the transmission transistor (TX), the reset of the FD, and the readout from the SF is crucial during testing.

[0004] The current test structure and test methods have the following shortcomings:

[0005] 1. Insufficient timeliness: The interval between wafer production at the Fab end and CP testing at the customer end can be as long as several weeks. During this period, the Fab has completed multiple batches (lots) of production, making it impossible to quickly locate the source of dark current contamination, resulting in delayed exposure of process problems.

[0006] 2. Limitations of testing scenarios: Complex timing circuit requirements can only be completed on CP testing equipment. The Fab side lacks in-situ monitoring capabilities and cannot quickly provide feedback on process defects on the production line.

[0007] 3. Limited measurement accuracy: The tiny capacitance (1fF ~ 10fF) of the floating diffusion node FD makes the signal susceptible to noise interference, and introduces additional errors in the amplification stage of the source follower SF, thereby reducing the accuracy of dark charge quantization. Utility Model Content

[0008] The purpose of this invention is to provide a dark current testing structure and method for image sensors, which can solve problems such as insufficient timeliness, limited testing scenarios, and limited measurement accuracy.

[0009] To address the above technical problems, this utility model provides an image sensor dark current testing structure, including a capacitor and multiple pixel units arranged in parallel. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode. The drain terminals of all the transmission transistors are connected to the first plate of the capacitor. The second plate of the capacitor is connected to a reference voltage.

[0010] Optionally, the positive terminal of the photodiode is grounded, the negative terminal of the photodiode is connected to the source terminal of the transmission transistor, the gate terminal of the transmission transistor is connected to a control signal, and the first plate is also connected to an external power supply.

[0011] Optionally, the reference voltage is a reference ground.

[0012] Optionally, the capacitor is a MOM capacitor or a MIM capacitor; the capacitance value of the capacitor is 1pF to 100pF.

[0013] Optionally, the first electrode plate is connected to at least 100 pixel units simultaneously.

[0014] Furthermore, the first electrode plate is simultaneously connected to 100 to 10,000 pixel units.

[0015] On the other hand, the present invention also provides a dark current testing semiconductor structure, including a substrate, the substrate including a dicing region, a device structure layer and an interconnect structure are sequentially disposed on the substrate, and a plurality of pixel units and capacitors are disposed in the device structure layer located in the dicing region.

[0016] Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode through the interconnect structure. The drain terminals of all the transmission transistors are connected to the first plate of the capacitor through the interconnect structure. The second plate of the capacitor is connected to a reference voltage.

[0017] Optionally, the capacitor is a MOM capacitor or a MIM capacitor.

[0018] Furthermore, when the capacitor is a MIM capacitor, the first electrode of the capacitor is the Mth metal layer located in the dicing region, the second electrode is the (M+1)th metal layer located on the Mth metal layer, and the insulating layer of the capacitor is the dielectric layer located between the Mth metal layer and the (M+1)th metal layer, wherein M+1≤N.

[0019] Furthermore, when the capacitor is a MOM capacitor, the first plate and the second plate have the same shape, and both are toothed plates.

[0020] Compared with the prior art, the present invention has the following unexpected technical effects:

[0021] This invention provides an image sensor dark current testing structure and a dark current testing semiconductor structure. The image sensor dark current testing structure includes a capacitor and multiple pixel units arranged in parallel. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode, and the drain terminals of all the transmission transistors are connected to the first plate of the capacitor. The second plate of the capacitor is connected to a reference voltage. This invention simplifies the image sensor dark current testing structure by using a capacitor C and multiple pixel units arranged in parallel. It only requires controlling the switching of the transmission transistor, eliminating the need for timing circuits and amplification circuits, reducing the complexity of dark current testing, and enabling in-situ monitoring at the fab stage. That is, dark current can be monitored directly on the fab process line without the need for a CP testing machine. This enables direct measurement of the charge of the BEOL (back-end process) capacitor, allowing for rapid tracking of contamination sources, reducing the interception time of problematic batches by 2-3 weeks, and reducing mass production losses by 30%. At the same time, the number of dark electrons can be directly calculated from the capacitor charge difference, enabling the measurement of the number of dark electrons at the FAB (Fab-end Process). Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a 4T pixel structure.

[0023] Figures 2-3 This is a schematic diagram of a dark current testing structure for an image sensor provided in one embodiment of the present invention.

[0024] Explanation of reference numerals in the attached figures:

[0025] 10-pixel unit. Detailed Implementation

[0026] The following will provide a more detailed description of the image sensor dark current testing structure and the dark current testing semiconductor structure of this utility model. The present utility model will be described in more detail below with reference to the accompanying drawings, which illustrate preferred embodiments of the present utility model. It should be understood that those skilled in the art can modify the present utility model described herein while still achieving the advantageous effects of the present utility model. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the present utility model.

[0027] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would confuse the present invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific goals, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0028] To make the objectives and features of this utility model clearer and easier to understand, the specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to facilitate and clarify the explanation of the objectives of the embodiments of this utility model.

[0029] It is known that in the field of CMOS image sensor manufacturing, white pixel defects caused by dark current are a core problem that has long plagued the industry. Traditional detection methods rely on CP testing of the 4T pixel structure of the product. Its fatal flaw is that when wafers move from the fab production line to the CP testing station, there may be several weeks in between, during which dozens of batches of wafers have already been processed at the fab, making it impossible to quickly trace the source of dark current contamination. For example... Figure 1 As shown, existing technologies employ a complete 4T pixel structure, including a photodiode (PPD), a transmission transistor (TX), a floating diffusion node (FD), a reset transistor (RST), and a source follower (SF). During testing, precise timing control of the TX's activation, the FD's readout, the RST's readout, and the SF's readout is crucial. This complexity makes it completely unfeasible for implementation on a fab process line. The industry urgently needs a dark current monitoring solution with a simplified structure, independent of timing, and capable of in-situ implementation before wafer dicing.

[0030] Based on the above analysis, this embodiment provides an image sensor dark current test structure, including a capacitor and multiple pixel units arranged in parallel. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode. The drain terminals of all the transmission transistors are connected to the first plate of the capacitor. The second plate of the capacitor is connected to a reference voltage.

[0031] This embodiment simplifies the image sensor dark current testing structure by using a capacitor C and multiple parallel pixel units 10. It only requires controlling the switching of the transmission transistor TX, eliminating timing and amplification circuits, reducing the complexity of dark current testing, and enabling in-situ monitoring at the fab stage. This means that dark current can be monitored directly on the fab process line without the need for a CP testing machine, achieving direct measurement of the charge of capacitor C in the BEOL (back-end process). This allows for rapid tracking of contamination sources, reducing the interception time of problematic batches by 2-3 weeks and decreasing mass production losses by 30%. At the same time, the number of dark electrons can be directly calculated from the charge difference of capacitor C, enabling the measurement of the number of dark electrons at the FAB end.

[0032] Figures 2-3 This is a schematic diagram of a dark current testing structure for an image sensor provided in this embodiment. Figures 2-3 As shown, this embodiment provides a dark current testing structure for an image sensor, including a capacitor C. The capacitor C includes a first plate and a second plate. The first plate of the capacitor C is simultaneously connected to multiple pixel units 10 arranged in parallel. This embodiment uses a capacitor C to replace the floating diffusion node FD in the existing 4T pixel structure for storing electrons, thereby avoiding the charge-to-voltage conversion error of the floating diffusion node FD. It can realize the direct collection and quantization of dark charge, providing the possibility for rapid process monitoring at the fab end.

[0033] In one embodiment, the capacitor C is a MOM capacitor or a MIM capacitor; the capacitance value of the capacitor C is 1pF to 100pF. The first electrode plate is simultaneously connected to at least 100 pixel units 10, preferably, the first electrode plate is simultaneously connected to 100 to 10000 pixel units 10.

[0034] The pixel unit 10 includes a photodiode (PPD) and a transmission transistor (TX). The PPD generates dark current charge under dark conditions, and its anode is grounded. The cathode of the PPD is connected to the source terminal of the transmission transistor (TX). The drain terminal of the transmission transistor (TX) is connected to the first plate, and the gate terminal of the transmission transistor (TX) is connected to a control signal. The first plate can be connected to an external power supply, which is used to charge / discharge and reset the capacitor C, thereby replacing the function of the reset transistor (RST) in the prior art. The second plate is connected to a reference voltage. In one embodiment, the reference voltage is, for example, a reference ground.

[0035] The image sensor dark current test structure also includes a voltage measurement unit, which is connected to the first and second plates of the capacitor C during testing and is used to detect the voltage change ΔV of the capacitor C.

[0036] The dark current testing method for the image sensor dark current testing structure provided in this embodiment includes:

[0037] First, an external power supply is connected to the first plate and charges capacitor C from the first plate; then, a voltage measuring unit is connected to the first and second plates of capacitor C to monitor the initial voltage V1 of capacitor C and calculate the initial charge Q1 = C·V1.

[0038] Next, the photodiodes (PPDs) are exposed to dark conditions (e.g., an environment with an illuminance ≤ 0.1 lux) for an exposure time T (e.g., 1 second). All transmission transistors (TX) are then activated, causing the dark charge generated by each photodiode (PPD) connected in parallel with capacitor C to flow into the corresponding capacitor C. A voltage measurement unit is then connected to the first and second plates of capacitor C to monitor the final voltage V2 of capacitor C and calculate the final charge Q2 = C·V2. Simultaneously, the charge change ΔQ = Q2 - Q1, the number of electrons n = ΔQ / e, and the number of dark electrons per pixel = n / number of parallel pixels are calculated. Here, e is the charge of a single electron.

[0039] The dark current testing method provided in this embodiment is applied in the Fab process stage before wafer dicing. Voltage measurement is performed by contacting the first and second plates of capacitor C with a probe, thus enabling direct monitoring of dark current on the Fab process line without the need for a CP testing machine. This allows for direct charge measurement of capacitor C in the BEOL (back-end process), enabling rapid tracing of contamination sources and reducing the interception time of problematic batches by 2-3 weeks, decreasing mass production losses by 30%. Furthermore, this embodiment allows for direct calculation of the number of dark electrons through the charge difference of capacitor C, enabling the measurement of dark electrons at the FAB (Fabry-Performance Assembly) end.

[0040] like Figure 3 As shown, this embodiment also provides a dark current testing semiconductor structure, including a substrate, the substrate including a dicing region, a device structure layer and an interconnect structure are sequentially disposed on the substrate, and a plurality of pixel units 10 are disposed in the device structure layer located in the dicing region, each pixel unit 10 including a photodiode PPD and a transmission transistor TX.

[0041] In one embodiment, the pixel unit 10 is further provided with a dual conversion gain transistor DCG, a floating diffusion node FD, a source follower SF, and a reset transistor RST, which are part of a 4T pixel structure.

[0042] The device structure layer is provided with an interconnect structure, which includes a first metal layer to an Nth metal layer from bottom to top. The first metal layer to the Nth metal layer are all embedded in an insulating dielectric layer, and the insulating dielectric layer exposes the upper surface of the Nth metal layer. A passivation layer is provided on the Nth metal layer.

[0043] The photodiode PPD, dual-conversion gain transistor DCG, transfer transistor TX, source follower SF, reset transistor RST, and select transistor RS are connected through the interconnection structure of the cut-out region. For details, see... Figure 1 As shown, in the 4T pixel structure, the positive terminal of the photodiode PPD is grounded, the negative terminal of the photodiode PPD is connected to the source terminal (i.e., TX Gate) of the transmission transistor TX, the drain terminal (i.e., TX Drain) of the transmission transistor TX is simultaneously connected to the drain terminal of the dual conversion gain transistor DCG and the floating diffusion node FD. The source terminal of the dual conversion gain transistor DCG is grounded through an internal capacitor in an interconnect structure located on the cut-out region. The floating diffusion node FD is also connected to the source terminal of the reset transistor RST and the gate terminal of the source follower SF. The source terminal of the source follower SF is connected to the output voltage Vout, and the drain terminals of the source follower SF and the reset transistor RST are both connected to the external power supply AVDD.

[0044] A capacitor C is disposed in the interconnect structure layer. Capacitor C is located in the dicing region and the dicing area, meaning that capacitor C will be removed during subsequent dicing. Capacitor C is either a MOM capacitor or a MIM capacitor. When capacitor C is a MIM capacitor, the first electrode is the Mth metal layer located in the dicing region, the second electrode is the (M+1)th metal layer on top of the Mth metal layer, and the insulating layer is a dielectric layer located between the Mth and (M+1)th metal layers. This dielectric layer can be 50nm~100nm thick Al2O3 or HfO2, where M+1≤N. When capacitor C is a MOM capacitor, both the first and second electrodes are located in the Mth metal layer. The insulating layer is a dielectric layer located between the first and second electrodes, which can be an oxide (such as SiO2). The first and second electrodes are identical toothed electrodes.

[0045] The first electrode plate is directly or indirectly connected to the drain terminals of the transmission transistors TX of the plurality of pixel units 10 in the device structure layer through a metal layer (M-1) below the M-1 metal layer in the dicing region and the M-1 metal layer in the dicing region. The first electrode plate and the second electrode plate are connected to the N-th metal layer through a metal layer or metal contact above the M+1 metal layer. The N-th metal layer includes a plurality of pads, and the passivation layer exposes the pads, wherein the gate terminals of all the transmission transistors TX are connected to pad 1, the first electrode plate is connected to pad 2, and the second electrode plate is connected to a pad 3.

[0046] The dark current testing semiconductor structure provided in this embodiment is independent of the client design. During the dicing process following the back-end fabrication, the dark current testing semiconductor located in the dicing zone is removed. Therefore, the dark current testing semiconductor structure will not affect the client after completing the in-fab testing, and the client can still use the 4T pixel structure for CP testing. In other words, this embodiment, located in the dicing zone, adds only a capacitor (C) and related circuitry during the back-end fabrication process in the dicing zone, resulting in a dark current testing structure that can be detected in real-time within the fab. Simultaneously, the client can still use the original 4T pixel structure to complete CP testing.

[0047] In summary, this invention provides an image sensor dark current testing structure and a dark current testing semiconductor structure. The image sensor dark current testing structure includes a capacitor and multiple pixel units arranged in parallel. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode, and the drain terminals of all the transmission transistors are connected to the first plate of the capacitor. The second plate of the capacitor is connected to a reference voltage. This invention simplifies the image sensor dark current testing structure by using a capacitor C and multiple pixel units arranged in parallel. It only requires controlling the switching of the transmission transistor, eliminating the need for timing circuits and amplification circuits, reducing the complexity of dark current testing, and enabling in-situ monitoring at the fab stage. That is, dark current can be monitored directly on the fab process line without the need for a CP testing machine. This enables direct measurement of the charge of the BEOL (back-end process) capacitor, allowing for rapid tracking of contamination sources, reducing the interception time of problematic batches by 2-3 weeks, and reducing mass production losses by 30%. At the same time, the number of dark electrons can be directly calculated from the capacitor charge difference, enabling the measurement of the number of dark electrons at the FAB stage.

[0048] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0049] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the present invention without departing from the scope of the present invention, or equivalent embodiments can be modified based on the disclosed technical content. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A dark current testing structure for an image sensor, characterized in that, The device includes a capacitor and multiple pixel units arranged in parallel. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode. The drain terminals of all the transmission transistors are connected to the first plate of the capacitor. The second plate of the capacitor is connected to a reference voltage.

2. The image sensor dark current testing structure as described in claim 1, characterized in that, The positive terminal of the photodiode is grounded, the negative terminal of the photodiode is connected to the source terminal of the transmission transistor, the gate terminal of the transmission transistor is connected to a control signal, and the first plate is also connected to an external power supply.

3. The image sensor dark current testing structure as described in claim 1, characterized in that, The reference voltage is a reference ground.

4. The image sensor dark current testing structure as described in claim 1, characterized in that, The capacitor is a MOM capacitor or a MIM capacitor; the capacitance value of the capacitor is 1pF to 100pF.

5. The image sensor dark current testing structure as described in claim 1, characterized in that, The first electrode plate is connected to at least 100 pixel units simultaneously.

6. The image sensor dark current test structure as described in claim 5, characterized in that, The first electrode plate connects to 100 to 10,000 pixel units simultaneously.

7. A semiconductor structure for dark current testing, characterized in that, The device includes a substrate, the substrate including a dicing region, a device structure layer and an interconnect structure are sequentially disposed on the substrate, and a plurality of pixel units and capacitors are disposed in the device structure layer located in the dicing region. Each pixel unit includes a photodiode and a transmission transistor. The source terminal of the transmission transistor is connected to the photodiode through the interconnect structure. The drain terminals of all the transmission transistors are connected to the first plate of the capacitor through the interconnect structure. The second plate of the capacitor is connected to a reference voltage.

8. The dark current testing semiconductor structure as described in claim 7, characterized in that, The capacitor is a MOM capacitor or a MIM capacitor.

9. The dark current testing semiconductor structure as described in claim 8, characterized in that, When the capacitor is a MIM capacitor, the first plate of the capacitor is the Mth metal layer located in the dicing region, the second plate is the (M+1)th metal layer located on the Mth metal layer, and the insulating layer of the capacitor is the dielectric layer located between the Mth metal layer and the (M+1)th metal layer, wherein M+1≤N.

10. The dark current testing semiconductor structure as described in claim 9, characterized in that, When the capacitor is a MOM capacitor, the first plate and the second plate have the same shape and are both toothed plates.

Images