PCB package structure

Abstract

The utility model discloses a kind of PCB packaging structures, including EPAD being arranged on PCB board, the surface of EPAD is equipped with tin cream layer, the surface of tin cream layer is equipped with solder resist, EPAD reserves multiple via holes.Solder resist includes multiple first area, tin cream layer includes multiple second area, in the position of directly facing adjacent via hole, the minimum distance of the edge of first area and the edge of corresponding second area below adjacent via hole is greater than preset interval threshold value. Thus, by setting solder resist includes multiple first area, tin cream layer includes multiple second area, in the position of directly facing adjacent via hole, the minimum distance of the edge of first area and the edge of corresponding second area below adjacent via hole is greater than preset interval threshold value, so that solder resist and tin cream layer are avoided to set via hole, ensure the effective welding of component, avoid component burnout.

Description

Technical Field

[0001] This utility model relates to the field of PCB design technology, and more specifically, to a PCB packaging structure. Background Technology

[0002] A PCB (Printed Circuit Board) is the support structure for electronic components and also the carrier for the electrical connections of electronic components.

[0003] During the PCB manufacturing process, after the PCB is fabricated, components need to be soldered and assembled. To enhance heat dissipation, vias are typically drilled on the bottom EPAD (Exposed Pad).

[0004] The EPAD has a solder paste layer and a solder mask layer. The solder paste layer is the part used to apply solder paste before soldering, and this layer can also be used to make the stencil for printing solder paste. The solder mask layer is the part of the PCB board that is coated with green solder mask, which is used to prevent solder paste from being applied to areas that should not be applied, so as to ensure that soldering only occurs in specific areas such as the pads.

[0005] In current packaging designs, the solder paste layer and solder mask layer are usually consistent with the pad size. Due to the through-hole design on the EPAD, after the solder paste is printed and mounted, the solder paste will flow into the through-hole during reflow soldering, causing solder leakage or insufficient solder. That is, because the solder paste will flow when heated, the solder paste will flow from the pad through-hole on the front of the PCB board to the back of the PCB board, which will reduce the contact area between the bottom of the component and the PCB board, making it impossible to ensure effective soldering of the component. As a result, the heat generated by the component during operation cannot be dissipated, causing the operating temperature to be too high and burn out. Summary of the Invention

[0006] This invention provides a PCB packaging structure that ensures effective soldering of components and prevents them from burning out. The specific technical solution is as follows: In a first aspect, this utility model provides a PCB packaging structure, including a printed circuit board (PCB), on which exposed pads (EPADs) are provided. A solder paste layer is provided on the surface of each EPAD, and a solder resist layer is provided on the surface of the solder paste layer. Multiple vias are provided in each EPAD. The solder mask layer includes a plurality of first regions, and the solder paste layer includes a plurality of second regions, wherein the first regions and the corresponding second regions below them have the same position, shape and size. At the position directly opposite the adjacent via, the minimum distance between the edge of the first region and the corresponding second region below and the edge of the adjacent via is greater than a preset distance threshold.

[0007] Optionally, multiple first regions are aligned in both row and column directions; Correspondingly, Multiple second regions are aligned in both row and column directions.

[0008] Optionally, at the position directly opposite the adjacent via, the edge of the first region is recessed inward toward the center of the first region to form a first arc, and the edge of the second region corresponding to the first region is recessed inward toward the center of the second region to form a second arc, wherein the minimum distance between the first arc and the second arc and the edge of the adjacent via is greater than a preset distance threshold.

[0009] Optionally, the center of each of the first arcs and the center of each of the second arcs coincide with the center of the adjacent via.

[0010] Optionally, each of the first arcs has the same radian length, and each of the second arcs has the same radian length.

[0011] Optionally, the first region and the corresponding second region below are both located at the center of the area enclosed by the four adjacent outer vias.

[0012] Optionally, the shapes of the first region and the corresponding second region below it are both centrally symmetrical about the central position.

[0013] Optionally, the edge connecting the first arc is a first straight line, and the edge connecting the second arc is a second straight line.

[0014] Optionally, the preset spacing threshold is 0.1 mm.

[0015] Optionally, the minimum spacing is 0.5 mm.

[0016] As described above, the PCB packaging structure provided in this embodiment includes a PCB board, on which an EPAD (Electronic Particulate Array) is disposed. A solder paste layer is disposed on the surface of the EPAD, and a solder resist layer is disposed on the surface of the solder paste layer. The EPAD has multiple vias. The solder resist layer includes multiple first regions, and the solder paste layer includes multiple second regions. The first regions and their corresponding lower second regions are of the same position, shape, and size. At positions directly opposite adjacent vias, the minimum distance between the edges of the first regions and their corresponding lower second regions and the edges of the adjacent vias is greater than a preset distance threshold. Therefore, by setting the solder resist layer to include multiple first regions and the solder paste layer to include multiple second regions, and ensuring that the minimum distance between the edges of the first regions and their corresponding lower second regions and the edges of the adjacent vias is greater than a preset distance threshold, both the solder resist layer and the solder paste layer are positioned away from the vias. This prevents solder paste from flowing from the front of the PCB board through the vias to the back of the PCB board, ensuring effective component soldering, effectively reducing thermal resistance, improving heat dissipation, and preventing component burnout.

[0017] The innovative aspects of this utility model embodiment include: 1. By setting the solder mask layer to include multiple first regions and the solder paste layer to include multiple second regions, and ensuring that the minimum distance between the edge of the first region and the corresponding second region below it and the edge of the adjacent via is greater than a preset distance threshold, the solder mask layer and the solder paste layer are both set to avoid the vias. This prevents solder paste from flowing from the front of the PCB board to the back of the PCB board through the vias, ensuring effective soldering of components, effectively reducing thermal resistance, improving heat dissipation capacity, and preventing components from burning out.

[0018] 2. Multiple first areas are aligned in both row and column directions; correspondingly, multiple second areas are aligned in both row and column directions. This design ensures the stability and overall consistency of the EPAD.

[0019] 3. The arc design of the first and second arcs ensures that the first and second regions do not contact the adjacent vias. At the same time, the arcs are easy to process, reducing the processing difficulty.

[0020] 4. The design that the center of each first arc and the center of each second arc coincide with the center of the adjacent via reduces the difficulty of production and can also improve the yield.

[0021] 5. The design that makes the first arc and the second arc the same reduces production costs and improves production efficiency.

[0022] 6. The first area and the corresponding second area below are both located at the center of the area enclosed by the four adjacent outer vias, which can ensure the overall coordination of the EPAD.

[0023] 7. The centrally symmetrical shape design of the first area and the corresponding second area below it makes the solder mask layer and solder paste layer have regular shapes, which not only facilitates the early PCB board design and drawing, but also ensures the overall coordination and stability of EPAD.

[0024] 8. The design of connecting the edge of the first arc with the first straight line and connecting the edge of the second arc with the second straight line ensures the minimum distance between the first and second regions and the adjacent vias, while reserving as large an area as possible for welding, thereby ensuring the welding effect.

[0025] Of course, implementing any product or method of this utility model does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0026] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0027] Figure 1 A schematic diagram of a PCB packaging structure provided in an embodiment of this utility model; Figure 2 This is a schematic diagram of the disassembled structure of the PCB package provided in an embodiment of the present utility model; Figure 3 This is a schematic diagram of the structure of the first region and the corresponding second region below it, along with the adjacent vias, provided for an embodiment of this utility model.

[0028] Figures 1-3 In the diagram, 1 is the PCB board, 2 is the EPAD, 3 is the via, 4 is the first area, 5 is the second area, 6 is the first arc, 7 is the first straight line, the upper left corner of the EPAD is the minimum spacing. Detailed Implementation

[0029] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only a part of the embodiments of the present utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present utility model without creative effort are within the scope of protection of the present utility model.

[0030] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and drawings of this utility model are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0031] This utility model discloses a PCB packaging structure that ensures effective soldering of components and prevents them from burning out. The following is a detailed description of this utility model embodiment.

[0032] Figure 1 This is a schematic diagram of a PCB packaging structure provided in an embodiment of the present invention. See also... Figure 1 The PCB packaging structure provided in this embodiment of the utility model includes a PCB (Printed Circuit Board) board 1, an EPAD (Exposed Pad) 2 on the PCB board 1, a solder paste layer on the surface of the EPAD 2, a solder resist layer on the surface of the solder paste layer, and multiple vias 3 reserved on the EPAD 2.

[0033] Figure 2 This is a schematic diagram of the disassembled PCB package structure provided in an embodiment of the present invention. See also: Figure 2 The solder mask layer includes multiple first regions 4, and the solder paste layer includes multiple second regions 5. The first regions 4 and their corresponding lower second regions 5 have the same position, shape, and size. Figure 2 As shown, the upper left corner A of EPAD2 can be divided into a first region 4 and a corresponding second region 5 below it.

[0034] Figure 3 This is a structural schematic diagram of the first region and the corresponding second region below it, along with the adjacent vias, provided for an embodiment of this utility model. (See also...) Figure 3 At positions directly opposite adjacent vias, the minimum distance B between the edges of the first region 4 and the corresponding second region 5 below and the edge of the adjacent via 3 is greater than a preset distance threshold. The preset distance threshold can be 0.1 mm; for example, the minimum distance is 0.5 mm.

[0035] In summary, the PCB packaging structure provided by this embodiment includes a PCB board 1, on which an EPAD 2 is disposed. The surface of the EPAD 2 is provided with a solder paste layer, and the surface of the solder paste layer is provided with a solder resist layer. The EPAD 2 has multiple vias 3. The solder resist layer includes multiple first regions 4, and the solder paste layer includes multiple second regions 5. The first regions 4 and their corresponding lower second regions 5 are of the same position, shape, and size. At positions directly opposite adjacent vias, the minimum distance between the edges of the first regions 4 and their corresponding lower second regions 5 and the edges of the adjacent vias 3 is greater than a preset distance threshold. Therefore, by setting the solder resist layer to include multiple first regions 4 and the solder paste layer to include multiple second regions 5, and ensuring that the minimum distance between the edges of the first regions 4 and their corresponding lower second regions 5 and the edges of the adjacent vias 3 is greater than a preset distance threshold, both the solder resist layer and the solder paste layer are positioned away from the vias. This prevents solder paste from flowing from the front of the PCB board through the vias to the back of the PCB board, ensuring effective component soldering, effectively reducing thermal resistance, improving heat dissipation, and preventing component burnout.

[0036] See also Figure 1 Multiple first regions 4 are aligned in both row and column directions; correspondingly, multiple second regions 5 are aligned in both row and column directions. This design ensures the stability and overall consistency of EPAD2.

[0037] For example, from Figure 1 As can be seen, both the first region 4 and the second region 5 use a 3×3 arrangement, meaning they are aligned in 3 rows and 3 columns. The shapes of the first region 4 and the second region 5 are not limited to... Figure 1 As shown, those skilled in the art can adjust the size and shape of the first region 4 and the second region 5 according to the specific circumstances of the surface mount components.

[0038] See also Figure 3 At the position directly opposite the adjacent via 3, the edge of the first region 4 is concave inward toward the center of the first region 4 to form a first arc 6, and the edge of the second region 5 corresponding to the first region 4 below is concave inward toward the center of the second region 5 to form a second arc. The minimum distance B between the first arc 6 and the second arc and the edge of the adjacent via 3 is greater than a preset distance threshold.

[0039] The arc design of the first arc 6 and the second arc ensures that the first region 4 and the second region 5 do not contact the adjacent via 3. At the same time, the arc is easy to process, reducing the processing difficulty.

[0040] Since there may be multiple adjacent vias 3 around the first region 4 and the second region 5, each first region 4 may include multiple first arcs 6, and each second region 5 may include multiple second arcs.

[0041] In one implementation, the center of each first arc 6 and the center of each second arc coincide with the center of the adjacent via 3.

[0042] The design that the center of each first arc 6 and the center of each second arc coincide with the center of the adjacent via 3 reduces the difficulty of production and can also improve the yield.

[0043] In one implementation, the first arc 6 has the same radius, and the second arc has the same radius. The specific radius can be designed according to the actual situation.

[0044] The design that each first arc 6 has the same radius and each second arc has the same radius reduces production costs and improves production efficiency.

[0045] See also Figure 2 The first region 4 and the corresponding second region 5 below are both located at the center of the area enclosed by the four adjacent vias 3 on the outside, which can ensure the overall coordination of EPAD2.

[0046] The shapes of the first region 4 and the corresponding second region 5 below it are both centrally symmetrical about the center position.

[0047] The symmetrical design of the first region 4 and the corresponding second region 5 below it makes the solder mask layer and solder paste layer have regular shapes, which not only facilitates the design and drawing of the PCB board 1 in the early stage, but also ensures the overall coordination and stability of EPAD2.

[0048] See also Figure 3 The edge connecting the first arc 6 is the first straight line 7, and the edge connecting the second arc is the second straight line.

[0049] The design of connecting the edge of the first arc 6 with the first straight line 7 and connecting the edge of the second arc with the second straight line ensures the minimum distance between the first region 4 and the second region 5 and the adjacent via 3, while reserving as large an area as possible for welding, thereby ensuring the welding effect.

[0050] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing this utility model.

[0051] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0052] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and not to limit it; although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this utility model.

Claims

1. A PCB packaging structure, comprising a printed circuit board (PCB), wherein exposed pads (EPADs) are disposed on the PCB, a solder paste layer is disposed on the surface of the EPADs, a solder mask layer is disposed on the surface of the solder paste layer, and the EPADs have a plurality of vias pre-drilled, characterized in that, The solder mask layer includes a plurality of first regions, and the solder paste layer includes a plurality of second regions, wherein the first regions and the corresponding second regions below them have the same position, shape and size. At the position directly opposite the adjacent via, the minimum distance between the edge of the first region and the corresponding second region below and the edge of the adjacent via is greater than a preset distance threshold.

2. The PCB packaging structure as described in claim 1, characterized in that, Multiple first regions are aligned in both row and column directions; Correspondingly, Multiple second regions are aligned in both row and column directions.

3. The PCB packaging structure as described in claim 1, characterized in that, At the position directly opposite the adjacent via, the edge of the first region is concave inward toward the center of the first region to form a first arc, and the edge of the second region corresponding to the first region below the first region is concave inward toward the center of the second region to form a second arc. The minimum distance between the first arc and the second arc and the edge of the adjacent via is greater than a preset distance threshold.

4. The PCB packaging structure as described in claim 3, characterized in that, The center of each of the first arcs and the center of each of the second arcs coincide with the center of the adjacent via.

5. The PCB packaging structure as described in claim 3, characterized in that, The first arc has the same radius, and the second arc has the same radius.

6. The PCB packaging structure as described in claim 3, characterized in that, The first region and the corresponding second region below are both located at the center of the area enclosed by four adjacent outer vias.

7. The PCB packaging structure as described in claim 6, characterized in that, The shapes of the first region and the corresponding second region below it are both centrally symmetrical about the central position.

8. The PCB packaging structure as described in claim 7, characterized in that, The edge connecting the first arc is the first straight line, and the edge connecting the second arc is the second straight line.

9. The PCB packaging structure as described in claim 1, characterized in that, The preset spacing threshold is 0.1 mm.

10. The PCB packaging structure as described in claim 1, characterized in that, The minimum spacing is 0.5 mm.

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