A multi-chip stacked system-in-package structure

Abstract

The utility model discloses a kind of multi-chip stacked system-level package structures, it is related to semiconductor packaging technical field, include substrate, passive component, SOC chip, memory chip, flash memory chip and plastic encapsulation resin;Passive component has two, two passive components are symmetrically arranged in the top surface of substrate two sides;SOC chip is inverted in the top surface of substrate middle part, and SOC chip is filled with bottom filling glue between substrate;Memory chip has two, two memory chips are vertically stacked in succession on SOC chip, two memory chips are fixed by DAF film bonding, the two sides of two memory chips are provided with bonding wire, and the scheme is vertically stacked by SOC chip, memory chip and flash memory chip, and passive component is reasonably arranged, the integration of multiple functional chips is realized in limited substrate space, greatly improve the integration of package structure, comply with mainstream trend of system integration, can satisfy the demand of electronic equipment miniaturization, high performance.

Description

Technical Field

[0001] This utility model relates to a system-level packaging structure for multi-chip stacking, belonging to the field of semiconductor packaging technology. Background Technology

[0002] System-in-package (SIP) is an electronic device packaging solution that integrates multiple functional chips, including processors and memory chips, into a single package to achieve a basic and complete function.

[0003] Traditional system-in-package (SIP) is typically divided into three layers: IC integration, package integration, and board-level structure. With advancements in integrated circuit technology, system integration has become the mainstream trend. However, in the pursuit of higher integration, interconnect latency issues have gradually emerged, shifting the bottleneck of system performance from the chip level to the package level. High integration within the package makes heat dissipation a major challenge; uneven temperature distribution and high temperatures can damage the package structure, and thermal mismatch between different materials can also affect its reliability. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a system-level packaging structure for multi-chip stacking.

[0005] To achieve the above objectives, the technical solution adopted by this utility model is: a multi-chip stacked system-level packaging structure, comprising a substrate, passive components, a SOC chip, a memory chip, a flash memory chip, and a molding resin;

[0006] There are two passive components, which are symmetrically arranged on both sides of the top surface of the substrate; the SOC chip is flip-chip mounted in the middle of the top surface of the substrate, and the space between the SOC chip and the substrate is filled with underfill.

[0007] There are two memory chips, which are stacked vertically on the SOC chip. The two memory chips are bonded together by a DAF film. Bonding lines are provided on both sides of the two memory chips. The two memory chips are interconnected with the substrate through the bonding lines, and the bonding line on the lower memory chip is wrapped in the DAF film between the two memory chips.

[0008] The flash memory chip is stacked on the memory chip on the upper layer. The flash memory chip is provided with multiple bonding wires and is interconnected with the substrate through the multiple bonding wires.

[0009] The encapsulating resin is located above the substrate and is used to encapsulate passive components, SOC chips, memory chips, and flash memory chips onto the substrate.

[0010] Preferably, the memory chip and the SOC chip in the lower layer, and the memory chip and the flash memory chip in the upper layer are both bonded and fixed by DAF film.

[0011] Preferably, the molding resin is epoxy resin, and the two sides of the molding resin are flush with the two sides of the substrate.

[0012] Preferably, lead-free solder paste is provided between the passive component and the substrate, and the passive component is connected to the substrate through the lead-free solder paste and fixed by reflow soldering.

[0013] Preferably, a plurality of equidistant solder balls are disposed on the bottom surface of the substrate, and the solder balls are soldered and fixed on the substrate.

[0014] Preferably, the substrate has a double-layer structure, and multiple through holes are provided in the middle of the substrate.

[0015] Preferably, the bonding wire is made of gold wire with a purity of 99%.

[0016] Due to the application of the above technical solution, this utility model has the following advantages compared with the prior art:

[0017] 1. This utility model achieves the integration of multiple functional chips within a limited substrate space by vertically stacking SOC chips, memory chips, and flash memory chips, and rationally arranging passive components. This greatly improves the integration of the packaging structure, conforms to the mainstream trend of system integration, and can meet the needs of miniaturization and high performance of electronic devices.

[0018] 2. The memory chip and flash memory chip of this application are interconnected with the substrate through bonding wires. The bonding wires of the lower memory chip are wrapped in DAF film, which not only ensures the reliability of the interconnection, but also reduces the space occupied by the bonding wires and reduces the interconnection delay. This interconnection method makes the signal transmission path between chips and between chips and the substrate shorter, which helps to improve system performance. Attached Figure Description

[0019] The technical solution of this utility model will be further described below with reference to the accompanying drawings:

[0020] Appendix Figure 1 This is a schematic diagram of a multi-chip stacked system-in-package structure according to the present invention;

[0021] Appendix Figure 2 This is a schematic diagram of step two of the processing procedure described in this utility model;

[0022] Appendix Figure 3 This is a schematic diagram of step three of the processing procedure described in this utility model;

[0023] Appendix Figure 4This is a schematic diagram of step four of the processing procedure described in this utility model;

[0024] Appendix Figure 5 This is a schematic diagram of step five of the processing procedure described in this utility model;

[0025] Appendix Figure 6 This is a schematic diagram of step six of the processing procedure described in this utility model;

[0026] Appendix Figure 7 This is a schematic diagram of step seven of the processing procedure described in this utility model.

[0027] In the diagram: 1. Substrate; 2. Passive components; 3. SOC chip; 4. Memory chip; 5. Flash memory chip; 6. Molding resin; 7. Underfill; 8. DAF film; 9. Bonding wire; 10. Lead-free solder paste; 11. Solder ball; 12. Through-hole. Detailed Implementation

[0028] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments.

[0029] As attached Figure 1 As shown, the system-in-package structure of the present invention, which is a multi-chip stack, includes a substrate 1, passive components 2, SOC chip 3, memory chip 4, flash memory chip 5, and encapsulating resin 6.

[0030] There are two passive components 2, which are symmetrically arranged on both sides of the top surface of the substrate 1. In this embodiment, lead-free solder paste 10 is provided between the passive components 2 and the substrate 1. The passive components 2 are connected to the substrate 1 through the lead-free solder paste 10 and fixed by reflow soldering. This connection method is not only environmentally friendly, but also ensures the stability of the connection.

[0031] The SOC chip 3 is flip-chip mounted on the top center of the substrate 1, and the space between the SOC chip 3 and the substrate 1 is filled with underfill adhesive 7. Underfill adhesive 7 can effectively eliminate the gap between the chip and the substrate 1, enhance the mechanical strength and reliability of the connection between the two, and reduce connection failure problems caused by thermal stress and other factors. At the same time, the flip-chip packaging can greatly improve the heat dissipation performance of the product.

[0032] There are two memory chips 4, which are stacked vertically on the SOC chip 3 to form an upper and lower layer structure. The lower memory chip 4 is bonded and fixed to the SOC chip 3 by a DAF film 8, and the two memory chips 4 are also bonded and fixed to each other by a DAF film 8. The DAF film 8 not only plays a bonding role, but also provides good buffering and protection during the chip stacking process, and at the same time helps with heat conduction.

[0033] Furthermore, bonding wires 9 are provided on both sides of the two memory chips 4. In this embodiment, the bonding wires 9 are made of gold wire with a purity of 99%. The two memory chips 4 are interconnected with the substrate 1 through the bonding wires 9. The bonding wires 9 located on the lower memory chip 4 are wrapped in the DAF film 8 between the two memory chips 4 to protect the bonding wires 9 and prevent them from being interfered with or damaged by external factors.

[0034] Flash memory chip 5 is stacked on top of memory chip 4. The memory chip 4 and flash memory chip 5 are bonded and fixed together by DAF film 8. Multiple bonding lines 9 are provided on flash memory chip 5. Flash memory chip 5 is interconnected with substrate 1 through multiple bonding lines 9 to ensure signal transmission and power supply between flash memory chip 5 and substrate 1.

[0035] The molding resin 6 is located above the substrate 1. The molding resin 6 is used to encapsulate the passive components 2, SOC chip 3, memory chip 4 and flash memory chip 5 on the substrate 1. In this embodiment, the molding resin 6 is epoxy resin, and the two sides of the molding resin 6 are flush with the two sides of the substrate 1. Epoxy resin has excellent insulation, heat resistance and mechanical properties, which can effectively protect the internal chips and connection structures from the influence of the external environment.

[0036] Furthermore, the substrate 1 has a double-layer structure, and multiple through holes 12 are provided in the middle of the substrate 1. The upper and lower layers of the substrate 1 are connected through the through holes 12 to form a complete current path.

[0037] Furthermore, a plurality of equidistant solder balls 11 are disposed on the bottom surface of the substrate 1. The solder balls 11 are soldered and fixed on the substrate 1, serving as an interface for connecting the package structure with external circuits to realize the transmission of signals and power.

[0038] In summary, this application achieves the integration of multiple functional chips within the limited space of the substrate 1 by vertically stacking the SOC chip 3, memory chip 4, and flash memory chip 5, and rationally arranging the passive components 2. This greatly improves the integration of the packaging structure, conforms to the mainstream trend of system integration, and can meet the needs of miniaturization and high performance of electronic devices.

[0039] Meanwhile, memory chip 4 and flash memory chip 5 are interconnected with substrate 1 through bonding wires 9. The bonding wires 9 of the lower memory chip 4 are wrapped in DAF film 8, which not only ensures the reliability of the interconnection, but also reduces the space occupied by the bonding wires 9 and reduces the interconnection delay. This interconnection method makes the signal transmission path between chips and between chips and substrate 1 shorter, which helps to improve system performance.

[0040] As attached Figure 2-7 As shown, the processing procedure of this utility model is as follows:

[0041] Step 1: Use DAG technology to grind SOC chip 3 to 150um; use DAG to grind memory chip 4 to 100um; use DAG to grind flash memory chip 5 to 150um.

[0042] Step 2, bonding of passive components 2:

[0043] Passive components 2 are reflow soldered on substrate 1 using lead-free solder paste 10.

[0044] Step 3: Flip-mount the SOC chip 3 and fill the gaps between the bumps using filler adhesive 7:

[0045] Use underfill 7 to fill the bottom of SOC chip 3.

[0046] Step 4: Memory chip bonding and gold wire bonding:

[0047] The first layer memory chip 4 is bonded to the SOC chip 3 using a standard DAF.

[0048] The second layer memory chip 4 is vertically bonded using embedded wire DAF-FOW and the gold wire of the lower layer chip is wrapped around it.

[0049] The memory chip 4 is interconnected with the substrate 1 using 99.99% pure gold wire.

[0050] Step 5: Laying the top-layer flash memory chip 5:

[0051] The top-level flash memory chip 5 is bonded using a standard DAF.

[0052] Step Six: Injection Molding of Epoxy Resin Material

[0053] Products are encapsulated using epoxy resin materials.

[0054] Step 7: Plant the bulbs and cut them into individual pieces:

[0055] Solder balls 11 are soldered onto the ball pads on the back of substrate 1; at the same time, strip-level packaged products are cut into unit-level particles.

[0056] The above are merely specific application examples of this utility model and do not constitute any limitation on the scope of protection of this utility model; all technical solutions formed by equivalent transformation or equivalent substitution fall within the scope of protection of this utility model.

Claims

1. A system-in-package (SIP) structure for multi-chip stacking, characterized in that: It includes a substrate (1), passive components (2), SOC chip (3), memory chip (4), flash memory chip (5) and encapsulating resin (6); There are two passive components (2), and the two passive components (2) are symmetrically arranged on both sides of the top surface of the substrate (1); the SOC chip (3) is flip-chip mounted on the middle of the top surface of the substrate (1), and the SOC chip (3) and the substrate (1) are filled with underfill adhesive (7). There are two memory chips (4). The two memory chips (4) are stacked vertically on the SOC chip (3) in sequence. The two memory chips (4) are bonded and fixed together by a DAF film (8). Bonding lines (9) are provided on both sides of the two memory chips (4). The two memory chips (4) are interconnected with the substrate (1) through the bonding lines (9). The bonding line (9) on the lower memory chip (4) is wrapped in the DAF film (8) between the two memory chips (4). The flash memory chip (5) is stacked on the memory chip (4) located on the upper layer. The flash memory chip (5) is provided with multiple bonding lines (9). The flash memory chip (5) is interconnected with the substrate (1) through the multiple bonding lines (9). The encapsulating resin (6) is located above the substrate (1). The encapsulating resin (6) is used to encapsulate the passive components (2), SOC chip (3), memory chip (4) and flash memory chip (5) on the substrate (1).

2. The system-in-package structure for multi-chip stacking according to claim 1, characterized in that: The memory chip (4) located in the lower layer and the SOC chip (3) are bonded and fixed together by a DAF film (8), and the memory chip (4) located in the upper layer and the flash memory chip (5) are bonded and fixed together by a DAF film (8).

3. The system-in-package structure for multi-chip stacking according to claim 1, characterized in that: The molding resin (6) is epoxy resin, and the two sides of the molding resin (6) are flush with the two sides of the substrate (1).

4. A system-in-package structure for multi-chip stacking according to claim 1, characterized in that: A lead-free solder paste (10) is provided between the passive component (2) and the substrate (1). The passive component (2) is connected to the substrate (1) through the lead-free solder paste (10) and fixed by reflow soldering.

5. A system-in-package structure for multi-chip stacking according to claim 1, characterized in that: A plurality of equidistant solder balls (11) are provided on the bottom surface of the substrate (1), and the solder balls (11) are soldered and fixed on the substrate (1).

6. A system-in-package structure for multi-chip stacking according to claim 1, characterized in that: The substrate (1) has a double-layer structure, and multiple through holes (12) are provided in the middle of the substrate (1).

7. A system-in-package structure for multi-chip stacking according to claim 1, characterized in that: The bonding wire (9) is made of gold wire with a purity of 99%.

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