Semiconductor structure

Abstract

A semiconductor structure includes a substrate, a semiconductor nanosheet stack, a metal gate structure, a liner, and a dielectric layer. The semiconductor nanosheet stack is located above the substrate. The metal gate structure is located above the semiconductor nanosheet stack. The liner is disposed adjacent to the metal gate structure, wherein a vertical profile of the liner includes a bottom segment extending from a bottom end of the metal gate structure to a height above the bottom end of the metal gate structure, wherein the vertical profile of the liner includes a top segment extending from the height above the metal gate structure to a top end of the metal gate structure, wherein an angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees. The dielectric layer is disposed adjacent to the liner.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure. Background Technology

[0002] The electronics industry's growing demand for smaller, faster electronic devices that can support increasingly complex and sophisticated functions has led the semiconductor industry to continue its preference for manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, this demand has been largely met by shrinking the size of semiconductor ICs (e.g., the smallest feature size), thereby increasing production efficiency and reducing associated costs. However, this shrinkage also increases the complexity of semiconductor manufacturing processes. Therefore, continued advancements in semiconductor ICs and devices require similar advancements in semiconductor manufacturing processes and technologies.

[0003] Multi-gate devices have been introduced to improve gate control, reduce off-state current, and mitigate the short-channel effect (SCE) by increasing gate-channel coupling. One such multi-gate device introduced is the fin field-effect transistor (FinFET). The name FinFET comes from the fin-like structure that extends from and is formed on the substrate to form the FET channel. Another multi-gate device introduced to address the performance challenges associated with FinFETs is the gate-all-around (GAA) transistor. The name GAA comes from the gate structure that extends completely around the channel, thus providing better electrostatic control than FinFETs. Both FinFET and GAA devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes. Furthermore, the three-dimensional structure of such devices allows for aggressive scaling while maintaining gate control and mitigating SCE. Utility Model Content

[0004] According to some embodiments of this disclosure, a semiconductor structure includes a substrate, a stack of semiconductor nanosheets, a metal gate structure, a pad, and a dielectric layer. The semiconductor nanosheet stack is located above the substrate. The metal gate structure is located above the semiconductor nanosheet stack. A pad is disposed adjacent to the metal gate structure, wherein the vertical profile of the pad includes a bottom segment extending from the bottom end of the metal gate structure to a height above the bottom end of the metal gate structure, and a top segment extending from the height above the metal gate structure to the top end of the metal gate structure, wherein an angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees. A dielectric layer is disposed adjacent to the pad.

[0005] According to some embodiments of this disclosure, the semiconductor structure includes a metal gate and a pad. The metal gate is located above a stack of nanosheet channels. The pad surrounds the sidewalls of the metal gate, wherein the vertical profile of the pad includes a bottom segment extending from the bottom end of the metal gate to a height above the bottom end of the metal gate, and wherein the vertical profile of the pad includes a top segment extending from the height above the metal gate to the top end of the metal gate, wherein an angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees.

[0006] According to some embodiments of this disclosure, a semiconductor structure includes a metal gate, a nanosheet channel stack, and a low-k pad. The metal gate is located above the nanosheet channel stack and has sidewalls extending from its bottom end to its top end. The low-k pad is composed of silicon, oxygen, carbon, and / or nitrogen and surrounds the sidewalls of the metal gate. The vertical profile of the low-k pad includes a bottom segment extending from the bottom end of the metal gate to a height above the bottom end of the metal gate. The vertical profile of the low-k pad includes a top segment extending from a height above the metal gate to the top end of the metal gate. An angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figure 1 This is a plan view of the layout of a multi-gate device according to some embodiments;

[0009] Figure 2 A flowchart illustrating a method according to some embodiments;

[0010] Figures 3 to 14 According to some embodiments Figure 2 A cross-sectional view of a semiconductor device during the continuous manufacturing phase;

[0011] Figure 15 This is a flowchart of a sidewall trimming process according to some embodiments;

[0012] Figures 16 to 24 According to some embodiments Figure 15 A cross-sectional view of a semiconductor device during the continuous manufacturing phase of the process.

[0013] [Symbol Explanation]

[0014] 8-8: Line

[0015] 10: Semiconductor substrate, substrate

[0016] 11: Lattice unit

[0017] 20: Parallel Active Region

[0018] 30: Parallel gate line

[0019] 100: Device

[0020] 200: Semiconductor device, apparatus

[0021] 202:Substrate

[0022] 205: Central Section

[0023] 212: Epitaxial Stacking

[0024] 214: Epitaxial layer, layer

[0025] 216: Epitaxial layer, layer

[0026] 217: Masking layer

[0027] 218: First mask layer

[0028] 219: Second masking layer

[0029] 220: Fins

[0030] 220a: Partial

[0031] 221: STI features, isolation features

[0032] 222: Sacrificial gate structure

[0033] 223: Sacrificial gate dielectric layer

[0034] 224: Sacrificial gate electrode

[0035] 225~227: Masking layer

[0036] 230: Spacer

[0037] 231: Lining layer

[0038] 232: Main Spacing Layer

[0039] 233: Bottom gap surface

[0040] 234: Depression

[0041] 235: Fin segment

[0042] 300: Isolation layer

[0043] 400: Source / Drain Characteristics

[0044] 440: Pad

[0045] 450: Dielectric layer, ILD

[0046] 460: Hard Mask

[0047] 498: Bottom of the chamber

[0048] 499: Gate cavity

[0049] 500: Metal gate

[0050] 501-503: Gate Structure

[0051] 505: Metal

[0052] 510: External gate portion

[0053] 520: Inner gate portion

[0054] 521: Lowest inner gate portion

[0055] 522: Middle inner gate portion

[0056] 523: Topmost inner gate portion

[0057] 540: Gate dielectric layer

[0058] 550: Gate electrode material

[0059] 560: Semiconductor Nanosheets

[0060] 561: Lowest level nanosheet

[0061] 562: Intermediate Nanosheets

[0062] 563: Top layer nanosheets

[0063] 599: Surface

[0064] 700: Sidewall spacers

[0065] 701: Part One

[0066] 702: Part Two

[0067] 710: Low-K spacer layer

[0068] 711~713: Sublayer

[0069] 720: Etching stop layer

[0070] 721: Sublayer

[0071] 722: Sublayer

[0072] 790: Top

[0073] 791: Bottom Segment

[0074] 792: Top Segment

[0075] 800: Electrical contacts

[0076] 810: Interlayer material

[0077] 900: Interconnection Structure

[0078] 910: Dielectric layer

[0079] 920: Metallization layer

[0080] 1000: Method

[0081] 2162: Internal spacer

[0082] 2169: Gap

[0083] S1010, S1020, S1030, S1040, S1050, S1060, S1070, S1080, S1090, S1100, S1110, S1120, S1130, S1140, S1150, S1160, S1170, S1510, S1520, S1530, S1540: Process

[0084] A1:Angle

[0085] D1: Bottom critical dimension

[0086] D2: Top critical size

[0087] H0, H5: Height

[0088] X, Y, Z: Direction Detailed Implementation

[0089] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0090] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “above,” “upper,” “top,” “top,” “below,” “submerged,” “below,” “under,” “lower,” “bottom,” “side,” etc., may be used herein to describe the relationship between one element or feature and another illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0091] In some embodiments herein, a “material layer” is a layer comprising at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, or at least 90% by weight, or substantially 100% by weight of an identified material; and a layer as “material” comprises at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, or at least 90% by weight, or substantially 100% by weight of an identified material. For example, in some embodiments, a titanium nitride layer and each of the titanium nitride layers is a layer of at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, or at least 95% by weight, or substantially 100% by weight of titanium nitride.

[0092] For the sake of brevity, this document may not describe in detail the conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionalities not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the description may represent multiple components.

[0093] Figure 1 The lattice unit 11 in the semiconductor device 100, i.e., a portion of the semiconductor substrate 10, is described. As shown, parallel active regions 20 are spaced apart from each other and extend along the X direction. Furthermore, parallel gate lines 30 are spaced apart from each other and extend along the Y direction, perpendicular to the X direction. Exemplary gate lines 30 are formed of a conductive material (such as a metal) and form the gate structure of the device 100.

[0094] Semiconductor device 100 may be a multi-gate device 100. In various embodiments, multi-gate device 100 may include a FinFET device, a GAA transistor, or other types of multi-gate device. Multi-gate device 100 is formed over substrate 10.

[0095] Multi-gate device 100 may include a P-type metal-oxide-semiconductor device 100 or an N-type metal-oxide-semiconductor multi-gate device 100. Due to the fin structure, specific examples of which may be presented herein and referred to as FinFET device 100 are also presented herein. An embodiment of a multi-gate transistor type referred to as a gate-all-around (GAA) device 100 is also presented herein. GAA device 100 includes any device having a gate structure or a portion thereof formed on all four sides of a channel region (e.g., around a portion of the channel region). Devices described herein also include embodiments having channel regions disposed in nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. The terms "nanosheet" or "nanosheet channel" as used herein are intended to include nanowire channel and strip channel configurations.

[0096] In some embodiments, substrate 10 may be a semiconductor substrate, such as a silicon substrate. Substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 10 may include various doping configurations known in the art, depending on design requirements. Substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 10 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 10 may optionally include an epitaxial layer, which may be strainable to improve performance, and may include a silicon-on-insulator (SOI) structure and / or have other suitable reinforcing features.

[0097] This document describes embodiments of devices that may have one or more channel regions (e.g., nanosheets) associated with a gate structure. For example, a stack of vertically spaced nanosheet channels may be provided. However, those skilled in the art will recognize that this teaching is applicable to a single channel (e.g., a single nanosheet) or any number of channels. Other examples of semiconductor devices that may benefit from the manner of this disclosure will be recognized by those skilled in the art.

[0098] It has been found that metal gate extrusion can suppress the performance of devices with nanosheet channel regions. Metal gate extrusion can create an electrical path between the gate and the source / drain feature. As used herein, "source / drain region" or "source / drain feature" may refer to the source or drain individually or collectively, depending on the context. The electrical path between the gate and the source / drain feature results in unwanted leakage current.

[0099] When a metal gate is formed with a stepped profile, metal gate squeezing may occur. Specifically, the upper portion of the metal gate has a larger lateral width or critical dimension than the lower portion. Therefore, the lateral distance between the upper portion of the metal gate and the adjacent region above the source / drain features (such as the location forming contact with the source / drain features) is shorter. This shorter lateral distance can lead to unwanted metal gate squeezing and leakage current.

[0100] To improve device RO% boost, low-k films can be used as sidewall spacers formed on the sacrificial gate. During the sidewall spacer trimming process, harder materials can be used as sacrificial layers, as these materials are more resistant to oxide etching processes. However, it has been found that oxide etching processes result in a top-to-bottom oxidation rate load. Specifically, at higher locations, more material to be removed is converted to oxide, while at lower locations, less material is converted to oxide. This trend is more pronounced for low-k sidewall spacers because their oxidation rate is much faster than that of harder sacrificial layers. Therefore, it has been found that oxide etching processes used to remove part of the low-k sidewall spacers result in a stepped profile and uneven thickness for the remaining portion of the low-k sidewall spacers. Specifically, the thickness of the oxide-etched low-k sidewall spacers is greatest at the bottom of the sidewall and includes steps from a thicker lower portion to a thinner middle portion. This stepped structure is more prone to metal gate extrusion defects and reduces RO%.

[0101] Some embodiments described herein prevent the formation of sidewall spacers with stepped profiles. For example, some embodiments include performing an oxide etching process or a sidewall trimming process under high pressure to allow for a more uniform reactant distribution during oxidation. A more uniform reactant distribution reduces the oxidation rate load from top to bottom. In other words, the uniform lateral thickness of the material to be removed is converted into oxide at higher and lower locations along the sidewall. Therefore, the sidewall pads are formed with a more linear profile, such as a more vertical profile, and a more uniform lateral thickness. Consequently, when the metal gate contacts the sidewall pads, the metal gate has a more linear profile, i.e., a more vertical profile. More specifically, the metal gate is formed without any lateral steps from the thinner portion to the thicker portion.

[0102] Some embodiments relate to a method for fabricating nanosheet FETs using an improved dummy polysilicon sidewall spacer trimming process. Specifically, some embodiments involve forming dummy polysilicon trench structures with less top-to-bottom critical size load and more uniform spacer layer thickness. These features may be beneficial for reducing gate-to-source / drain leakage and improving RO% device performance.

[0103] In some embodiments, the gate cavity is formed by removing a sacrificial or dummy polysilicon gate structure, followed by a sidewall spacer trimming process. The sidewall spacer trimming process is performed under increased oxidation stress, followed by an oxide removal etching process.

[0104] High-pressure oxidation provides a more uniform top-to-bottom distribution of reactants, resulting in a uniform oxide layer from the low-k material. Therefore, the sidewall spacer trimming process achieves a more vertical profile with uniform spacer thickness. The metal gate formed on the sidewall spacers then also has a vertical profile, thereby reducing the risk of metal gate extrusion and minimizing defect problems by increasing the spacing between the metal gate (MG) and the source / drain contacts (MD). In some embodiments, the process avoids forming a metal gate with a stepped shape, which can be beneficial for defects and electrical performance.

[0105] Therefore, the embodiments described herein reduce the risk of metal gate extrusion, reduce effective capacitance, and improve RO% performance.

[0106] As device size shrinks in nanosheet FET technology, sidewall spacer trimming processes may be key to achieving metal gate profile modulation with fewer defects, thereby improving device performance and yield.

[0107] The embodiments disclosed herein offer advantages over the prior art, but it should be understood that other embodiments may offer different advantages, but not all advantages are necessarily discussed herein, and not all embodiments need to have a particular advantage.

[0108] See Figure 2 This document describes a method 1000 for manufacturing a semiconductor device 200 (such as a multi-gate device 100) according to various embodiments. The method 1000 is discussed below with reference to a GAA device 200 having a channel region, which may be referred to as a nanosheet or nanosheet channel, and may include various geometries (e.g., cylindrical, strip-shaped) and sizes. However, it should be understood that the form of method 1000 can be equally applied to other types of multi-gate devices without departing from the scope of this disclosure. In some embodiments, method 1000 can be used to manufacture devices described above. Figure 1 The multi-gate device 100 is described. Therefore, one or more states discussed above with reference to the multi-gate device 100 can also be applied to method 1000. It should be understood that method 1000 includes steps with complementary metal-oxide-semiconductor (CMOS) technology process flow characteristics, and therefore, is only briefly described herein. In addition, other steps may be performed before, after, and / or during method 1000.

[0109] See below Figures 3 to 14Description method 1000, Figures 3 to 14 Provide a perspective view of the multi-gate device 200 or a cross-sectional view of the multi-gate device 200 along a plane, which is parallel to... Figure 1 The planes defined by the Y-axis and Z-axis are substantially parallel, as described above, illustrating the various manufacturing stages according to method 1000.

[0110] Furthermore, the semiconductor device 200 may include various other devices and features, such as other types of devices, such as additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM), and / or other logic circuits, but simplifications are provided for a better understanding of the concepts disclosed herein. In some embodiments, the semiconductor device 200 includes multiple semiconductor devices (e.g., transistors), including PFETs, NFETs, etc., which may be interconnected. It should also be noted that the process steps of method 1000 (including any descriptions given with reference to the accompanying drawings) are illustrative only and are not intended to limit the scope beyond what is specifically described in the following new application.

[0111] In operation S1010, method 1000 provides substrate 202, such as Figure 3 As shown. In some embodiments, substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. Substrate 202 may include various layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 202 may include various doping configurations known in the art, depending on design requirements. For example, different doping profiles (e.g., p-well, n-well) may be formed in regions on substrate 202 designed for different device types (e.g., n-type field-effect transistors (NFETs) and p-type field-effect transistors (PFETs)). Suitable doping may include ion implantation and / or diffusion processes of dopants, such as boron (B) for p-wells and phosphorus (P) for n-wells. In some embodiments, substrate 202 includes a single-crystal semiconductor layer at least on its surface portion. Substrate 202 may include single-crystal semiconductor materials, such as, but not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. Alternatively, substrate 202 may include compound semiconductors and / or alloy semiconductors. In the illustrated embodiment, the substrate 202 is made of crystalline Si.

[0112] like Figure 3 As shown, in operation S1020, method 1000 ( Figure 2One or more epitaxial layers are formed over a substrate 202. In some embodiments, an epitaxial stack 212 is formed over the substrate 202. The epitaxial stack 212 includes an epitaxial layer 214 of a first composition, with an epitaxial layer 216 of a second composition interposed therebetween. The first and second compositions may be different. Embodiments may include those providing a first and second composition with different oxidation rates and / or etch selectivity. In an embodiment, epitaxial layer 214 is SiGe, and epitaxial layer 216 is silicon. In an embodiment where epitaxial layer 214 comprises SiGe and epitaxial layer 216 comprises silicon, the silicon oxidation rate is lower than the SiGe oxidation rate. It should be noted that... Figure 3 The description of three epitaxial layers 214 and 216 is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It is understood that any number of epitaxial layers can be formed in the epitaxial stack 212; the number of layers depends on the number of channel regions required by the GAA device 200. In some embodiments, the number of epitaxial layers 216 is between 2 and 10, such as 6 or 7.

[0113] In some embodiments, the thickness of epitaxial layer 214 ranges from about 5 nanometers to about 15 nanometers. The thickness of epitaxial layer 214 may be substantially uniform. In some embodiments, the thickness of epitaxial layer 216 ranges from about 5 nanometers to about 15 nanometers. In some embodiments, the thickness of the stacked epitaxial layers 216 is substantially uniform. As described in more detail below, epitaxial layer 216 may be used as a channel region for a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations. Epitaxial layer 214 may be used to define the gap between adjacent channel regions of a subsequently formed multi-gate device, and its thickness is selected based on device performance considerations.

[0114] For example, the epitaxial growth of the epitaxial stack 212 can be performed using molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes. In some embodiments, the epitaxial growth layer (such as epitaxial layer 216) comprises the same material as the substrate 202. In some embodiments, epitaxial growth layers 214 and 216 comprise materials different from the substrate 202. As described above, in at least some instances, epitaxial layer 214 comprises epitaxially grown Si. 1-x Ge xThe epitaxial layer 214 comprises a silicon (Si) layer epitaxially grown (where x is about 10 to about 55%). Alternatively, in some embodiments, either of the epitaxial layers 214 and 216 may comprise other materials such as germanium, compound semiconductors (such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide), alloy semiconductors (such as SiGe, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP and / or GaInAsP), or combinations thereof. As discussed, the materials of the epitaxial layers 214 and 216 may be selected based on providing different oxidation, etch selectivity characteristics. In various embodiments, the epitaxial layers 214 and 216 are substantially dopant-free (i.e., having about 0 cm⁻¹). -3 To approximately 1×10 17 cm -3 The concentration of external dopant is specified, wherein, for example, no intentional doping is performed during the epitaxial growth process. In some embodiments, the bottom and top layers of the epitaxial stack 212 are SiGe layers (not shown). In an alternative embodiment, the bottom layer of the epitaxial stack 212 is a Si layer, and the top layer of the epitaxial stack 212 is a SiGe layer (not shown).

[0115] like Figure 3 and Figure 4 As shown, in operation S1030, method 1000 ( Figure 2 The epitaxial stack 212 is patterned to form semiconductor fins 220. In some embodiments, operation S1030 includes forming a masking layer 217 over the epitaxial stack 212, such as... Figure 3 As shown. Masking layer 217 includes a first masking layer 218 and a second masking layer 219. The exemplary first masking layer 218 is a pad oxide layer made of silicon oxide, which can be formed by thermal oxidation. The exemplary second masking layer 219 is made of silicon nitride (SiN) and can be formed by chemical vapor deposition (CVD), including low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. Masking layer 217 is patterned into a mask pattern using patterning operations including lithography and etching. Subsequently, operation S1030 patternes epitaxial stack 212 in an etching process (such as dry etching (e.g., reactive ion etching), wet etching, and / or other suitable processes) through openings defined in the patterned masking layer 217. The stacked epitaxial layers 214 and 216 are thus patterned into fins 220. Although Figure 4This describes the formation of one fin 220, but any suitable number of fins can be formed. Grooves are etched between adjacent fins 220.

[0116] In various embodiments, each fin 220 includes an upper portion of staggered epitaxial layers 214 and 216, and a bottom portion formed by etching the substrate 202. Each fin 220 projects upward from the substrate 202 in the Z direction and extends longitudinally in the Y direction. The sidewalls of each fin 220 may be straight or inclined (not shown). Figure 4 In the middle, the additional fins will be spaced apart along the Y direction. The fins 220 may have the same width or different widths.

[0117] like Figure 5 As shown, in operation S1040, method 1000 ( Figure 2 Shallow trench isolation (STI) features (also referred to as STI features) 221 are formed in the trenches adjacent to each fin 220 using a dielectric layer. The STI feature 221 can be formed by first filling the trenches around each fin 220 with a dielectric material layer to cover the top surface and sidewalls (not shown) of the fin 220. The dielectric material layer may include one or more dielectric materials. Suitable dielectric materials for the dielectric layer may include silicon oxide, silicon nitride, silicon carbide, fluorosilicate glass (FSG), low-k dielectric materials, and / or other suitable dielectric materials. The dielectric material can be deposited using any suitable technique, including thermal growth, flowable CVD (FCVD), HDP-CVD, PVD, ALD, and / or spin coating. Then, the dielectric material layer is planarized using, for example, chemical mechanical planarization (CMP) until the top surface of the masking layer 217 is exposed, and the dielectric material layer is recessed to form a shallow trench isolation (STI) feature (also referred to as STI feature) 221, such as... Figure 5 As shown. In the illustrated embodiment, STI feature 221 is formed on substrate 202. Any suitable etching technique can be used to recess the isolation feature 221, including dry etching, wet etching, RIE and / or other etching methods, and in the exemplary embodiment, anisotropic dry etching is used to selectively remove the dielectric material of the isolation feature 221 without etching the fins 220. The masking layer 217 (e.g., ...) can also be removed before, during and / or after recessing the isolation feature 221. Figure 4 (As shown). In some embodiments, the mask layer 217 is removed by a CMP process performed prior to recessing the isolation feature 221. In some embodiments, the mask layer 217 is removed by an etchant used to recess the isolation feature 221.

[0118] like Figure 6 As shown, in operation S1050, method 1000 ( Figure 2 A sacrificial (dummy) gate structure 222 is formed. The sacrificial gate structure 222 is formed over portions of the fins 220 that will serve as channel regions. The sacrificial gate structure 222 may extend over multiple adjacent fins (not shown). The sacrificial gate structure 222 is directly located over and defines the channel region of the GAA device to be formed. Each sacrificial gate structure 222 includes a sacrificial gate dielectric layer 223 and a sacrificial gate electrode 224 located above the sacrificial gate dielectric layer 223. As shown, the sacrificial gate structures 222 extend longitudinally in the Y direction and are spaced apart in the X direction.

[0119] A sacrificial gate structure 222 is formed by first depositing a sacrificial gate dielectric layer over fin 220. A sacrificial gate electrode layer is then deposited over the sacrificial gate dielectric layer and over fin 220. The sacrificial gate dielectric layer comprises silicon oxide, silicon nitride, or a combination thereof. In some embodiments, the thickness of the sacrificial gate electrode layer ranges from about 100 nanometers to about 200 nanometers. The sacrificial gate electrode 224 comprises silicon, such as polycrystalline silicon or amorphous silicon. In some embodiments, the thickness of the sacrificial gate dielectric layer ranges from about 1 nanometer to about 5 nanometers. In some embodiments, the sacrificial gate electrode layer undergoes a planarization operation. The sacrificial gate dielectric layer and the sacrificial gate electrode layer are deposited using CVD, including LPCVD and PECVD, PVD, ALD, or other suitable processes. A masking layer 225 is formed over the sacrificial gate electrode layer. The masking layer 225 may include a masking layer 226 (such as silicon oxide) and a masking layer 227 (such as silicon nitride). Subsequently, the mask layer 225 is patterned to pattern the sacrificial gate electrode layer and the sacrificial gate dielectric layer into a sacrificial gate structure 222, including a sacrificial gate dielectric layer 223 and a sacrificial gate electrode 224.

[0120] As shown in the figure, fins 220 are partially exposed between and above the opposite sides of the sacrificial gate structure 222, thereby defining the source / drain (S / D) region. In this disclosure, the source and drain are interchangeable and have essentially the same structure.

[0121] See also Figure 6 At operation S1060, method 1000 ( Figure 2Spacers 230 are formed on the sidewalls of the sacrificial gate structure 222 and the sidewalls of the fin 220 by depositing spacer material followed by etching. Spacers 230 may include spacer materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or combinations thereof. In some embodiments, each spacer 230 includes multiple layers, such as a pad layer 231 and a main spacer layer 232 located on the sidewall of the pad layer 231. For example, spacers 230 can be formed by depositing spacer material over the sacrificial gate structure 222 using processes such as subatmospheric CVD (SACVD), flowable CVD, ALD, PVD, or other suitable processes, the spacer material comprising a pad material layer and a dielectric material layer.

[0122] like Figure 7 As shown, after depositing the pad material layer and dielectric material layer, an etchback (e.g., anisotropically) is performed at operation S1070 to expose and remove the portion 220a (e.g., the S / D region) of the fin 220 adjacent to the sacrificial gate structure 222 and not covered by the sacrificial gate structure 222. The pad material layer and dielectric material layer may remain on the sidewalls of the sacrificial gate structure 222 as gate sidewall spacers 230, and on the sidewalls of the fin as fin sidewall spacers 230. In some embodiments, the etchback process may include a wet etching process, a dry etching process, a multi-step etching process, and / or a combination thereof. The thickness of the spacer 230 may range from about 5 nanometers to about 20 nanometers.

[0123] Cross-reference Figure 7 and Figure 8 (X-section view), in operation S1070, method 1000 ( Figure 2 The steps include: forming an inner spacer 2162 that is laterally adjacent to the epitaxial layer 216.

[0124] For example, operation S1070 may include recessing a portion of the fin 220 not covered by the sacrificial gate structure 222 to form a gap or recess 234 in the S / D region. It should be noted that... Figure 7 Only one adjacent portion of the sacrificial gate structure 222 and fin 220 is shown to provide a clearer view. Figure 6 Etching of the S / D region between the sacrificial gate structure 222. Figure 8 For along Figure 7 The cross-sectional view of line 8-8 in the figure illustrates three sacrificial gate structures 222 and fins 220 located below the sacrificial gate structures 222.

[0125] like Figure 8The most clearly shown example is the etching of the stacked epitaxial layers 214 and 216 onto the bottom gap surface 233 formed by the fins 220. In many embodiments, operation S1070 forms the recesses 234 by a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof. As a result of the etching process, the fin segments 235 of the upper portion of the fins 220 are defined by the recesses 234 and separated from each other.

[0126] Furthermore, operation S1070 may include lateral etching of the second epitaxial layer 216. In an exemplary embodiment, a SiGe etch-back process is performed to laterally recess the layer 216. This forms a pocket portion laterally adjacent to the layer 216 and perpendicular to the layer 214. Operation S1070 includes forming an inner spacer 2162 within the pocket portion. In an exemplary embodiment, the inner spacer 2162 may be formed of silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride, silicon carbide oxide, silicon carbide oxynitride, and / or other suitable dielectric materials. The inner spacer 2162 may be formed by ALD or any other suitable method. As shown, after depositing the material forming the inner spacer 2162, the material may be trimmed from the sidewalls of the epitaxial layer 214.

[0127] The method can continue at operation S1080, where source / drain characteristics 400 are formed, such as Figure 9 As shown. Figure 9 This is a cross-sectional view of the X-section. In an exemplary embodiment, the source / drain feature 400 is formed by epitaxial growth. For example, operation S1080 may include selectively growing an epitaxial material over the isolation layer 300 to form the source / drain feature 400. In an exemplary embodiment, the source / drain feature 400 is a strained source / drain feature 400.

[0128] In an exemplary embodiment, the source / drain feature 400 may include n-type epitaxial material source / drain features and p-type epitaxial material source / drain features. For an n-channel FET, the epitaxial material may include one or more layers of Si, SiP, SiC, and SiCP; for a p-channel FET, the epitaxial material may include Si, SiGe, and Ge. For a p-channel FET, the source / drain may also contain boron (B). The source / drain epitaxial layers may be formed using epitaxial growth methods such as CVD, ALD, or molecular beam epitaxy (MBE).

[0129] exist Figure 10In method 1000, the steps include: at operation S1090, covering the source / drain feature 400 with a dielectric layer. Specifically, a dielectric pad 440 may be formed over the source / drain feature 400 and along the side of the spacer 230. Furthermore, a dielectric layer 450 may be formed over the pad 440 over the source / drain feature 400. Specifically, the recess 234 is filled with the dielectric layer 450. In an exemplary embodiment, the dielectric layer 450 is a first interlayer dielectric layer (ILD). The dielectric layer 450 may be silicon oxide or other suitable dielectric material. In some embodiments, the dielectric pad 440 is a dielectric, such as silicon nitride or other suitable material.

[0130] like Figure 11 As further shown, method 1000 includes the following steps: at operation S1100, the sacrificial gate structure 222 is opened and removed. Specifically, a chemical mechanical planarization (CMP) process may be performed to remove the masking layer 225 and expose the sacrificial gate electrode 224. Furthermore, the sacrificial gate electrode 224 is removed to form a gate cavity 499. As shown, the gate cavity 499 is defined by spacers 230 and an uppermost epitaxial layer 214. Figure 11 This is a cross-sectional view of section X.

[0131] like Figure 2 The explanation and Figures 15 to 23 As shown, method 1000 includes the following steps: at operation S1110, the sidewall spacers 230 are trimmed, as described below.

[0132] exist Figure 12 In method 1000, the second epitaxial layer 216 is removed in operation S1140. This forms gaps 2169 between the first epitaxial layers 214. In this manner, the first epitaxial layers 214 are formed as vertically spaced semiconductor nanosheets 560. The nanosheets 560 include a lowest nanosheet 561, a highest or uppermost nanosheet 563, and intermediate nanosheets or nanosheets 562. Figure 12 This is a cross-sectional view of section X.

[0133] exist Figure 13 In the method 1000, the steps include: at operation S1150, completing a replacement metal gate process to form a gate structure 500, such as gate structure 501, gate structure 502 and gate structure 503. Figure 13 This is a cross-sectional view of section X.

[0134] In an exemplary embodiment, the replacement metal gate process includes: forming a gate dielectric layer 540 in the gate cavity 499 and the gap 2169; and forming a gate electrode material 550 over the gate dielectric layer 540 to fill the gate cavity 499 and the gap 2169.

[0135] An exemplary gate dielectric layer 540 is conformally deposited in the gate cavity 499 and the gap 2169. The gate dielectric layer 540 may be formed on the semiconductor nanosheet 560, and the gate electrode material 550 may be formed on the gate dielectric layer 540. Thus, each semiconductor nanosheet 560 is encapsulated in the gate dielectric layer 540 and surrounded by the gate electrode material 550.

[0136] According to some embodiments, the gate dielectric layer 540 comprises silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layer 540 is a high-k dielectric material, and in these embodiments, the gate dielectric layer 540 may have a k value greater than about 7.0, and may include metal oxides or silicates of Hf, Al, Zr, La, Mg, Ba, Ti, Pb, and combinations thereof. Methods for forming the gate dielectric layer 540 may include molecular-beam deposition (MBD), ALD, PECVD, etc.

[0137] Gate electrode material 550 is deposited over gate dielectric layer 540 and fills the remainder of the gate cavity. Gate electrode material 550 may be a metallic material, such as TiN, TaN, TaC, Co, Ru, Al, combinations thereof, or multiples thereof. For example, although a single gate electrode material is described, any number of work function adjustment layers may be deposited.

[0138] like Figure 13 As shown, the replacement metal gate process further includes removing excess portions of the gate dielectric layer 540 and gate electrode material 550 located above the top surface of the ILD 450. For example, a planarization process (such as a CMP process) can be performed to remove excess portions of the gate dielectric layer 540 and gate electrode material 550. Thus, the device 200 has an upper surface 599. The remaining material portions of the gate dielectric layer 540 and gate electrode material 550 thus form a replacement gate structure 500 of the resulting device 200. The gate dielectric layer 540 and gate electrode material 550 may be collectively referred to as a “gate,” a “gate stack,” or a “gate structure.” Each gate structure 500 may extend along the sidewall of the channel region of the fin structure.

[0139] like Figure 13As shown, each metal gate 500 includes an upper or outer gate portion 510 located above the uppermost nanosheet 563. Furthermore, each metal gate 500 includes an inner gate portion 520 located below the uppermost nanosheet 563. Specifically, each metal gate 500 includes an uppermost inner gate portion 523 located directly below the uppermost nanosheet 563, a lowest inner gate portion 521 located directly below the lowest nanosheet 561, and a middle inner gate portion 522 located directly above the lowest nanosheet 561. Each metal gate 500 is located directly above the center portion 205 of the substrate 202.

[0140] like Figure 14 As shown, method 1000 can continue at operation S1160, wherein electrical contact 800 is formed.

[0141] Operation S1160 may include forming a dielectric material over device 200. For example, a layer such as a contact etch stop layer (CESL) or a capping layer may be formed over surface 599. In an exemplary embodiment, the CESL layer has a vertical thickness of 1 to 5 nanometers in the Z direction.

[0142] Furthermore, operation S1160 may include forming a second interlayer dielectric (ILD) layer over the CESL layer. In some embodiments, the second interlayer dielectric (ILD) layer is silicon oxide or another suitable material. In some embodiments, the second ILD layer and the first ILD layer 450 are the same material, such as silicon oxide.

[0143] Furthermore, operation S1160 may include performing an etching process to form an upper opening extending to the selected source / drain feature 400. Additionally, operation S1160 may include forming silicide on the selected source / drain feature 400.

[0144] Then, operation S1160 may include filling the opening above the silicide with a conductive material. In some embodiments, the conductive material includes a metal, such as tungsten (W) or other suitable material. A planarization process may be performed to remove the covering portion of the conductive material above the dielectric layer 450. Operation S1160 forms conductive contacts 800 (i.e., source / drain contacts 800) to selected source / drain features 400.

[0145] Method 1000 can continue with further processing in operation S1170. For example, dielectric layer 910 and metallization layer 920 can be deposited and etched to form interconnect structure 900, such as... Figure 14As shown. Further processing may include other back end-of-line (BEOL) processes, such as passivation and packaging.

[0146] Figure 15 A flowchart illustrating the sidewall trimming process of operation S1110 according to some embodiments.

[0147] Figures 16 to 23 According to some embodiments Figure 15 A cross-sectional view of a semiconductor device during the continuous manufacturing phase of the process.

[0148] Figure 16 This describes an embodiment of the device 100 after operation S1060, where the sacrificial gate structure 222 is opened and removed to form the gate cavity 499. As shown, the cavity 499 extends to a cavity bottom 498, which is defined by an interlayer material 810 formed over the fin prior to the formation of the sacrificial gate structure. The interlayer material 810 may be an oxide, such as silicon oxide.

[0149] The sides of chamber 499 are surrounded by more than one layer of sidewall spacers 700. As shown, the low-k spacer layer 710 may be the innermost layer. Specifically, the low-k spacer layer 710 may be formed directly on the sacrificial gate structure. In some embodiments, the low-k spacer layer 710 is formed of a low-k material including carbon and nitrogen. In some embodiments, the low-k spacer layer 710 is formed of a low-k material including silicon, carbon, nitrogen, and / or oxygen. In an embodiment, the low-k spacer layer 710 is formed of SiOCN.

[0150] The low-k spacer layer 710 may include sublayers 711, 712, and 713. For example, sublayer 711 may be a soft low-k spacer sublayer 711, sublayer 712 may be a low-k hard shell sublayer 712, and sublayer 713 may be an NFD+KC3P sublayer 713.

[0151] As shown in the figure, the etch stop layer 720 is formed directly on the low-k spacer layer 710. In some cases, the etch stop layer 720 or the contact etch stop layer (CESL) 720 is formed of a nitride material. For example, the etch stop layer 720 may be formed of silicon nitride. For example, the etch stop layer 720 may be Si3N4.

[0152] The etch stop layer 720 may include sublayer 721 and sublayer 722. For example, sublayer 721 may be a low-k CESL sublayer, while sublayer 722 may be a silicon nitride CESL sublayer 722.

[0153] exist Figure 16In this embodiment, a hard mask 460 is formed above the ILD 450. In some embodiments, the hard mask 460 is a nitride, such as silicon nitride. For example, the hard mask 460 may be Si3N4. In some embodiments, the ILD 450 is an oxide, such as silicon oxide. For example, the ILD 450 may be SiO2.

[0154] Each nanosheet 214 can be a silicon-germanium (SiGe) film.

[0155] Process S1110 may include, at stage S1510, performing a first sidewall spacer treatment, such as Figure 17 As shown. Specifically, operation S1510 may include inducing a chemical reaction in a gaseous, radical, or plasma mode using any combination of gases, N2, H2, or O2, at a chamber pressure of 0.003 to about 3 Torr. For example, operation S1510 may be performed at a pressure of at least 1 Torr, such as at least 1.25 Torr, at least 1.5 Torr, at least 1.65 Torr, at least 1.8 Torr, or at least 2 Torr. In some embodiments, the process conditions are a flow rate of 3840 sccm N2 + 160 sccm H2 + 6000 sccm O2.

[0156] exist Figure 17 In this process, the first portion 701 of the low-k spacer layer 710 is transformed into a material that is easier to remove. Specifically, the first portion 701 of the low-k spacer layer 710 is oxidized.

[0157] Process S1110 may include performing a first removal process at stage S1520, such as... Figure 18 As shown. Specifically, operation S1520 may include performing wet chemical etching using an HF solution diluted in DI water at any suitable ratio. In some embodiments, the HF:DI water ratio is 1:500.

[0158] Process S1110 may include performing a second sidewall spacer treatment at stage S1530, such as Figure 19 As shown. Specifically, operation S1530 may include inducing a chemical reaction in a gaseous, free radical, or plasma mode using any combination of gaseous, free radical, or plasma modes at a chamber pressure of 0.003 to about 3 Torr. For example, operation S1530 may be performed at a pressure of at least 1 Torr, such as at least 1.25 Torr, at least 1.5 Torr, at least 1.65 Torr, at least 1.8 Torr, or at least 2 Torr. In some embodiments, the process conditions are a flow rate of 3840 sccm N2 + 160 sccm H2 + 6000 sccm O2.

[0159] exist Figure 19 In this process, the second portion 702 of the low-k spacer layer 710 is transformed into a material that is easier to remove. Specifically, the second portion 702 of the low-k spacer layer 710 is oxidized.

[0160] Process S1110 may be included at stage S1540, performing, as follows Figure 20 The second removal process is shown. Specifically, operation S1540 may include performing dry chemical etching using a gas mixture of HF and NH3 at a chamber pressure of 0.1 to 1 Torr. In some embodiments, the process conditions include using HF:NH3 in a 1:4 ratio at 0.3 Torr. In some embodiments, the lateral thickness (i.e., in the X direction) is 1 to 10 nm, for example 2 to 8 nm, 4 to 6 nm, or about 5 nm.

[0161] Phase S1540 completes the trimming operation S1110.

[0162] Figures 20 to 23 Explanation based on Figure 2 Further operations of method 1000.

[0163] like Figure 21 As shown, method 1000 may include the following steps: at operation S1140, removing epitaxial layer 216.

[0164] Furthermore, method 1000 may include the following step: at operation S1150, completing the gate replacement process. For example, as... Figure 22 As shown, metal 505 can be deposited in the gate cavity 499. Furthermore, as... Figure 23 As shown, the covering portion of metal 505 can be removed (e.g., by planarization) to form metal gate 500.

[0165] As described above, method 1000 can continue to form contacts with selected source / drain characteristics.

[0166] Figure 24 This describes certain dimensions of the device 100 manufactured according to method 1000. As shown, the height of the bottom of the chamber or metal gate is H0. Height H5 is 5 nanometers higher than height H0.

[0167] As shown in the figure, the sidewall spacer 700 extends upward from the bottom chamber surface H0 and terminates at the top 790. Figure 24The vertical profile of the sidewall spacer liner (cut along X) is illustrated, including a bottom segment 791 extending from the bottom chamber surface H0 to a height H5 (5 nanometers above the bottom chamber surface) and a top segment 792 extending from the height H5 to a top segment 790. As shown, an angle A1 is formed between the bottom segment 791 and the top segment 792. In some embodiments, angle A1 is at least 150 degrees. For example, angle A1 may be at least 155 degrees, at least 160 degrees, at least 165 degrees, at least 170 degrees, at least 175 degrees, at least 180 degrees, at least 185 degrees, at least 190 degrees, or at least 195 degrees. Furthermore, angle A1 may be at most 200 degrees, at most 195 degrees, at most 190 degrees, at most 185 degrees, at most 180 degrees, at most 175 degrees, at most 170 degrees, at most 165 degrees, at most 160 degrees, at most 155 degrees, or at most 150 degrees.

[0168] also, Figure 24 The X-section illustrates the load of the metal gate profile from the top to the bottom critical dimensions. For example, the bottom critical dimension D1 (or the lateral width along the horizontal plane) is measured at a height between height H0 and height H5. Furthermore, the top critical dimension D2 (or the lateral width along the horizontal plane) is measured at a height between height H5 and top 790. Top 790 may be located at a height of 12 nm above height H0. The load is equal to the difference between D2 and D1. In some embodiments, the load is 0 to 2.0 nm. For example, the load may be less than 1.8, less than 1.6, less than 1.4, less than 1.2, less than 1, less than 0.8, less than 0.6, less than 0.5, less than 0.4, less than 0.3, or less than 0.2. Furthermore, the load may be at least 0.1, at least 0.2, at least 0.3, at least 0.4, at least 0.5, at least 0.6, at least 0.7, or at least 0.8.

[0169] In some embodiments, each critical dimension D1 and D2 is 14 to 16 nm. For example, the critical dimensions D1 and / or D2 may be at least 14.25, at least 14.5, at least 14.75, at least 15, at least 15.25, at least 15.5, at least 15.75, or at least 16 nm. Furthermore, the critical dimensions D1 and / or D2 may be at most 16, at most 15.75, at most 15.5, at most 15.25, at most 15, at most 14.75, at most 14.5, or at most 14.25.

[0170] In one embodiment, a method includes the steps of: forming a semiconductor nanosheet stack over a substrate; forming a sacrificial gate structure over the semiconductor nanosheet stack; forming a pad adjacent to the sacrificial gate structure; forming a dielectric layer adjacent to the pad; removing the sacrificial gate structure to form a gate cavity; performing an oxidation process to oxidize a portion of the pad adjacent to the gate cavity; and removing a portion of the pad adjacent to the gate cavity.

[0171] In some embodiments of the method, the oxidation process is carried out at a pressure of at least 1 Torr.

[0172] In some embodiments of the method, the oxidation process is a second oxidation process, and the pad portion is a second portion of the pad, and the method further includes the steps of: performing a first oxidation process under a pressure of at least 1 Torr to oxidize a first portion of the pad adjacent to the gate cavity; and removing the first portion of the pad adjacent to the gate cavity before performing the second oxidation process.

[0173] In some embodiments of the method, the step of removing the first portion of the pad includes the step of performing wet chemical etching; and the step of removing the second portion of the pad includes the step of performing dry chemical etching.

[0174] In some embodiments of the method, the liner is a low-k material composed of silicon, oxygen, carbon, and / or nitrogen.

[0175] In some embodiments, the method further includes the following steps: forming an interlayer material over a substrate, wherein a sacrificial gate structure and a pad are formed over the interlayer material; forming a metal gate structure in a gate cavity; planarizing the metal gate structure and a dielectric layer; forming an isolation layer over the metal gate structure, wherein the pad abuts against the isolation layer at a top end and against the interlayer material at a bottom end; the pad has a top lateral thickness at the top end and a bottom lateral thickness at the bottom end; and the difference between the top lateral thickness and the bottom lateral thickness is less than 2 nanometers (nm).

[0176] In some embodiments of the method, the difference is less than 1 nm.

[0177] In some embodiments of the method, the maximum lateral thickness of the liner is 16 nm.

[0178] In some embodiments, the method further includes the steps of: forming a contact etch stop layer on the pad; and forming a hard mask over a dielectric layer adjacent to the contact etch stop layer.

[0179] In some embodiments of the method, the oxidation process is carried out at a pressure of at least 1.5 Torr.

[0180] In some embodiments of the method, the oxidation process is carried out at a pressure of at least 1.65 Torr.

[0181] In another embodiment, a method includes the steps of: forming a chamber extending to a bottom chamber surface and laterally defined by a liner; performing a first oxidation process at a pressure of at least 1 Torr to oxidize a first portion of the liner adjacent to the chamber; removing the first portion of the liner; performing a second oxidation process to oxidize a second portion of the liner adjacent to the chamber; and removing the second portion of the liner.

[0182] In some embodiments of the method, the second oxidation process is carried out at a pressure of at least 1 Torr.

[0183] In some embodiments of the method, after the second portion of the liner is removed, the remaining portion of the liner extends upward from the bottom surface of the chamber and terminates at the top, wherein the remaining portion of the liner has a critical dimensional difference from the bottom surface of the chamber to the top, wherein the thickness difference is less than 2 nanometers (nm).

[0184] In some embodiments of the method, the critical size difference is less than 1 nanometer (nm).

[0185] In some embodiments of the method, the remaining portion of the liner has a maximum lateral critical dimension of 16 nm.

[0186] In some embodiments of the method, after the second portion of the liner is removed, the remaining portion of the liner extends upward from the bottom chamber surface and terminates at the top; the vertical profile of the remaining portion of the liner includes a bottom segment extending from the bottom chamber surface to a height of 5 nanometers above the bottom chamber surface; the vertical profile of the remaining portion of the liner includes a top segment extending from a height of 5 nanometers above the bottom chamber surface to the top; an angle is formed between the bottom segment and the top segment; and the angle is at least 150 degrees.

[0187] In some embodiments of the method, the angle is 160 to 200 degrees.

[0188] In another embodiment, the semiconductor structure includes: a metal gate located above a nanosheet channel stack and having sidewalls extending from a bottom end to a top end; and a low-K pad including silicon, oxygen, carbon, and / or nitrogen surrounding the sidewalls of the metal gate, wherein the vertical profile of the low-K pad includes a bottom segment extending from the bottom end of the metal gate to a height above the bottom end of the metal gate, and a top segment extending from a height above the top end of the metal gate, wherein an angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees.

[0189] In some embodiments of this structure, the height is 5 nanometers from the bottom of the metal gate.

[0190] In some embodiments of this structure, the metal gate has a thickness difference from the bottom to the top, and the thickness difference is less than 2 nanometers (nm).

[0191] In some embodiments of this structure, the thickness difference is less than 1 nanometer (nm).

[0192] In some embodiments of this structure, the maximum lateral thickness of the metal gate is 16 nm.

[0193] In another embodiment, the semiconductor structure includes a substrate, a stack of semiconductor nanosheets, a metal gate structure, a pad, and a dielectric layer. The stack of semiconductor nanosheets is located above the substrate. The metal gate structure is located above the stack of semiconductor nanosheets. The pad is disposed adjacent to the metal gate structure, wherein the vertical profile of the pad includes a bottom segment extending from the bottom end of the metal gate structure to a height above the bottom end of the metal gate structure, and wherein the vertical profile of the pad includes a top segment extending from the height above the metal gate structure to the top end of the metal gate structure, wherein an angle is formed between the bottom segment and the top segment, and the angle is at least 150 degrees. The dielectric layer is disposed adjacent to the pad.

[0194] In some embodiments of this structure, the semiconductor structure further includes an interlayer material layer and an isolation layer. The interlayer material layer is located above the substrate, wherein the metal gate structure and the pad are located above the interlayer material layer. The isolation layer is located above the metal gate structure, wherein the metal gate structure abuts against the isolation layer at its top end and against the interlayer material layer at its bottom end; wherein the metal gate structure has a top lateral thickness at its top end and a bottom lateral thickness at its bottom end; wherein the thickness difference between the top lateral thickness and the bottom lateral thickness is less than 2 nanometers.

[0195] In some embodiments of this structure, the thickness difference is less than 1 nanometer.

[0196] In some embodiments of this structure, the maximum lateral thickness of the metal gate structure is 16 nanometers.

[0197] In some embodiments of this structure, the semiconductor structure further includes a contact etch-stop layer and a hard mask. The contact etch-stop layer is located on the pad. The hard mask is disposed over a dielectric layer adjacent to the contact etch-stop layer.

[0198] In another embodiment, the semiconductor structure includes a metal gate and a pad. The metal gate is located above the nanosheet channel stack. The pad surrounds the sidewalls of the metal gate, wherein the vertical profile of the pad includes a bottom segment extending from the bottom end of the metal gate to a height above the bottom end of the metal gate, and wherein the vertical profile of the pad includes a top segment extending from the height above the metal gate to the top end of the metal gate, wherein the bottom segment and the top segment form an angle of at least 150 degrees.

[0199] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, Include: One substrate; A stack of semiconductor nanosheets is located on top of the substrate; A metal gate structure is located above the semiconductor nanosheet stack; A pad is disposed adjacent to the metal gate structure, wherein a vertical profile of the pad includes a bottom segment extending from a bottom end of the metal gate structure to a height above the bottom end of the metal gate structure, wherein the vertical profile of the pad includes a top segment extending from the height above the metal gate structure to a top end of the metal gate structure, wherein the bottom segment and the top segment form an angle, and the angle is at least 150 degrees; and A dielectric layer is disposed adjacent to the pad.

2. The semiconductor structure as described in claim 1, characterized in that, Further includes: An interlayer material layer is located above the substrate, wherein the metal gate structure and the pad are located above the interlayer material layer; as well as An isolation layer is located above the metal gate structure, wherein the metal gate structure abuts against the isolation layer at its top end and against the interlayer material layer at its bottom end; The metal gate structure has a top lateral thickness at the top end and a bottom lateral thickness at the bottom end; wherein the difference between the top lateral thickness and the bottom lateral thickness is less than 2 nanometers.

3. The semiconductor structure as described in claim 2, characterized in that, The difference is less than 1 nanometer.

4. The semiconductor structure as described in claim 2, characterized in that, The maximum lateral thickness of the metal gate structure is 16 nanometers.

5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, Further includes: A contact etch stop layer is located on the pad; and A hard mask is disposed above the dielectric layer adjacent to the contact etch stop layer.

6. A semiconductor structure, characterized in that, Include: A metal gate is located above a stack of nanosheet channels; and A pad surrounds one sidewall of the metal gate, wherein a vertical profile of the pad includes a bottom segment extending from a bottom end of the metal gate to a height above the bottom end of the metal gate, wherein the vertical profile of the pad includes a top segment extending from the height above the metal gate to a top end of the metal gate, wherein the bottom segment and the top segment form an angle, and the angle is at least 150 degrees.

7. A semiconductor structure, characterized in that, Include: A metal gate is located above a stack of nanosheet channels and has a sidewall extending from a bottom end to a top end; and A low-K pad, composed of silicon, oxygen, carbon and / or nitrogen, surrounds the sidewall of the metal gate, wherein a vertical profile of the low-K pad includes a bottom segment extending from the bottom end of the metal gate to a height above the bottom end of the metal gate, wherein the vertical profile of the low-K pad includes a top segment extending from the height above the metal gate to the top end of the metal gate, wherein the bottom segment and the top segment form an angle, and the angle is at least 150 degrees.

8. The semiconductor structure as described in claim 7, characterized in that, The height is 5 nanometers from the bottom of the metal gate.

9. The semiconductor structure as described in claim 7 or 8, characterized in that, The metal gate has a thickness difference from its bottom to its top, and the thickness difference is less than 2 nanometers.

10. The semiconductor structure as described in claim 9, characterized in that, The thickness difference is less than 1 nanometer, and the metal gate has a maximum lateral thickness of 16 nanometers.

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