A semiconductor structure containing a multi-level recess structure

Abstract

The utility model discloses a semiconductor structure containing multistage pit structure, including substrate, seed crystal layer, buffer layer, epitaxial layer and groove. The epitaxial layer is provided with first, second, third doped layer from top to bottom in turn, and the depth gradient of doped area increases, the groove is opened in the epitaxial layer, the bottom surface is provided with multistage pit and nanometer texture, the corner is arc surface structure, the inner wall covers porous dielectric material lining layer and fills isolation material. Through arc corner and gradient doping optimization electric field distribution, reverse blocking voltage improves 20%~30%; seed crystal layer alternate structure and low roughness buffer layer relieve lattice mismatch stress, and the crack occurrence rate reduces by more than 40%; the forward conduction resistance reduces 20%, and the production cost reduces 15%~20%. It is applicable to high voltage power semiconductor device, and improves the withstand voltage performance and reliability.

Description

Technical Field

[0001] This utility model belongs to the field of semiconductor processing technology, and specifically relates to a semiconductor structure with a multi-level pit structure. Background Technology

[0002] In the manufacturing of high-voltage power semiconductor devices (such as gallium nitride HEMTs and SiC MOSFETs), trench structures are one of the core design features for achieving high-voltage blocking capability and low conduction loss. With the surge in demand for high-voltage (1200V and above) and high-reliability devices in fields such as new energy vehicles, smart grids, and industrial inverters, the limitations of traditional trench technology are becoming increasingly apparent, mainly in the following two aspects: 1. Electric field concentration leads to insufficient withstand voltage performance. Traditional trench designs often employ right-angle or acute-angle corners. Under reverse bias, localized peak electric fields can easily form at the bottom corners of the trench, leading to premature breakdown. For example, in the design of devices with a 1200V withstand voltage rating, the actual breakdown voltage of a right-angle trench structure often only reaches around 900V, far below the theoretical value, severely limiting the application of the device in high-voltage scenarios. Furthermore, the uniform distribution of doping concentration in the epitaxial layer further exacerbates the electric field concentration phenomenon, resulting in increased reverse leakage current and reduced reliability.

[0003] 2. Risk of device failure caused by stress cracks Trench etching processes (such as dry etching) can create steep morphologies and surface damage on the sidewalls. Simultaneously, the difference in thermal expansion coefficients between the trench filling material (such as silicon oxide) and the epitaxial layer material can easily generate thermal stress during temperature cycling. These factors collectively lead to microcracks on the trench sidewalls and bottom. Under high voltage operation, these cracks may propagate into through-hole defects, causing device leakage or even short-circuit failure. While existing technologies use passivation layers (such as SiO2) to cover the trench surface to reduce damage, a single material cannot simultaneously alleviate both mechanical and electric field stresses, and the problem of charge accumulation at the interface between the passivation layer and the epitaxial layer remains unresolved.

[0004] To improve the electric field distribution, some solutions attempt to optimize it by adjusting the trench depth or doping concentration gradient, but these do not address the fundamental problem of electric field concentration at corners from a structural design perspective. Regarding stress cracks, traditional buffer layer designs (such as a single aluminum nitride layer) cannot effectively alleviate the lattice mismatch between the substrate and the epitaxial layer (e.g., the lattice mismatch between the silicon substrate and the gallium nitride epitaxial layer reaches 17%), resulting in a high defect density in the epitaxial layer. Therefore, the applicant hereby applies for this invention. Utility Model Content

[0005] To address the aforementioned problems in the prior art, this invention provides a semiconductor structure with a multi-level pit structure that can improve upon these shortcomings.

[0006] This utility model relates to a semiconductor structure with a multi-level pit structure, including a substrate; A seed layer is disposed on the upper part of the substrate and is composed of alternating layers of silicon-doped aluminum nitride and aluminum nitride, wherein the silicon-doped aluminum nitride layer is formed by ion implantation. A buffer layer is disposed on the upper part of the seed crystal layer, and the material of the buffer layer is the same as the base material of the seed crystal layer (i.e., aluminum nitride). An epitaxial layer is disposed on the upper part of the buffer layer, including a first doped layer, a second doped layer and a third doped layer stacked from top to bottom. The first doped layer is located above the second doped layer and the third doped layer is located below the second doped layer. The depth of the doped region of the first doped layer is smaller than that of the second doped layer, and the depth of the doped region of the second doped layer is smaller than that of the third doped layer. A trench is formed in the epitaxial layer. There is at least one trench, which includes a bottom surface and a side surface. The bottom surface is provided with a multi-level pit structure and a nanotexture is provided on the bottom surface. The nanotexture is a nanopillar or a nanowire. The trench depth gradually decreases from the center of the trench to the edge, forming a gradient pit structure. The bottom surface and the side surface of the trench are covered with a porous dielectric material liner layer and filled with an insulating material layer inside.

[0007] Furthermore, the groove is asymmetrical in shape.

[0008] Furthermore, the surface roughness of the side gradually decreases from bottom to top.

[0009] Furthermore, the total thickness of the seed layer is ≤500nm, and the ratio of silicon-doped aluminum nitride layer to aluminum nitride layer is 1:1 to 2:1.

[0010] Furthermore, the depth of the doped regions of the first doped layer, the second doped layer, and the third doped layer ranges from 10% to 80% of the substrate thickness, and the depth increases linearly from top to bottom.

[0011] Furthermore, the trench is V-shaped, with the bottom corners transitioning to an arc surface, wherein the corner radius is 50~100nm, the porosity of the lining layer is 20%~50%, and the insulating material is a silicon oxide-based composite material.

[0012] Furthermore, an isolation material layer is provided on the bottom surface of the substrate. The thickness of the isolation material layer is 1~5μm and it is electrically connected to the isolation material layer inside the trench. The metal layer is electrically connected to the isolation material layer inside the trench through conductive vias on the substrate surface, and the contact resistance is ≤1E-5Ω·cm².

[0013] Furthermore, the epitaxial layer also includes an aluminum nitride insertion layer, which is located between the second doped layer and the third doped layer, and has a thickness of 50~200nm.

[0014] Furthermore, the thickness of the buffer layer is ≤500nm, and the interlayer roughness between the buffer layer and the seed crystal layer is ≤5nm.

[0015] Furthermore, it also includes a fourth doped layer, which extends downward from the top surface of the first doped layer to a depth of 1 / 2 to 2 / 3 of the depth of the doped region of the first doped layer.

[0016] Furthermore, the substrate is a silicon substrate, and the substrate surface has a nanoscale uneven structure.

[0017] Furthermore, the side surface is provided with a nanotexture, which is a nanopillar structure.

[0018] Technical effects: 1. Optimization of electric field distribution and improvement of withstand voltage performance The trench features curved corners and a multi-level recessed design: Traditional right-angle corners are optimized into curved transitions with radii of 50-100 nm. A multi-level recessed structure with gradually varying depths is incorporated into the bottom surface of the trench, along with nanotextures (nanopillars / nanowires), reducing the local electric field intensity by over 40%. Combined with a linearly increasing doping depth from top to bottom in the epitaxial layer (50 μm for the first doped layer → 100 μm for the second doped layer → 200 μm for the third doped layer), the reverse blocking voltage is increased from 900 V in the traditional structure to over 1200 V, meeting the requirements of high-voltage power devices.

[0019] Synergistic effect of porous dielectric liner: The trench surface is covered with a porous silicon nitride liner with a porosity of 20%~50%. The gradient change of dielectric constant (3.5→4.2) alleviates the accumulation of interface charge and further reduces the leakage current to below 1E-7A / cm².

[0020] 2. Stress buffering and reliability enhancement Synergistic design of seed layer and buffer layer: The seed layer (total thickness ≤500nm) consists of alternating layers of silicon-doped aluminum nitride and aluminum nitride, combined with a buffer layer with a roughness ≤5nm, which effectively alleviates 17% lattice mismatch stress between the silicon substrate and the epitaxial layer, and reduces the crack incidence rate by more than 40%.

[0021] Asymmetric trenches and gradient roughness: The surface roughness of the trench side gradually decreases from the bottom (Ra=5nm) to the top (Ra=1nm). Combined with the V-shaped gradient depth structure, thermal stress concentration is reduced, which improves the reliability of the device by 50% in temperature cycling tests from -55℃ to 150℃.

[0022] 3. Balancing electrical performance with process compatibility Doping depth gradient control: The doping depth gradient distribution (10%~80% of substrate thickness) is achieved through ion implantation process. While improving the reverse breakdown voltage, the forward conduction resistance is reduced by 20% (from 0.625Ω·cm² to 0.5Ω·cm²), achieving a balance between "high voltage and low resistance".

[0023] Compatibility with conventional processes: All structures are realized through mature semiconductor processes such as ion implantation, PECVD, and ALD, without the need for special equipment, reducing production costs by 15% to 20% and increasing yield to over 95%.

[0024] 4. Additional advantages brought about by structural innovation Aluminum nitride insertion layer and fourth doped layer: A 100nm aluminum nitride insertion layer is added between the second and third doped layers to put the epitaxial layer in a compressive strain state and eliminate through cracks; the fourth doped layer (extending depth 0.6μm) further optimizes the surface electric field distribution and reduces edge effects.

[0025] Synergistic effect of metal layer and trench filling: A 1-5 μm metal layer on the bottom surface of the substrate and the isolation material (SiO2) in the trench form a low contact resistance path, improving the switching speed of the device by 15%.

[0026] In summary, this structure significantly improves the withstand voltage, reliability, and electrical performance of high-voltage power semiconductor devices through multi-dimensional innovations in "electric field optimization, stress buffering, and process compatibility," making it suitable for high-voltage scenarios such as new energy vehicles and smart grids. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of this utility model.

[0028] Figure 2 This is a diagram showing the relationship between the second doped layer, the aluminum nitride insertion layer, and the third doped layer.

[0029] Figure 3 This is a schematic diagram of the channel structure.

[0030] Figure 4 for Figure 3 Schematic diagram of the structure at point A in the middle.

[0031] Figure 5 for Figure 3 Schematic diagram of the structure at point B.

[0032] The diagram shows: 1. Substrate, 2. Seed layer, 3. Buffer layer, 4. Epitaxial layer, 41. First doped layer, 42. Second doped layer, 43. Third doped layer, 44. Fourth doped layer, 5. Isolation material layer, 6. Channel, 61. Liner layer, 62. Isolation material, 7. Aluminum nitride insertion layer. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the scope of the present utility model.

[0034] like Figure 1 As shown in Embodiment 1, this utility model relates to a semiconductor structure with a multi-level pit structure, including a substrate 1; a seed layer 2, a buffer layer 2, an epitaxial layer 4, and a trench 6.

[0035] Substrate 1: The substrate is the fundamental supporting component of this semiconductor structure, and its material selection must comprehensively consider factors such as lattice mismatch, coefficient of thermal expansion, and cost. In this embodiment, substrate 101 is made of n-type silicon with a thickness of 500 μm. To enhance the electrical performance of substrate 101, a titanium-nickel-gold metal layer with a total thickness of 3 μm is sputtered onto its bottom surface. Furthermore, the surface of substrate 101 has a nanoscale uneven structure with a height of 10 nm and a spacing of 50 nm. This structure helps improve the adhesion between substrate 101 and subsequent layers, as well as its electrical performance.

[0036] Seed layer 2: Located on the upper surface of the substrate, the seed layer's main function is to form nucleation sites on the substrate surface, which is beneficial for the subsequent growth of the epitaxial layer. It also effectively prevents silicon from diffusing from the substrate into the epitaxial layer, reducing the reaction between silicon and the epitaxial layer material, thereby obtaining a high-quality epitaxial layer. Seed layer 102 is composed of alternating layers of silicon-doped aluminum nitride and aluminum nitride, with the silicon-doped aluminum nitride layers formed by ion implantation. In this embodiment, the seed layer comprises a four-layer structure, where the silicon-doped aluminum nitride layer is 50 nm thick with a silicon doping concentration of 1E18; the aluminum nitride layer is also 50 nm thick, for a total thickness of 200 nm. This alternating layer structure can better buffer the lattice mismatch stress between the substrate and the epitaxial layer, improving device reliability.

[0037] Buffer layer 3: The buffer layer is disposed above the seed layer. Its main function is to effectively alleviate lattice mismatch and thermal mismatch between the epitaxial layer and the substrate, reduce strain caused by stress in the epitaxial layer, and reduce the occurrence of dislocations and defects. The material of the buffer layer 103 is the same as the base material of the seed layer, namely aluminum nitride. In this embodiment, the thickness of the buffer layer 103 is 300 nm, which is prepared by atomic layer deposition (ALD) process, and the interface roughness is 3 nm. The ALD process parameters are: temperature 300°C, pressure 1 Torr, and deposition rate 0.1 nm / cycle. This low-roughness buffer layer can further improve the quality of the epitaxial layer and reduce the generation of cracks.

[0038] Epitaxial Layer: The epitaxial layer, located on top of the buffer, is the core component of this semiconductor structure and is used to implement the main electrical functions of the device. The epitaxial layer comprises a first doped layer 41, a second doped layer 42, and a third doped layer 43, stacked sequentially from top to bottom. The first doped layer is located above the second doped layer, and the third doped layer 43 is located below the second doped layer. The first doped layer has a doping depth of 50 μm, is implanted with magnesium ions at a doping concentration of 1E17 / cm³, and the ion implantation parameters are: implantation energy 100 keV, dose 1E14 / cm². The second doped layer has a doping depth of 100 μm and a doping concentration of 5E16 / cm³. The third doped layer has a doping depth of 200 μm and a doping concentration of 1E16 / cm³. This gradient distribution of doping depth optimizes the electric field distribution, improves the reverse blocking voltage of the device, and reduces the forward conduction resistance. The doping depth gradient is achieved by using an ion implantation energy gradient (100keV→200keV→300keV), with the doping concentration decreasing linearly from the first to the third doped layer in the order 1E17→5E16→1E16 cm⁻³.

[0039] In addition, a fourth doped layer and an aluminum nitride insertion layer 7 are also provided in the epitaxial layer. The fourth doped layer 1044 extends downward from the top surface of the first doped layer, with an extension depth of 1 / 2 to 2 / 3 of the depth of the doped region of the first doped layer, i.e., an extension depth of 0.6 μm. This design can further optimize the electric field distribution and reduce electric field concentration. The aluminum nitride insertion layer is located between the second and third doped layers, with a thickness of 100 nm. The main function of the insertion layer is to place the subsequently grown epitaxial layer in a compressive strain state, reduce stress and dislocations in the epitaxial layer, and thus eliminate cracks in the epitaxial layer, resulting in a high-quality, crack-free epitaxial layer.

[0040] Trench 6: Formed in the epitaxial layer, such as Figure 3 As shown, at least one groove is provided, the groove includes a bottom surface 62 and a side surface 61, the bottom surface is provided with a multi-level pit structure, such as... Figure 5 As shown, a nanotexture 65 is formed on the bottom surface. The nanotexture is either nanopillars or nanowires. The trench depth gradually decreases from the center to the edge, forming a gradient pit structure. Both the bottom and sides of the trench are covered with a porous dielectric material liner layer 64, with a porosity of 20%–50% and a thickness of 50 nm. The liner layer is made of porous silicon nitride and prepared using a PECVD deposition process. The trench 106 is filled with an insulating material, SiO2, deposited using a CVD deposition process. The deposition gases are SiH4 and O2, and the deposition temperature is 400°C. This insulating material effectively isolates different areas, preventing electrical interference. Furthermore, the filling process does not generate internal stress due to volume expansion, further improving the reliability of the device.

[0041] It should be noted that the "multi-level pit structure" of this design is preferably 2-4 levels, with the depths from the center of the groove to the edge being 200μm, 150μm, and 100μm respectively (taking 3 levels as an example), and the pits of each level are connected by a curved surface transition.

[0042] Furthermore, the trench is asymmetrical in shape. The left side wall of the asymmetrical trench has an inclination angle of 60°, the right side wall has an inclination angle of 45°, and the depth increases by 10% to 20% from left to right. It can also be designed as concentric circular depressions, or depressions of different sizes at different depths. This design can further optimize the electric field distribution and reduce electric field concentration.

[0043] like Figure 4 As shown, the surface roughness of the side surface 61 gradually decreases from the bottom to the top. The side surface is provided with a nanotexture, which is a nanopillar structure. The nanopillars of the nanotexture have a diameter of 50-100 nm, a height of 200-300 nm, a spacing of 100-200 nm, and are arranged periodically.

[0044] As a technological improvement, the seed layer has a layer ratio of 2:1, namely 6 silicon-doped aluminum nitride layers and 3 aluminum nitride layers, with a total thickness of 450 nm. This structure can further optimize the performance of the seed layer and improve its ability to buffer lattice mismatch stress between the substrate and the epitaxial layer.

[0045] As a technological improvement, the trenches can be designed as concentric circles, or with different sizes at different depths. This design can further optimize the electric field distribution and reduce electric field concentration. The trench lining layer is an insulating material layer, specifically silicon oxynitride with a porosity of 40%. The insulating material 1062 is SiON. This material combination provides better electrical performance and stability, making it suitable for various applications.

[0046] As a technological improvement, substrate 1 is made of silicon carbide, which has better thermal conductivity and electrical properties and is suitable for special applications such as high temperature and high frequency.

[0047] The epitaxial layer 4 does not have an aluminum nitride insertion layer 105. This structure simplifies the manufacturing process, reduces production costs, and can still meet performance requirements in certain application scenarios.

[0048] Compared to traditional right-angle corner structures, the semiconductor structure described in the above embodiments exhibits a 30% increase in reverse blocking voltage (from 900V to 1200V), a 20% reduction in forward conduction resistance (from 0.625Ω·cm² to 0.5Ω·cm²), a 50% reduction in leakage current (reaching 1E-7A / cm²), and a 40% reduction in crack incidence. These performance improvements demonstrate that the semiconductor structure of this invention possesses significant advantages in electric field optimization, stress buffering, precise doping control, and process compatibility. It effectively addresses the problems existing in the prior art, thereby improving the overall performance and reliability of semiconductor devices.

Claims

1. A semiconductor structure containing a multi-level pit structure, characterized in that: Including substrate; A seed layer is disposed on the upper part of the substrate and is composed of alternating layers of silicon-doped aluminum nitride and aluminum nitride, wherein the silicon-doped aluminum nitride layer is formed by ion implantation. A buffer layer is disposed on the upper part of the seed crystal layer and is made of the same base material as the seed crystal layer. An epitaxial layer is disposed on the upper part of the buffer layer, including a first doped layer, a second doped layer and a third doped layer stacked from top to bottom. The first doped layer is located above the second doped layer and the third doped layer is located below the second doped layer. The depth of the doped region of the first doped layer is smaller than that of the second doped layer, and the depth of the doped region of the second doped layer is smaller than that of the third doped layer. A trench is formed in the epitaxial layer. There is at least one trench, which includes a bottom surface and a side surface. The bottom surface is provided with a multi-level pit structure and a nanotexture is provided on the bottom surface. The nanotexture is a nanopillar or a nanowire. The trench depth gradually decreases from the center of the trench to the edge, forming a gradient pit structure. The bottom surface and the side surface of the trench are covered with a porous dielectric material liner layer and filled with an insulating material layer inside.

2. The semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: The groove is asymmetrical in shape.

3. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: The surface roughness of the side gradually decreases from bottom to top.

4. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: An isolation material layer is disposed on the bottom surface of the substrate. The thickness of the isolation material layer is 1~5μm, and it is electrically connected to the isolation material layer inside the trench.

5. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: The epitaxial layer also includes an aluminum nitride insertion layer, which is located between the second doped layer and the third doped layer and has a thickness of 50~200nm.

6. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: The thickness of the buffer layer is ≤500nm, and the interlayer roughness between the buffer layer and the seed crystal layer is ≤5nm.

7. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: It also includes a fourth doped layer, which extends downward from the top of the first doped layer to a depth of 1 / 2 to 2 / 3 of the depth of the doped region of the first doped layer.

8. A semiconductor structure with a multi-level pit structure according to claim 1, characterized in that: The substrate is a silicon substrate, and the substrate surface has a nanoscale uneven structure.

9. A semiconductor structure with a multi-level pit structure according to claim 3, characterized in that: The side surface is provided with a nanotexture, which is a nanopillar structure.

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