Semiconductor device

Abstract

A semiconductor device includes a fin base protruding from a substrate, two isolation layers disposed above the substrate, two source / drain components disposed above the two isolation layers, an isolation structure disposed above the fin base and connecting the two isolation layers, a stack of multiple semiconductor layers disposed above the isolation structure, wherein the stack of semiconductor layers includes a bottom semiconductor layer and multiple top semiconductor layers disposed above the bottom semiconductor layer, wherein the bottom semiconductor layer connects the two isolation layers, and wherein the top semiconductor layers connect the two source / drain components, an isolation component disposed adjacent to the fin base and the isolation structure, wherein a top surface of the isolation component is above a top surface of the isolation structure, and a metal gate structure wrapping around the top semiconductor layers.

Description

Technical Field

[0001] This utility model relates to semiconductor technology, and more particularly to semiconductor devices. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advancements in IC materials and design have led to generation after generation of ICs, each with smaller and more complex circuits than the previous one. During the evolution of ICs, functional density (i.e., the number of interconnects per unit wafer area) typically increases while geometric dimensions (i.e., the smallest components (or lines) that can be manufactured using a process) decrease. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs. However, such size reduction also increases the complexity of the manufacturing process and the production of ICs.

[0003] For example, as integrated circuit (IC) technology has evolved to smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). Multi-gate devices typically refer to devices with a gate structure, or a portion of the gate structure, positioned above more than one side of the channel region. Gate-all-around (GAA) transistors are examples of multi-gate devices and have become popular and promising candidates for high-performance and low-leakage applications. A GAA transistor has a gate structure that can extend partially or completely around the channel region to provide access to the channel region on both sides or more. Because its gate structure surrounds the channel region, the fully wrapped gate (GAA) transistor can also be called a surrounding gate transistor (SGT) or a multi-bridge-channel (MBC) transistor.

[0004] However, despite its many desirable properties, the fabrication of multi-gate devices remains challenging due to the continuous miniaturization of semiconductor integrated circuits (ICs). Therefore, existing technologies have not yet proven to be completely satisfactory in all aspects. Utility Model Content

[0005] This invention provides a semiconductor device, comprising: a fin substrate protruding from a substrate; two isolation layers disposed above the substrate; two source / drain components disposed above the two isolation layers; an isolation structure disposed above the fin substrate and connecting the two isolation layers; a stack of semiconductor layers disposed above the isolation structure, wherein the stack of semiconductor layers includes a bottom semiconductor layer and a top semiconductor layer disposed above the bottom semiconductor layer, wherein the bottom semiconductor layer connects the two isolation layers, and wherein the top semiconductor layer connects the two source / drain components; an isolation component disposed adjacent to the fin substrate and the isolation structure, wherein the top surface of the isolation component is located above the top surface of the isolation structure; and a metal gate structure wrapping around the top semiconductor layer.

[0006] In some embodiments, the two isolation layers comprise dielectric material, epitaxial material, or a combination thereof.

[0007] In some embodiments, the top surface of the isolation component is approximately 10 nm to approximately 60 nm above the bottom surface of the two isolation layers.

[0008] In some embodiments, the isolation structure includes a dielectric layer and two inner spacers that enclose the dielectric layer, wherein each of the two inner spacers is disposed between the dielectric layer and one of the two isolation layers.

[0009] In some embodiments, the two inner spacer components connect the two isolation layers.

[0010] In some embodiments, the top surfaces of the two inner spacers are higher than the top surfaces of the two isolation layers.

[0011] In some embodiments, the metal gate structure includes an inner portion sandwiched between the two inner spacer members.

[0012] In some embodiments, the bottom surface of the metal gate structure is lower than the top surface of the two source / drain components.

[0013] In some embodiments, the top surface of the isolation component is approximately 10 nm to approximately 70 nm above the bottom surface of the two isolation layers.

[0014] In some embodiments, the bottom surface of the isolation component is higher than the bottom surfaces of the two isolation layers. Attached Figure Description

[0015] The various embodiments of this utility model can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily enlarged or reduced.

[0016] Figure 1 and Figure 2 A flowchart illustrating one or more embodiments of the present invention for forming a semiconductor structure is shown.

[0017] Figure 3 , 4A 4B, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18A, 18B, 19, 20A, 20B, 21A, 21B, 21C and Figure 21D Examples of one or more embodiments of the present invention are illustrated. Figure 1 and Figure 2 Partial cross-sectional views of exemplary semiconductor structures during various manufacturing stages in the method.

[0018] Figure 22A , 22B 22C and 22D illustrate one or more embodiments of the present invention. Figure 1 and Figure 2 Partial cross-sectional views of alternative semiconductor structures during various manufacturing stages in the method.

[0019] Figure 23 , 24 Examples 25, 26, and 27 illustrate one or more embodiments of the present invention. Figure 1 and Figure 2 Partial cross-sectional views of alternative semiconductor structures during various manufacturing stages in the method.

[0020] Figure 28 Examples of one or more embodiments of the present invention are illustrated. Figure 1 and Figure 2 Partial cross-sectional views of alternative semiconductor structures during various manufacturing stages in the method.

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 100: Method

[0023] 102: Block

[0024] 104: Block

[0025] 106: Block

[0026] 108: Block

[0027] 110: Block

[0028] 112: Block

[0029] 114: Block

[0030] 116: Block

[0031] 118: Block

[0032] 120: Block

[0033] 122: Block

[0034] 124: Block

[0035] 126: Block

[0036] 128: Block

[0037] 130: Block

[0038] 132: Block

[0039] 134: Block

[0040] 136: Block

[0041] 138: Block

[0042] 200: Structure

[0043] 202: Substrate

[0044] 204: Stacking

[0045] 204B: Bottom stack

[0046] 204T: Top Stack

[0047] 206: Sacrificial Layer

[0048] 208: Channel Layer

[0049] 208B: Boundary Semiconductor Layer

[0050] 212: Fin-like structure

[0051] 212-1: Section

[0052] 212-2: Section

[0053] 212B: Fin substrate structure

[0054] 212C: Passage Area

[0055] 212SD: Source / Drain Region

[0056] 214: Isolation component

[0057] 215: Protective layer

[0058] 216: Virtual Dielectric Layer

[0059] 218: Dummy Electrode Layer

[0060] 220: Dummy Gate Stack

[0061] 222: Hard masking layer at the top of the gate

[0062] 223: Silicon oxide layer

[0063] 224: Silicon nitride layer

[0064] 226: Gate spacer layer

[0065] 228: Source / Drain Trench

[0066] 229: Space

[0067] 230: Virtual Layer

[0068] 232: Inner spacer groove

[0069] 234: Inner spacer component

[0070] 236: Isolation layer

[0071] 238: Source / Drain Components

[0072] 240: Contact etch stop layer (CESL) 242: Interlayer dielectric (ILD) layer

[0073] 244: Dielectric components

[0074] 250: Dielectric material

[0075] 252: Dielectric materials

[0076] 254: Gate Trench

[0077] 256: Gate structure

[0078] 256a: Internal part

[0079] 258: Isolation Structure

[0080] 300: Structure

[0081] 400: Structure

[0082] 500: Structure

[0083] 2080: Channel Components

[0084] 2080B: Boundary Semiconductor Component

[0085] T0: Thickness

[0086] T1: Thickness

[0087] T2: Thickness

[0088] T3: Thickness

[0089] D1: Distance D1': Distance D2: Distance D2': Distance D3: Distance A-A': Section B-B': Section C-C': Section

[0090] X: X direction

[0091] Y: Y direction

[0092] Z: Z direction Detailed Implementation

[0093] Numerous embodiments or examples are disclosed below for different components of this utility model. Specific examples of elements and configurations are described below to simplify this utility model. Of course, these are merely examples and are not intended to be limiting. For instance, if the following description refers to a first element forming above a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact.

[0094] Furthermore, reference values ​​and / or letters may be repeated in various examples of the embodiments of this utility model. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed. Additionally, in the following description of this utility model, references to a first element being formed on, connected to, and / or coupled to a second element may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Moreover, spatially relative terms such as “lower,” “upper,” “horizontal,” “vertical,” “above,” “under,” “below,” “top,” “bottom,” and similar terms and their derivatives (e.g., “horizontally,” “downward,” “upward,” etc.) may be used to facilitate the description of the relationship between one or more components or components in the drawings. Spatially relative terms are used to include different orientations of the device in use or operation. Additionally, when using terms such as "approximately" or "around" to describe a number or a range of numbers, the meaning of the term includes the number being described and any numbers that differ from the described number by no more than ±10%, unless otherwise stated. For example, the term "approximately 5 nanometers" includes a size range from 4.5 nanometers to 5.5 nanometers.

[0095] As described above, multi-bridge channel (MBC) transistors can also be referred to as gate-all-around (SGT) transistors, gate-all-around (GAA) transistors, nanosheet transistors, or nanowire transistors. They can be n-type or p-type. MBC devices can have channel regions disposed in nanowire channel components, strip channel components, nanosheet channel components, nanostructured channel components, bridge-shaped channel components, and / or other suitable channel configurations. MBC transistors typically include a stack of channel layers in a multilayer structure disposed above a semiconductor substrate, epitaxial source / drain components formed above or within active regions (e.g., fins), and a metal gate structure interleaved with and inserted between the source / drain components. In some examples, leakage current may occur between the epitaxial source / drain components and / or between the epitaxial source / drain components and the semiconductor substrate, which may also be doped to form wells therein. Furthermore, the bottom channel layer in the multilayer structure may generate leakage current and potentially degrade device performance. While existing technologies are generally sufficient to achieve their intended purpose, they are not entirely satisfactory in all respects.

[0096] This invention provides a method for forming a semiconductor device such as a gate-wound (GAA) transistor. In an example process, a fin structure is formed over a substrate, the fin structure including a fin substrate structure and a stack of channel layers and sacrificial layers. Isolation members are formed on one side of the fin substrate structure and the bottom of the stack. The top surface of the isolation members is located above the top surface of the bottommost sacrificial layer. After forming a dummy gate stack over the channel region of the fin structure, gate spacers are formed over the dummy gate stack. The source / drain regions of the fin structure are recessed. The sacrificial layer is selectively removed to release the channel layer as a channel member. A dummy layer is deposited over each channel member. The dummy layer is then selectively and partially etched to form inner spacer trenches between the multiple channel members. Inner spacer members are formed in the inner spacer trenches. Isolation layers and epitaxial source / drain members are formed in the source / drain trenches. The isolation layer may include a dielectric material and / or an undoped epitaxial material. After selectively removing the dummy gate stack, the top of the dummy layer is selectively removed to release the top of the channel member. The gate structure is then formed to wrap around each top of the channel component. The remaining portion of the dummy layer and the inner spacers on its sides together form an isolation structure. By having an isolation structure and an isolation layer, current leakage from the channel layer and epitaxial source / drain components can be mitigated, latch-up problems between adjacent epitaxial source / drain components can be prevented, and trigger voltage faults can be avoided, thereby improving the overall performance of the semiconductor device.

[0097] The various aspects of this utility model will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor structure according to an embodiment of the present invention. Figure 2 This is a flowchart illustrating routes A and B. Routes A and B are as follows: Figure 1 This is a part of method 100. Method 100 is merely illustrative and is not intended to limit the present invention to what is expressly shown in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, deleted, or moved for additional embodiments of the method. For brevity, not all steps are described in detail herein. The following is in conjunction with... Figures 3-28 Description method 100, Figures 3-28 It is based on Figure 1 and Figure 2 Partial cross-sectional views of structures 200 and alternative structures 300, 400, and 500 at different manufacturing stages of embodiments of method 100. Because structures 200, 300, 400, and 500 will be manufactured as semiconductor structures or semiconductor devices, structures 200, 300, 400, and 500 are referred to herein as semiconductor structures or semiconductor devices 200, 300, 400, and 500, as the context requires. To avoid ambiguity, Figures 3-28 The X, Y, and Z directions are perpendicular to each other and are used consistently throughout this utility model. Throughout this utility model, unless otherwise stated, similar element symbols denote similar parts. That is, in a description of a method or drawing, the material properties of each element symbol and its corresponding counterpart should also apply to elements with the same element symbol in descriptions of different methods or drawings.

[0098] Furthermore, the semiconductor structures disclosed herein may include various other devices and components, such as other types of devices including additional transistors, bipolar junction transistors, resistors, capacitors, inductors, diodes, fuses, static random-access memory (SRAM), and / or other logic circuits, but these are simplified for a better understanding of the novel concept of this invention. In some embodiments, exemplary devices include multiple interconnectable semiconductor devices (e.g., transistors), including n-type fully wound gate (GAA) transistors, p-type fully wound gate (GAA) transistors, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), etc.

[0099] refer to Figure 1 and Figure 3 Method 100 includes block 102, in which structure 200 is provided. For example... Figure 3 As shown, structure 200 includes a substrate 202 and a stack 204 of alternating semiconductor layers formed over the substrate 202. In some embodiments, the substrate 202 may be a semiconductor substrate, such as a silicon (Si) substrate. As is known in the art, the substrate 202 may include various doping configurations depending on design requirements. In embodiments where the semiconductor device is p-type, an n-type doping distribution (i.e., an n-type well or n-well) may be formed on the substrate 202. In some embodiments, the n-type dopant used to form the n-type well may include phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the semiconductor device is n-type, a p-type doping distribution (i.e., a p-type well or p-well) may be formed on the substrate 202. In some embodiments, the p-type dopant used to form the p-type well may include boron (B) or gallium (Ga). Suitable doping steps may include ion implantation and / or diffusion processes of the dopant. The substrate 202 may also include other semiconductors, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), germanium tin (GeSn), or diamond. Alternatively, the substrate 202 may include compound semiconductors and / or alloy semiconductors. In addition, the substrate 202 may optionally include an epitaxial layer that can be strained to enhance performance, and may include a silicon-on-insulator (SOI) or germanium-on-insulator (GeOI) structure, and / or may have other suitable reinforcing components.

[0100] In some embodiments, the stack 204 above the substrate 202 includes a channel layer 208 having a first semiconductor composition and interspersed with sacrificial layers 206 having a second semiconductor composition. Alternatively, the sacrificial layers 206 and channel layers 208 may be interspersed. The first and second semiconductor compositions may be different. In some embodiments, the sacrificial layer 206 comprises silicon-germanium (SiGe) or germanium-tin (GeSn), while the channel layer 208 comprises silicon (Si). Note that, as Figure 3 As shown, four sacrificial layers 206 and four channel layers 208 are alternately configured. This is for illustrative purposes only and is not intended to limit the scope beyond that specifically described in the claims. It is understood that any number of epitaxial layers can be formed in the stack 204. The number of layers depends on the desired number of channel components and the desired number of isolation structures (described below) of the semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10. In some embodiments, the stack 204 includes a top stack 204T and a bottom stack 204B located below the top stack 204T. The top stack 204T and the bottom stack 204B each include at least one channel layer 208. In some embodiments, the bottom stack 204B includes one to three channel layers. The sacrificial layers 206 in the bottom stack 204B may each have a thickness T0 of about 6 nm to about 60 nm.

[0101] The sacrificial layer 206 and channel layer 208 in stack 204 can be deposited using molecular beam epitaxy (MBE), vapor phase deposition (VPE), and / or other suitable epitaxial growth processes. As described above, in at least some examples, the sacrificial layer 206 comprises an epitaxially grown silicon-germanium (SiGe) layer and the channel layer 208 comprises an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and channel layer 208 are substantially dopant-free (i.e., having a dopant content of about 0 atoms / cm²). 3 To approximately 1x10 17 atoms / cm 3 The external (extrinsic) doping concentration, wherein, for example, no intentional doping is performed during the epitaxial growth process of stack 204.

[0102] refer to Figure 1 and Figures 4A-4BMethod 100 includes a block 104 in which a fin-like structure 212 (also referred to as an active region 212 or fin-like structure 212) is formed from a stack 204 and a substrate 202. To pattern the stack 204, a hard mask layer may be deposited over the stack 204 to form an etch mask. The hard mask layer may be a single layer or multiple layers. For example, the hard mask layer may include a pad oxide layer and a pad nitride layer disposed above the pad oxide layer. The fin-like structure 212 may be patterned from the stack 204 and the substrate 202 using lithography and etching processes. Lithography processes may include photoresist coating (e.g., spin-on coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, etching processes may include dry etching (e.g., reactive ion etching (RIE)), wet etching, and / or other etching methods. Figures 4A-4B As shown, the etching process at block 104 forms trenches extending vertically through stack 204 and a portion of substrate 202. The trenches define fin structures 212. In some embodiments, dual-patterning or multi-patterning processes can be used to define fin structures having, for example, a smaller pitch than that achievable using a single, direct optical lithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned material layer using a self-aligning process. The material layer is then removed, and the remaining spacers or mandrels can then be used to pattern the fin structure 212 by etching a portion of stack 204 and substrate 202. Figures 4A-4B As shown, the fin structure 212, comprising the sacrificial layer 206 and the channel layer 208, extends vertically along the Z direction and longitudinally along the X direction. Figures 4A-4B As shown, the fin structure 212 includes a fin substrate structure 212B patterned from the substrate 202. A patterned stack 204 including a sacrificial layer 206 and a channel layer 208 is disposed directly above the fin substrate structure 212B.

[0103] Still referencing Figure 1 and Figures 4A-4B Method 100 includes block 106, wherein adjacent fin structures 212 form an isolation member 214. Figure 4AIn some embodiments shown, isolation member 214 is disposed on the sidewalls of fin substrate structure 212B and a portion of bottom stack 204B. In some embodiments, isolation member 214 may be formed in trenches to isolate fin structure 212 from adjacent fin structure 212. In the disclosed embodiments, isolation member 214 may cover the sidewalls of sacrificial layer 206 in bottom stack 204B. Isolation member 214 may also be referred to as shallow trench isolation (STI) member 214. For example, in some embodiments, a dielectric layer is first deposited over substrate 202 and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer may include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials. In various examples, the dielectric layer can be deposited using chemical vapor deposition (CVD), subatmospheric CVD (SACVD), flowable CVD (FCVD), spin coating, and / or other suitable processes. The deposited dielectric material is then thinned and planarized, for example, using chemical mechanical polishing (CMP). The planarized dielectric layer is further recessed or pulled back using dry etching, wet etching, and / or combinations thereof to form... Figure 4A The shallow trench isolation (STI) component 214 is shown. After the recess, the top stack 204T of the fin structure 212 rises above the shallow trench isolation (STI) component 214, while the fin base structure 212B and the bottom stack 204B are embedded or buried in the isolation component 214.

[0104] like Figure 4AAs shown, a protective layer 215 is formed above the isolation component 214. The protective layer 215 may be a single layer or multiple layers. In some embodiments, the protective layer 215 includes silicon nitride (SiN), silicon carbonitride oxynitride (SiCON), silicon oxide, silicon carbonitride (SiCN), silicon oxynitride (SiON), silicon carbonitride oxynitride (SiCO), a high-k dielectric material, or a combination thereof. High-k dielectric materials include hafnium oxide, titanium oxide (TiO2), zirconium hafnium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), and hafnium titanium oxide (HfTiO). In some embodiments, the protective layer 215 includes silicon nitride, silicon carbonitride, aluminum oxide, or combinations thereof.

[0105] A combination of processes can be used to deposit a protective layer 215 on the top surface of the insulating component 214. The protective layer material can be deposited over the structure 200 using physical vapor deposition (e.g., sputtering) or chemical vapor deposition. Because the top-facing surface is closer to the line of sight, the deposited protective layer material is thicker on the top-facing surface and thinner along the sidewalls of the fin structure 212. A bottom antireflective coating (BARC) layer (not shown) can be deposited over the protective layer material using CVD, spin coating, or other suitable processes. The BARC layer may include silicon oxynitride (SiON), silicon oxycarbide, polymers, or other suitable materials. The BARC layer can then be etched back to expose the top of the protective layer material. The protective layer material not covered by the BARC layer is then trimmed using oxygen-containing gas, fluorine-containing gas, chlorine-containing gas, bromine-containing gas, iodine-containing gas, other suitable gases and / or plasma, and / or combinations thereof (e.g., by dry etching). The BARC layer is then removed using an ashing process or a dry etching process. The protective layer material above the sidewalls of the fin structure 212 is then removed using an isotropic process (such as a wet etching process). As described above, because the protective layer material along the sidewalls of the fin structure 212 is thinner than the corresponding portion above the isolation member 214, the protective layer material along the sidewalls of the fin structure 212 can be completely removed, while a portion of the protective layer material above the isolation member 214 remains as the protective layer 215. In some embodiments, the thickness of the protective layer 215 is between about 1 nm and about 10 nm.

[0106] exist Figure 4A In the illustrated embodiment, the topmost channel layer 208 (also referred to as the border semiconductor layer 208B) in the bottom stack 204B has a thickness T1. The channel layer 208 in the top stack 204 may have a thickness T2. T1 may be equal to or greater than T2. ​​In some embodiments, T1 may be from about 4 nm to about 10 nm. The top surface of the border semiconductor layer 208B may be coplanar with or higher than the top surface of the protective layer 215. The bottom surface of the border semiconductor layer 208B may be lower than the top surface of the protective layer 215.

[0107] exist Figure 4B In some other embodiments shown, the formation of the isolation member 214 is related to... Figure 4A The embodiments described herein are similar, and are the same as those described herein. Figure 4A The differences between the embodiments described herein are as follows. Figure 4BIn this embodiment, the protective layer 215 is omitted. In this embodiment, the boundary semiconductor layer 208B may have a thickness T3 greater than T1. T3 may be approximately 5 nm to approximately 30 nm. The top surface of the boundary semiconductor layer 208B may be coplanar with or higher than the top surface of the isolation member 214. The bottom surface of the boundary semiconductor layer 208B may be lower than the top surface of the isolation member 214.

[0108] The following processes of method 100 can be obtained from about Figure 4A or Figure 4B The embodiments continue. In some of the following figures (e.g., Figure 5 , Figure 21D and Figure 22D It should be understood that it is possible to... Figure 4B The protective layer 215 is omitted in the middle.

[0109] refer to Figure 1 , Figure 5 and Figure 6 Method 100 includes block 108, wherein a dummy gate stack 220 is formed over channel region 212C of fin structure 212. Figure 6 Structure 200 is shown along Figure 5 A partial cross-sectional view taken along line A-A'. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the dummy gate stack 220 (e.g.) Figure 5 and Figure 6 (As shown) This structure is used as a placeholder to undergo various processes and will be removed and replaced by a functional gate. Other processes and configurations are also possible. Figure 6 In some embodiments shown, a dummy gate stack 220 is formed above a fin structure 212, and the fin structure 212 can be divided into a channel region 212C located below the dummy gate stack 220 and a source / drain region 212SD not located below the dummy gate stack 220. The channel region 212C is adjacent to the source / drain region 212SD. Figure 6 As shown, the channel region 212C is disposed between the two source / drain regions 212SD along the X direction.

[0110] The formation steps of the dummy gate stack 220 may include a deposition step of layers in the dummy gate stack 220 and a patterning step of these layers. (See reference) Figure 5A dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be blanketly deposited over structure 200. In some embodiments, the dummy dielectric layer 216 can be formed on the fin structure 212 using chemical vapor deposition (CVD), atomic layer deposition (ALD), oxygen plasma oxidation process, or other suitable processes. In some cases, the dummy dielectric layer 216 may comprise silicon oxide. Subsequently, a dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using CVD, ALD, or other suitable processes. In some cases, the dummy electrode layer 218 may comprise polysilicon. For patterning purposes, the gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using CVD, ALD, or other suitable processes. The gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can then be patterned to form a dummy gate stack 220, such as... Figure 6 As shown. For example, the patterning process may include lithography (e.g., optical lithography or electron beam lithography) and etching. The lithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The optical lithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is applied as an etching mask to pattern the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the gate top hard mask layer 222 may include a silicon oxide layer 223 and a silicon nitride layer 224 above the silicon oxide layer 223. Figure 6 As shown, the dummy gate stack 220 is patterned such that it is disposed only above the channel region 212C and not above the source / drain region 212SD.

[0111] refer to Figure 1 and Figure 7Method 100 includes block 110, in which a gate spacer layer 226 is deposited over structure 200 (including over dummy gate stack 220). In some embodiments, the gate spacer layer 226 is conformally deposited over structure 200, including over the top surface and sidewalls of dummy gate stack 220. The term “conformal” may be used herein to describe a layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, or silicon nitride. The gate spacer layer 226 may be deposited over dummy gate stack 220 using processes such as CVD, subatmospheric chemical vapor deposition (SACVD), ALD, or other suitable processes.

[0112] refer to Figure 1 and Figure 8 Method 100 includes block 112, wherein the source / drain regions 212SD of the fin structure 212 are anisotropically etched to form source / drain trenches 228. The anisotropic etching may include dry etching or a suitable etching process that etches the source / drain regions 212SD and a portion of the substrate 202 beneath the source / drain regions 212SD. The anisotropic etching may include multiple etching processes. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and may extend partially into the substrate 202. The exemplary dry etching process of block 112 can use oxygen-containing gases, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3, C4H8 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma and / or combinations thereof. Figure 8 As shown, the source / drain region 212SD of the fin structure 212 is etched to expose the sidewalls of the sacrificial layer 206 and the channel layer 208 in the top stack 204T and the bottom stack 204B. Because the source / drain trench 228 extends below the stack 204 into the substrate 202 and / or the fin substrate structure 212B, the source / drain trench 228 includes a bottom surface and a lower sidewall defined in the substrate 202 and / or the fin substrate structure 212B.

[0113] refer to Figure 1 and Figure 9Method 100 includes block 114, wherein a plurality of channel layers 208 in the channel region are released as channel members 2080. After forming source / drain trench 228, sacrificial layers 206 interleaved with channel layers 208 in channel region 212C are selectively removed. The selective removal of sacrificial layers 206 releases channel layers 208. Figure 8 (as shown) to form Figure 9 The channel component 2080 is shown. The channel component 2080 in the bottom stack 204B may also be referred to as semiconductor component 2080. Selective removal of the sacrificial layer 206 forms a space 229 between adjacent channel components 2080. Selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. Example selective dry etching processes may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Example selective wet etching processes may include APM etching (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture). Depending on the design, the channel component 2080 may be in the form of nanowires, nanosheets, or other nanostructures.

[0114] Although not explicitly shown, the operations in block 114 may include cleaning processes to clean the surfaces of structure 200. Cleaning processes may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using Standard Cleaner 1 (RCA SC-1, a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide), Standard Cleaner 2 (RCA SC-2, a mixture of deionized water, hydrochloric acid, and hydrogen peroxide), SPM (a mixture of sulfur peroxide), and / or hydrofluoric acid to remove oxides.

[0115] refer to Figure 1 and Figure 10 Method 100 includes block 116, in which a dummy layer 230 is deposited around channel member 2080 and over source / drain trench 228. The dummy layer 230 may include a dielectric material. The dielectric material may include oxides, nitrides, carbides, or combinations thereof. Examples of dielectric materials may include silicon oxide, SiCO, SiN, SiCN, and aluminum oxide (e.g., Al2O3). In some embodiments, the dummy layer 230 includes silicon oxide and / or aluminum oxide. The dummy layer 230 may be deposited using plasma-enhanced CVD (PECVD) or ALD. Figure 10 As shown, the dummy layer 230 fills the space 229 between the channel members 2080 and covers the end sidewalls of the channel members 2080. In addition, the dummy layer 230 is in direct contact with the sidewalls of the gate spacer layer 226 and the top surface of the substrate 202 or the base fin substrate structure 212B.

[0116] refer to Figure 1 , Figure 2 and Figure 11 In some embodiments, method 100 includes route A starting from block 116. Route A includes block 126, in which the dummy layer 230 is selectively and partially etched to form an inner spacer recess 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed portion of the substrate 202 or the base fin substrate structure 212B, and the channel member 2080 are substantially left unetched. The remaining dummy layer 230 may include a plurality of sublayers 230 interleaved with the channel member 2080. In embodiments where the channel member 2080 is substantially composed of silicon (Si) and the dummy layer 230 is formed of silicon oxide, selective etching of the dummy layer 230 may be performed using a selective wet etching process or a selective dry etching process. Example selective dry etching processes may include using carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), hydrogen (H2), or mixtures thereof. Example selective wet etching processes may include using hydrofluoric acid, ammonium fluoride, or mixtures thereof.

[0117] refer to Figure 1 , Figure 2 and Figure 12 Route A includes block 128, in which inner spacer members 234 are formed in inner spacer recesses 232. Although not explicitly shown, operations at block 128 may include depositing inner spacer material over structure 200, and etching back the inner spacer material to form inner spacer members 234 in inner spacer recesses 232 (e.g., Figure 12 (As shown). After forming the inner spacer recess 232, an inner spacer material is deposited over the structure 200, including over the inner spacer recess 232. The inner spacer material may include metal oxides, silicon oxides, silicon carbonitride, silicon nitride, silicon oxynitride, carbon-rich silicon carbonitride, or low-k dielectric materials. Metal oxides may include aluminum oxide, zirconium oxide, tantalum oxide, yttrium oxide, titanium oxide, lanthanum oxide, or other suitable metal oxides. Although not explicitly illustrated, the inner spacer material may be a single layer or multiple layers. In some embodiments, CVD, PECVD, SACVD, ALD, or other suitable methods may be used to deposit the inner spacer material. The inner spacer material is deposited in the inner spacer recess 232 and over the sidewalls of the channel member 2080 exposed in the source / drain trench 228. See also Figure 12 Then, the deposited inner spacer material is etched back to remove the inner spacer material from the sidewall of the channel member 2080, thereby forming an inner spacer member 234 in the inner spacer groove 232.

[0118] refer to Figure 1 , Figure 2and Figure 13 Route A includes block 130, in which an isolation layer 236 is formed in the bottom of the source / drain recess 228. Although not explicitly shown, operations in block 130 may include cleaning processes to clean the surfaces of structure 200. Cleaning processes may include dry cleaning, wet cleaning, or a combination thereof. In some examples, wet cleaning may include using a mixture of deionized (DI) water, ammonium hydroxide, and hydrogen peroxide, a mixture of DI water, hydrochloric acid, and hydrogen peroxide, SPM (sulfur peroxide mixture), and / or hydrofluoric acid to remove oxides. Dry cleaning processes may include helium (He) and hydrogen (H2) treatment. Hydrogen treatment can convert silicon on the surface into silane (SiH4), which can be pumped out for removal.

[0119] See Figure 13 The isolation layer 236 may include a dielectric material, an epitaxial material, or a combination thereof. In the illustrated embodiment, the top surface of the isolation layer 236 is higher than the bottom surface of the boundary semiconductor member 2080B (or the topmost surface of the dummy layer 230 below the boundary semiconductor member 2080B). In some embodiments, the top surface of the isolation layer 236 is higher than or coplanar with the top surface of the boundary semiconductor member 2080B, and lower than or coplanar with the bottom surface of the bottommost channel member 2080 of the top stack 204T. In some embodiments, the isolation layer 236 is in direct contact with the inner spacer 234 between the boundary semiconductor member 2080B and the bottommost channel member 2080 of the top stack 204T. In the depicted embodiment, the top surface of the isolation layer 236 has a flat profile. Alternatively, the top surface of the isolation layer 236 may have a concave profile or a convex profile.

[0120] The dielectric material of the isolation layer 236 may include any suitable dielectric material. In some embodiments, the composition of the dielectric material differs from that of the channel member 2080, dummy layer 230, dummy electrode layer 218, gate spacer 226, and inner spacer 234 to allow selective removal by an etching process. In some embodiments, the dielectric material may include silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiOC), silicon carbonitride (SiCN), aluminum oxide, hafnium oxide, or other suitable materials. The dielectric material may be deposited over structure 200 and etched back to form the isolation layer 236 in the bottom of the source / drain trench 228.

[0121] In some embodiments, the epitaxial material of the isolation layer 236 comprises an undoped semiconductor material, such as undoped silicon (Si), undoped germanium (Ge), or undoped silicon-germanium (SiGe). As used herein, an undoped semiconductor material is considered undoped when not intentionally doped. In the example process, the epitaxial material is epitaxially deposited on structure 200 using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), and / or other suitable epitaxial growth methods. Due to crystalline orientation, the epitaxial material deposited on the exposed top surface of the substrate 202 or the base fin substrate structure 212B has fewer defects. This allows for selective removal of the epitaxial material from surfaces other than the exposed top surface of the substrate 202 or the base fin substrate structure 212B.

[0122] In some alternative embodiments, the epitaxial material of the isolation layer 236 includes a counter dopant to reduce leakage current into the bulk substrate 202. For example, the epitaxial material on which the n-type source / drain components (described below) will be formed may include a p-type dopant, such as boron (B). For another example, the epitaxial material on which the p-type source / drain components will be formed may include an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb).

[0123] refer to Figure 1 , Figure 2 and Figure 14Method 100 includes a block 118 extending from route A or route B. At block 118, a source / drain component 238 is formed over an isolation layer 236. The source / drain component 238 may refer individually or collectively to a source or drain, depending on the context. Each source / drain component 238 may be epitaxially and selectively formed from the exposed sidewalls of the channel member 2080 and / or the epitaxial material of the isolation layer 236 (if any) in the top stack 204T using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. Depending on the transistor type, the source / drain component 238 may include an n-type source / drain component and / or a p-type source / drain component. Exemplary n-type source / drain components may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and may be in-situ doped during epitaxial processing by introducing an n-type dopant such as phosphorus, arsenic, or antimony, or ex-situ doped using a junction implantation process. Exemplary p-type source / drain components may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped during epitaxial processing by introducing a p-type dopant (e.g., boron), or ex-situ doped using a junction implantation process. In some embodiments, source / drain component 238 includes more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may include the same or different materials and / or the same or different doping concentrations.

[0124] refer to Figure 1 and Figure 15Method 100 includes block 120, wherein a contact etch stop layer (CESL) 240 and an interlayer dielectric (ILD) layer 242 are formed over source / drain components 238. In some embodiments, the contact etch stop layer (CESL) 240 is deposited over structure 200, including over source / drain components 238. The contact etch stop layer (CESL) 240 may comprise silicon nitride or aluminum nitride. In some embodiments, the contact etch stop layer (CESL) 240 may be deposited using CVD or ALD. The interlayer dielectric (ILD) layer 242 is then deposited over the contact etch stop layer (CESL) 240. In some embodiments, the interlayer dielectric (ILD) layer 242 comprises tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borophosphosilicate glass (BPSG), fused silica glass (FSG), fused silica glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. The interlayer dielectric (ILD) layer 242 can be deposited using CVD, FCVD, spin coating, or suitable deposition techniques. The operations in block 120 may also include planarization processes, such as chemical mechanical planarization (CMP).

[0125] refer to Figure 1 and Figure 16 Method 100 includes block 122 in which dielectric members 244 are formed to cleave fin structure 212 into two segments (e.g., segment 212-1 and segment 212-2). Dielectric member 244 is longitudinally oriented in the Y direction and provides isolation between the segments (e.g., segment 212-1 and segment 212-2). In the depicted embodiment, dielectric member 244 is disposed between two adjacent source / drain members 238. Dielectric member 244 may include one or more dielectric materials 250. The one or more dielectric materials 250 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, silicon carbide, or combinations thereof. Dielectric member 244 may include a single layer or multiple layers. In some embodiments, dielectric member includes one or more air gaps 252.

[0126] The dielectric component 244 can be formed by any suitable method. In some embodiments, the operation in block 122 includes forming trenches to cut the fin structure 212 and filling the trenches with one or more dielectric materials 250. In some embodiments, the dielectric component 244 is formed using a continuous-poly-on-diffusion-edge (CPODE) process. In the CPODE process, the polysilicon gate is replaced by the dielectric component. For the purposes of this invention, "diffusion edge" can be equivalently referred to as an active edge, where, for example, it is an active edge adjacent to an adjacent active region. Prior to the CPODE process, the active edge may include a dummy GAA structure (e.g., Figure 15 The dummy gate stack 220 on the left side of the middle section), the dummy GAA structure has a dummy gate structure and multiple vertically stacked nanostructures as channel layers (e.g., Figure 15 (Stack 204 on the left side). A subsequent polysilicon diffusion edge (CPODE) etching process removes the dummy gate structure and the channel layer beneath it to form a polysilicon diffusion edge (CPODE) trench. One or more dielectric materials are then filled into the polysilicon diffusion edge (CPODE) trench to form a dielectric component. In this embodiment, the dielectric component 244 is also referred to as a polysilicon diffusion edge (CPODE) component.

[0127] refer to Figure 1 and Figures 17 to 21D Method 100 includes block 124, wherein the dummy gate stack 220 and dummy layer 230 in the top stack 204T are replaced with gate structures. Operations at block 124 may include removing the dummy gate stack 220 (e.g., Figures 17-18B (As shown), remove the dummy layer 230 in the top stack 204T (as shown) Figures 19-20B (as shown), and the deposited gate structure 256 to wrap around each channel member 2080 in the top stack 204T (as shown). Figures 21A-21D (As shown).

[0128] refer to Figure 17The dummy gate stack 220 is removed. Before removing the dummy gate stack 220, the structure 200 can be planarized to expose the dummy gate stack 220. For example, the planarization process may include a CMP process. The exposure of the dummy gate stack 220 allows for its removal. The removal step of the dummy gate stack 220 may include one or more etching processes that are selective to the material of the dummy gate stack 220. For example, selective wet etching, selective dry etching, or a combination thereof can be used to perform the removal of the dummy gate stack 220.

[0129] Figure 18A and Figure 18B Examples along Figure 17 A partial cross-sectional view of structure 200 intercepted by line B-B' in the diagram, and Figure 18A and Figure 18B Corresponding to Figure 4A and Figure 4B The structure presented in [the text]. Figure 18A In the illustrated embodiment, after the dummy gate stack 220 is removed, the top surface of the protective layer 215 is exposed. The protective layer 215 may have a first etch rate, and at least a portion of the protective layer 215 remains unetched during the etch process that removes the dummy gate stack 220. In some embodiments, Figure 4A and Figure 18A The vertical distances (e.g., along the Z direction) between the top surface of the boundary semiconductor member 2080B (or boundary semiconductor layer 208B) and the top surface of the protective layer 215 are D1 and D1', respectively. D1 can be greater than or equal to D1'. D1' can be from about 1 nm to about 5 nm, or from about 1 nm to about 3 nm. The top surface of the protective layer 215 is coplanar with or higher than the bottom surface of the boundary semiconductor member 2080B. Figure 18B In the illustrated embodiment, the top surface of the isolation member 214 is exposed after the dummy gate stack 220 is removed. During the etching process for removing the dummy gate stack 220, the isolation member 214 may have a second etch rate. The second etch rate may be greater than the first etch rate. Therefore, the removal step of the dummy gate stack 220 may remove a portion of the isolation member 214. In some embodiments, Figure 4B and Figure 18B The vertical distances between the top surface of the boundary semiconductor component 2080B (or boundary semiconductor layer 208B) and the top surface of the isolation component 214 are D2 and D2', respectively. D2' can be greater than D2. D2' can be from about 5 nm to about 30 nm, or D2' can be from about 5 nm to about 10 nm. The top surface of the isolation component 214 is coplanar with or higher than the bottom surface of the boundary semiconductor component 2080B.

[0130] After removing the dummy gate stack 220, the dummy layer 230 in the top stack 204T in the channel region 212C is exposed, while the dummy layer 230 in the bottom stack 204B is retained, as shown below. Figures 18A-18B As shown. Individual etching processes can be performed to selectively remove the dummy layer 230 in the top stack 204T. For example, selective wet etching or selective dry etching processes can be performed. Example selective wet etching processes may include using diluted hydrofluoric acid (DHF) or a mixture of hydrofluoric acid (HF) and ammonium fluoride (NH4F). Example selective dry etching processes may include using anhydrous hydrogen fluoride (HF) vapor, trifluoromethane (CHF3), nitrogen trifluoride (NF3), hydrogen (H2), ammonia (NH3), carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), or combinations thereof. Gate spacer layer 226, isolation layer 236, internal spacer component 234, isolation component 214, protective layer 215, and dummy layer 230 may include different compositions for etching selectivity. In the depicted embodiment, the dummy layer in the bottom stack 204B is protected from contact with the etchant of the etching process by surrounding components (e.g., sandwiched between isolation components 214 along the Y direction and between isolation layers 236 along the X direction, and disposed below the boundary semiconductor member 2080B). Therefore, the dummy layer 230 in the bottom stack 204B remains unetched, while the dummy layer 230 in the top stack 204T is selectively removed. After the selective removal of the dummy layer 230 in the top stack 204T, the channel member 2080 in the channel region 212C of the top stack 204T is exposed again, as... Figure 19-20B As shown. Figure 20A and Figure 20B Examples along Figure 19 The partial cross-sectional view of structure 200 intercepted by line B-B' in the diagram, and corresponding to... Figure 18A and Figure 18B The structure presented in the diagram. The selective removal step of the dummy layer 230 forms a gate trench 254, which includes a space adjacent to the channel member 2080.

[0131] refer to Figures 21A-21D A gate structure 256 is formed to surround each channel member 2080 released in the top stack 204T. Figure 21B and Figure 21C Examples along Figure 21A The partial cross-sectional view of structure 200 intercepted by line B-B' in the diagram, and corresponding to... Figure 20A and Figure 20B The structure presented in it. Figure 21D Examples along Figure 21A A partial cross-sectional view of structure 200 taken by line C-C'. After releasing the channel members 2080 in the top stack 204T, a gate structure 256 is formed to surround each channel member 2080 in the top stack 204T. Although not explicitly illustrated, the gate structure 256 includes an interface layer interfacing with the channel members 2080 in the top stack 204T and the boundary semiconductor members 2080B in the channel region 212C, a gate dielectric layer above the interface layer, and a gate electrode layer above the interface layer. The interface layer may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material such as hafnium oxide. Alternatively, the gate dielectric layer may also comprise other high-k dielectric materials, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), zirconium oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), lanthanum hafnium oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The gate dielectric layer may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0132] The gate electrode layer may comprise a single layer or, as appropriate, a multilayer structure, such as a metal layer (work function metal layer) having a selected work function to enhance device performance, a substrate, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode may comprise titanium nitride (TiN), aluminum titanium nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes. In various embodiments, a CMP process can be performed to remove excess metal, thereby providing a substantially flat top surface for the gate structure.

[0133] refer to Figure 21A The gate structure 256 includes an inner portion 256a that intersects with the channel member 2080 in the top stack 204T. In the illustrated embodiment, the top surface of the isolation layer 236 is higher than or coplanar with the bottom surface of the bottom inner portion 256a, and lower than or coplanar with the top surface of the bottom inner portion 256a. The isolation layer 236 may provide isolation between the fin substrate structure 212B or substrate 202, the source / drain member 238, and the channel member 2080 (e.g., boundary semiconductor member 2080B) in the bottom stack 204B. The remaining dummy layer 230, a sublayer beneath the boundary semiconductor member 2080B and the adjacent inner spacer member 234, may collectively form an isolation structure 258. The isolation structure 258 may provide isolation between the fin substrate structure 212B and the semiconductor member 2080 in the bottom stack 204B (e.g., 2080B). The isolation structure 258 may have a thickness T0 as described above.

[0134] refer to Figure 21A and Figure 21B The vertical distance (e.g., along the Z direction) D3 between the top surface of the protective layer 215 and the bottom surface of the isolation layer 236 is approximately 10 nm to approximately 60 nm. The isolation structure 258 can be formed horizontally between the top surface of the protective layer 215 and the bottom surface of the isolation layer 236. If D3 is too small, the space for the isolation structure 258 may be too small. If D3 is too large, it may increase the height of the structure 200 excessively, along with the associated cost. Similarly, refer to... Figure 21A and Figure 21CIn embodiments without protective layer 215, the vertical distance between the top surface of the isolation member 214 and the bottom surface of the isolation layer 236 can be within the same range as D3.

[0135] Semiconductor device 200 may undergo further processes to form various components and regions known in the art. For example, subsequent processes may form additional interlayer dielectric (ILD) layers, contacts / vias / wires, and multilayer interconnect components (e.g., metal layers and interlayer dielectrics) over substrate 202, configured to connect various components to form functional circuitry, which may include one or more devices, including semiconductor device 200. In this example, multilayer interconnect components may include vertical interconnects such as vias or contacts and horizontal interconnects such as metal wires. Various interconnects may be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes are used to form copper-associated multilayer interconnect structures.

[0136] refer to Figures 22A-22D In some alternative embodiments, method 100 can be used to form structure 300. Referring to the gate electrode layer, in some alternative embodiments, method 100 can be used to form structure 300. In the embodiment of the gate electrode layer shown, the bottom stack 204B includes more than one (e.g., two) channel members 2080 and more than one (e.g., two) isolation structures 258. Each isolation structure 258 may have a thickness T0 as described above. The semiconductor member 2080 below the boundary semiconductor member 2080B may have a thickness T4, the thickness T4 being similar to or greater than the thickness T2 of the channel member 2080 above the boundary semiconductor member 2080B. In such an embodiment, as Figure 22B The top surface of the protective layer 215 (or as Figure 22C The vertical distance D4 between the top surface of the isolation component 214 and the bottom surface of the isolation layer 236 can be greater than D3. D4 can be in the range of about 10 nm to about 70 nm. The number of isolation structures 258 can be adjusted by adjusting the vertical distance D4. The vertical distance D4 can be increased with the increase of the number and / or thickness of the isolation structures 258.

[0137] refer to Figure 1 , Figure 2 and Figure 23In some alternative embodiments, method 100 includes route B continuing from block 116. For clarity, the structure in such embodiments is designated as structure 400. In some embodiments, the step of route B includes block 132 removing the dummy layer 230 in the source / drain trench 228, while the dummy layer 230 (also referred to as a sublayer of dummy layer 230) in the channel member 2080 remains as depicted. Removal of the dummy layer 230 from the source / drain trench 228 can be performed using any suitable method, such as those described in block 126. Process conditions (e.g., duration, etchant) can be controlled during the operation of block 132. The operation in block 132 can include anisotropic etching. During the operation of block 132, the dummy layer 230 between the channel members 2080 may not be substantially etched.

[0138] refer to Figure 1 , Figure 2 and Figure 24 Route B includes block 134, in which isolation layer 236 is formed in the bottom of source / drain trench 228. Operation in block 134 can be similar to that in block 130 as described above. The difference from the embodiment of block 130 is as follows. In some embodiments, isolation layer 236 and dummy layer 230 are in direct contact with each other in a sublayer between the bottom channel member 2080 and the boundary semiconductor member 2080B of the top stack 204T. In the depicted embodiment, isolation layer 236 is located on the sidewall of dummy layer 230 in the bottom stack 204B. Dummy layer 230 in the bottom stack 204B extends between two adjacent isolation layers 236.

[0139] refer to Figure 1 , Figure 2 and Figure 25 Route B includes block 136, in which sublayers of the dummy layer 230 in the top stack 204T are selectively and partially etched to form inner spacer recesses 232, while the gate spacer layer 226, the dummy gate stack 220, the exposed channel member 2080, the isolation layer 236, and the sublayers of the dummy layer 230 in the bottom stack 204B are substantially unetched. The operation in block 136 can be similar to the operation described in block 126. The difference includes that the sublayers of the dummy layer 230 in the bottom stack 204B are not etched to form inner spacer recesses. In some embodiments, the sublayers of the dummy layer in the bottom stack 204B are subjected to surrounding components (e.g., such as...). Figure 25 As shown, the protection (interposed between the isolation members 214 along the Y direction, between the isolation layers 236 along the X direction, and disposed below the boundary semiconductor member 2080B) prevents contact with the etchant of the selective etching process. Therefore, the sublayers of the dummy layer 230 in the bottom stack 204B remain unetched, while the sublayers of the dummy layer 230 in the top stack 204T are selectively and partially etched.

[0140] refer to Figure 1 , Figure 2 and Figure 26 Route B includes block 138, in which inner spacer members 234 are formed in inner spacer recesses 232, similar to those described in block 128. The difference includes that no inner spacer members are formed between the sublayer of the dummy layer 230 and the isolation layer 236 in the bottom stack 204B.

[0141] refer to Figure 1 , Figure 2 and Figure 27 Structure 400 can then continue to undergo the process described above in blocks 118 to 124. Figure 27 A partial cross-sectional view is shown after the operation of structure 400 in block 124. (Compared to...) Figures 21A-21D The differences in structure 200 are as follows. Figure 27 In the illustrated embodiment, sublayers of the dummy layer 230 extend between adjacent isolation layers 236. No inner spacer is provided between the dummy layer 230 and the adjacent isolation layers 236. In other words, the isolation structure 258 includes the dummy layer 230 but does not include inner spacer components. The isolation structure 258 may have a thickness T0 as described above. Figure 27 The partial cross-sectional views along line B-B' and C-C' are similar. Figures 21B-21D .

[0142] Figure 28 A partial cross-sectional view of the alternative structure 500 formed by method 100 after operation in block 124 is shown. Structure 500 can be formed similarly to structure 400. The differences from structure 300 in the gate electrode layer are as follows. Figure 28 In the illustrated embodiment, sublayers of the dummy layer 230 extend between adjacent isolation layers 236. No inner spacers are provided between the sublayers of the dummy layer 230 and the adjacent isolation layers 236. In other words, each isolation structure 258 includes a sublayer of the dummy layer 230 but does not include inner spacers. Each isolation structure 258 may have a thickness T0 as described above. Figure 28 The partial cross-sectional views along line B-B' and C-C' are similar. Figure 22B-22D .

[0143] Those skilled in the art will recognize that, although Figures 3-28 The GAA device is shown as an example, but other examples of semiconductor devices (such as fork-sheet transistors, complementary field-effect transistors, CFETs) can benefit from various forms of this invention.

[0144] While not intended to be limiting, one or more embodiments of the present invention provide numerous benefits to semiconductor devices. For example, the present invention provides a semiconductor structure having an isolation structure extending between adjacent isolation layers located below the channel layer and below the source / drain components. This mitigates current leakage from the channel layer and the source / drain components, prevents latch-up problems between the source / drain elements, avoids trigger voltage failures, and improves the overall performance of the semiconductor device.

[0145] In one exemplary embodiment, the present invention relates to a method. This method includes providing a fin substrate and forming an isolation member disposed adjacent to the fin substrate. The fin substrate protrudes from a substrate. The top surface of the isolation member is located above the bottom surface of the bottommost channel layer. The method further includes forming a dummy gate structure over a channel region of alternating channel layers and sacrificial layers; depositing a gate spacer layer over the dummy gate structure; forming source / drain trenches in a source / drain region of alternating channel layers and sacrificial layers; selectively removing the sacrificial layer in the channel region to release the channel layer as a channel member; depositing a dummy layer over the channel member and in the source / drain trench; selectively partially etching the dummy layer to form an inner spacer trench between the channel members; and forming an inner spacer member in the inner spacer trench. The remaining dummy layers include sublayers interleaved with the channel members. The method also includes forming an isolation layer over the source / drain region. The top surface of the isolation layer is higher than the top surface of the bottommost sublayer. This method further includes forming source / drain components on the isolation layer, removing the dummy gate structure and the top of the sublayer, and forming a gate structure that surrounds the top of the channel member.

[0146] In some embodiments, the isolation layer includes a dielectric material, an undoped epitaxial layer, or a combination thereof, and the source / drain component includes a doped epitaxial layer. In some embodiments, the method further includes forming a dielectric structure adjacent to the isolation layer and the source / drain component, and the dielectric structure extends through the channel layer and into the substrate. In some embodiments, the isolation component includes a dielectric layer and a hard masking layer above the dielectric layer. In some embodiments, removing the top of the dummy gate structure and sublayer further removes the top of the isolation component below the dummy gate structure and forms a gate trench, and the top surface of the remaining portion of the isolation component in the gate trench is above the bottom surface of the bottommost channel layer. In some embodiments, the method further includes removing the dummy layer in the source / drain trench before selectively and partially etching the dummy layer to form an internal isolation trench, and forming the isolation layer above the source / drain region after removing the dummy layer in the source / drain trench and before selectively and partially etching the dummy layer to form an internal sidewall trench. In some embodiments, the top of the sublayer includes at least one sublayer, and the top of the channel component includes at least one channel component. In some embodiments, the bottommost sublayer is retained after the top of the dummy gate structure and sublayer is removed. In some embodiments, in a cross-sectional view, the gate structure includes an inner portion that intersects with the top of the channel member, and the top surface of the isolation layer is located between the horizontal levels of the top and bottom surfaces of the bottommost inner portion of the gate structure.

[0147] In another exemplary embodiment, the present invention relates to a method. This method includes forming a stack of channel layers and sacrificial layers over a fin substrate. The sacrificial layer includes a top and a bottom below the top. The method further includes forming an isolation member adjacent to the fin substrate and the stack; forming a dummy gate structure disposed over the stack and the isolation member; forming a source / drain trench in the fin substrate and exposing the sidewalls of the sacrificial layer; selectively removing the top of the sacrificial layer to form a top opening and selectively removing the bottom of the sacrificial layer to form a bottom opening; depositing a dummy layer in the top and bottom openings; selectively and partially etching the dummy layer to form an internal spacer recess between the channel layers; forming an internal spacer member in the internal spacer recess; forming a source / drain member in the source / drain trench; and replacing the dummy gate structure and dummy layer in the top opening with a metal gate structure, but not replacing the dummy layer in the bottom opening.

[0148] In some embodiments, the bottom of the sacrificial layer includes at least one sacrificial layer, and the top surface of the isolation member is located above the topmost surface of the bottom of the sacrificial layer. In some embodiments, the method further includes forming an isolation layer in the source / drain trench before forming the source / drain member in the source / drain trench. The isolation layer includes a dielectric layer, an undoped epitaxial layer, or a combination thereof, and the step of forming the source / drain member includes forming the source / drain member over the isolation layer. In some embodiments, the top surface of the isolation layer is located above the topmost surface of the bottom of the sacrificial layer. In some embodiments, the step of replacing the dummy gate structure and dummy layer in the top opening with a metal gate structure, but not replacing the dummy layer in the bottom opening, includes: removing the dummy gate structure to form a gate trench, selectively removing the dummy layer in the top opening while the dummy layer in the bottom opening is protected by the isolation member and the source / drain member, and forming a metal gate structure in the top opening and the gate trench. In some embodiments, the top and bottom of the sacrificial layer are isolated by a boundary channel layer in a channel layer having a first thickness, and one of the channel layers above the boundary channel layer having a second thickness less than the first thickness. In some embodiments, the top surface of the isolation component is approximately 10 nm to approximately 60 nm above the bottom surface of the source / drain trench.

[0149] In another exemplary embodiment, this invention relates to a semiconductor structure. This semiconductor structure includes a fin substrate protruding from a substrate, two isolation layers disposed above the substrate, two source / drain components disposed above the two isolation layers, an isolation structure disposed above the fin substrate and connecting the two isolation layers, and a stack of semiconductor layers disposed above the isolation structure. The semiconductor layer stack includes a bottom semiconductor layer and a top semiconductor layer disposed above the bottom semiconductor layer, the bottom semiconductor layer connecting the two isolation layers, and the top semiconductor layer connecting the two source / drain components. The semiconductor structure also includes isolation components and an isolation structure disposed adjacent to the fin substrate, and a metal gate structure surrounding the top semiconductor layer. The top surface of the isolation component is located above the top surface of the isolation structure.

[0150] In some embodiments, the two isolation layers comprise a dielectric material, an epitaxial material, or a combination thereof. In some embodiments, the top surface of the isolation member is approximately 10 nm to approximately 60 nm above the bottom surface of the two isolation layers. In some embodiments, the isolation structure comprises a dielectric layer and two inner spacers that enclose the dielectric layer, each of the two inner spacers being disposed between the dielectric layer and one of the two isolation layers.

[0151] The components of several embodiments are outlined above to facilitate a better understanding of the present invention by those skilled in the art. Those skilled in the art should understand that they can design or modify other processes and structures based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that they can make various changes, substitutions, and replacements without departing from the spirit and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, include: A fin substrate protrudes from a substrate; Two isolation layers are disposed above the substrate; Two source / drain components are disposed above the two isolation layers; An isolation structure is disposed above the fin substrate and connects the two isolation layers; A stack of multiple semiconductor layers is disposed above the isolation structure, wherein the stack of semiconductor layers includes a bottom semiconductor layer and multiple top semiconductor layers disposed above the bottom semiconductor layer, wherein the bottom semiconductor layer connects the two isolation layers, and wherein the top semiconductor layers connect the two source / drain components; An isolation component is disposed adjacent to the fin substrate and the isolation structure, wherein the top surface of the isolation component is located above the top surface of the isolation structure; and A metal gate structure surrounds the top semiconductor layer.

2. The semiconductor device as claimed in claim 1, characterized in that, The top surfaces of the two isolation layers have a concave profile.

3. The semiconductor device as claimed in claim 1 or 2, characterized in that, The top surface of the isolation component is approximately 10 nm to approximately 60 nm higher than the bottom surface of the two isolation layers.

4. The semiconductor device as claimed in claim 1, characterized in that, The isolation structure includes a dielectric layer and two inner spacers that enclose the dielectric layer. Each of the two inner spacers is disposed between the dielectric layer and one of the two isolation layers.

5. The semiconductor device as claimed in claim 4, characterized in that, The two inner spacer components connect the two isolation layers.

6. The semiconductor device as claimed in claim 4, characterized in that, The top surfaces of the two inner spacers are higher than the top surfaces of the two isolation layers.

7. The semiconductor device as claimed in claim 4, characterized in that, The metal gate structure includes an internal portion sandwiched between the two inner spacer components.

8. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the metal gate structure is lower than the top surface of the two source / drain components.

9. The semiconductor device as claimed in claim 1, characterized in that, The top surface of the isolation component is approximately 10 nm to approximately 70 nm higher than the bottom surface of the two isolation layers.

10. The semiconductor device as claimed in claim 1, characterized in that, The bottom surface of the isolation component is higher than the bottom surface of the two isolation layers.

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