Display panel and display device

Abstract

Embodiments of the present application provide a display panel, which comprises a gate layer, a silicon island layer and a drain layer. The gate layer is arranged along a first direction, and the gate layer is provided with a silicon island region. The silicon island layer is arranged on the gate layer and located in the silicon island region. The drain layer is arranged along a second direction, and the first direction and the second direction are perpendicular to each other. The drain layer comprises an extension part, the extension part extends to the silicon island layer, and the extension part forms a first capacitor with the gate layer in the silicon island region. The gate layer extends a connecting part on a side away from the drain layer, and the extension part and the connecting part overlap to form a second capacitor. The technical scheme forms two capacitors in the display panel by arranging the overlapping structure of the extension part and the connecting part. The scheme improves the capacitor performance by optimizing the device structure without increasing additional process steps, thereby improving the stability of the driving voltage and improving the display effect.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a display panel and display device. Background Technology

[0002] A display screen is a component in electronic devices used to display images and text, typically consisting of three main parts: a display unit, a glass substrate, and driving circuitry. Display screens are widely used in televisions, computer monitors, mobile phones, tablets, e-readers, automotive displays, and other fields. They are crucial infrastructure for daily life and the modern electronic information industry. With technological advancements, display screens are also being applied to emerging fields such as wearable devices, smart homes, and medical devices, driving the development of related industries.

[0003] Currently, TFT LCD displays often suffer from insufficient capacitance, resulting in a significant drop in feedthrough voltage and unstable driving voltage, which affects the display effect.

[0004] Therefore, a display panel and display device are provided that can avoid insufficient capacitance and improve display effect. Utility Model Content

[0005] This application provides a display panel and display device that can avoid insufficient capacitance and improve display effect.

[0006] In a first aspect, this application provides a display panel, comprising: A gate layer is disposed along a first direction, and a silicon island region is disposed on the gate layer; A silicon island layer is disposed on the gate layer and located in the silicon island region; A drain layer is disposed along a second direction, wherein the first direction intersects the second direction perpendicularly; The drain layer includes an extension that extends onto the silicon island layer. The extension forms a first capacitor with the gate layer in the silicon island region. The gate layer extends a connection portion on the side away from the drain layer. The extension and the connection portion overlap to form a second capacitor.

[0007] In some embodiments, an insulating layer is provided between the connecting portion and the drain layer, and the insulating layer is provided with a via, through which the connecting portion and the drain layer are connected.

[0008] In some embodiments, the silicon island layer is a hafnium dioxide layer.

[0009] In some embodiments, the insulating layer is a silicon dioxide layer.

[0010] In some embodiments, the connection portion adopts a serpentine wiring structure.

[0011] In some embodiments, a shielding layer is provided in the overlapping area of ​​the extension and the connecting portion.

[0012] In some embodiments, the shielding layer is a molybdenum layer.

[0013] In some embodiments, the system further includes a substrate, wherein the gate layer is disposed on the substrate.

[0014] In some embodiments, the substrate is a polyimide flexible substrate.

[0015] Secondly, another embodiment of this application also provides a display device, including the display panel described in the above embodiments.

[0016] This application proposes a display panel including a gate layer, a silicon island layer, and a drain layer. The gate layer is disposed along a first direction, and a silicon island region is formed on the gate layer. The silicon island layer is disposed on the gate layer and located within the silicon island region. The drain layer is disposed along a second direction, with the first direction intersecting the second direction perpendicularly. The drain layer includes an extension extending onto the silicon island layer, forming a first capacitor with the gate layer in the silicon island region. A connection portion extends from the gate layer on a side away from the drain layer, and the extension portion overlaps with the connection portion to form a second capacitor. This technical solution forms two capacitors in the display panel by setting an overlapping structure of the extension portion and the connection portion. The first capacitor is formed by the extension portion and the gate layer in the silicon island region, and the second capacitor is formed by the overlap of the extension portion and the connection portion. This dual-capacitor structure can effectively increase the total capacitance value and avoid the problem of feedthrough voltage drop due to insufficient capacitance. Compared with the prior art, this solution improves capacitor performance by optimizing the device structure without adding additional process steps, thereby improving the stability of the driving voltage and enhancing the display effect. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the display panel structure provided in this application; Figure 2 This is a cross-sectional schematic diagram of the display panel provided in this application in region A; Figure 3 This is another schematic diagram of the display panel structure provided in this application; Figure 4 This is another structural schematic diagram of the display panel provided in this application; Figure 5 This is a schematic diagram of the display device structure provided in this application. Detailed Implementation

[0018] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings and embodiments. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0019] Furthermore, the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order. The terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0020] This application provides a display panel and a display device.

[0021] Please see Figures 1 to 4 This application provides a display panel 100, including a gate layer 10, a silicon island layer 20, and a drain layer 30. The gate layer 10 is disposed along a first direction, and a silicon island region is disposed on the gate layer 10. The silicon island layer 20 is disposed on the gate layer 10 and located in the silicon island region 11. The drain layer 30 is disposed along a second direction, and the first direction intersects the second direction perpendicularly. The drain layer 30 includes an extension 31 extending onto the silicon island layer 20, and the extension 31 forms a first capacitor with the gate layer 10 in the silicon island region 11. A connection portion 12 extends from the side of the gate layer 10 away from the drain layer 30, and the extension 31 overlaps with the connection portion 12 to form a second capacitor.

[0022] Unless otherwise specified, the first direction is horizontal and the second direction is vertical by default.

[0023] The gate layer 10 can be made of a metallic material, such as aluminum, copper, or molybdenum. The silicon island layer 20 can be made of a semiconductor material, such as amorphous silicon, polycrystalline silicon, or oxide semiconductor. The drain layer 30 can be made of the same or different conductive material as the gate layer 10. The extension 31 can be designed as rectangular, trapezoidal, or other shapes to optimize capacitance. The connection portion 12 can use a straight trace or a serpentine trace structure. The capacitance of the first capacitor and the second capacitor can be controlled by adjusting the overlap area or the dielectric layer thickness.

[0024] This technical solution forms two capacitors in the display panel 100 by setting an overlapping structure of the extension portion 31 and the connecting portion 12. The first capacitor is formed by the extension portion 31 and the gate layer 10 in the silicon island region 11, and the second capacitor is formed by the overlap of the extension portion 31 and the connecting portion 12. This dual-capacitor structure can effectively increase the total capacitance value and avoid the problem of feedthrough voltage drop caused by insufficient capacitance. Compared with the prior art, this solution improves capacitor performance by optimizing the device structure without adding additional process steps, thereby improving the stability of the driving voltage and enhancing the display effect.

[0025] Furthermore, this application also proposes to provide an insulating layer 40 between the connecting portion 12 and the drain layer 30, and the insulating layer 40 is provided with a via 41, through which the connecting portion 12 and the drain layer 30 are connected.

[0026] Specifically, the insulating layer 40 can be fabricated using dielectric materials such as silicon dioxide, with a thickness controlled in the range of 100-500 nanometers. Vias 41 can be formed through photolithography and etching processes, with a aperture of 1-5 micrometers. The connection between the connector 12 and the drain layer 30 can be achieved by sputtering and depositing a metal material, such as aluminum or copper. As a preferred embodiment, the insulating layer 40 can be a double-layer structure, with a bottom layer of silicon dioxide and an upper layer of silicon nitride, with a thickness ratio of 2:1. The via 41 can be designed in a tapered shape, with an upper diameter larger than the lower diameter, which facilitates metal filling. The contact resistance between the connector 12 and the drain layer 30 can be reduced to below 10 ohms through a rapid thermal annealing process.

[0027] Therefore, this technical solution achieves a reliable electrical connection between the gate layer 10 and the drain layer 30 by introducing an insulating layer 40 and a via structure 41 in the overlapping region. The insulating layer 40 effectively isolates the parasitic effects of the overlapping capacitance, while the via structure 41 ensures the stability of signal transmission. Compared with existing technologies, this design maintains necessary capacitive coupling while avoiding leakage current problems caused by poor insulation, thereby improving the driving voltage stability of the display panel 100. Specifically, under the same operating conditions, the feedthrough voltage fluctuation amplitude can be reduced by more than 30%, and the display uniformity is significantly improved.

[0028] Furthermore, this application also proposes that the silicon island layer 20 is a hafnium dioxide layer.

[0029] Hafnium dioxide is a material with a high dielectric constant of approximately 25. As a material choice for the silicon island layer 20, hafnium dioxide can be formed using physical vapor deposition or atomic layer deposition processes. Specifically, a hafnium dioxide thin film can be deposited on the gate layer 10 using radio frequency magnetron sputtering, with the deposition temperature controlled within the range of 200-300°C, and the film thickness preferably 50-100 nanometers. Alternatively, a hafnium dioxide layer can be selectively grown in the silicon island region 11 using chemical vapor deposition.

[0030] Using hafnium dioxide as the material for the silicon island layer 20 effectively improves the capacitive coupling between the gate layer 10 and the drain layer 30. Due to the high dielectric properties of hafnium dioxide, a larger first capacitance value can be formed at the same thickness, thereby improving the feed-through voltage problem of TFT devices. Simultaneously, hafnium dioxide has good thermal and chemical stability, and its material properties are not easily degraded during the manufacturing process of the display panel 100. In practice, the size of the first capacitance can be precisely controlled by adjusting the thickness and area of ​​the hafnium dioxide layer to meet different display driving requirements.

[0031] Furthermore, this application also proposes to provide an insulating layer 40 between the connecting portion 12 and the drain layer 30, the insulating layer 40 having a via 41, the connecting portion 12 and the drain layer 30 being connected through the via 41, and the insulating layer 40 being a silicon dioxide layer.

[0032] Specifically, the silicon dioxide layer as the insulating layer 40 can be implemented in the following ways: the silicon dioxide layer can be formed by chemical vapor deposition, with a thickness controlled in the range of 100-500 nanometers; it can also be grown directly on a silicon substrate by thermal oxidation; or it can be formed by spin coating a liquid silicon dioxide precursor and then curing it. As a preferred embodiment, the dielectric constant of the silicon dioxide layer is about 3.9, which can effectively isolate the electrical connection between the connection portion 12 and the drain layer 30, while realizing conduction at specific locations through the via 41.

[0033] The working principle of this technical solution is as follows: while maintaining overall insulation between the connection portion 12 and the drain layer 30, the silicon dioxide insulating layer 40 achieves partial conductivity through precisely positioned vias 41. This maintains the stability of the second capacitor structure and ensures the reliability of the signal transmission path. Compared with conventional insulating materials, silicon dioxide has higher dielectric strength and more stable chemical properties, effectively preventing leakage current and improving the long-term operational stability of the capacitor structure. Specifically, in the application of the display panel 100, this structure helps maintain the stability of the driving voltage and improves the problem of feedthrough voltage drop caused by insufficient capacitance.

[0034] Furthermore, this application also proposes that the connecting part 12 adopts a serpentine wiring structure.

[0035] Specifically, the serpentine trace structure refers to a trace pattern in which the connection portion 12 exhibits periodic bending in a planar layout, with bending angles typically between 90 and 180 degrees. As a preferred embodiment, the serpentine trace can be designed as a continuous, equally spaced "S"-shaped structure, with the spacing between adjacent trace segments controlled within the range of 5-20 micrometers. For example, this structure can be implemented on the gate metal layer using photolithography, fabricated using a molybdenum / aluminum / molybdenum three-layer composite metal material, wherein the top molybdenum layer has a thickness of 30-50 nanometers.

[0036] Therefore, by adopting a serpentine routing structure, the overlap area between the connecting portion 12 and the extension portion 31 can be effectively increased, thereby improving the capacitance value of the second capacitor. Specifically, the periodic bending design of the serpentine routing significantly increases the effective overlap length per unit length, increasing the capacitor area by 30%-50% compared to a straight routing structure. Simultaneously, this structure helps to evenly distribute the electric field intensity, avoiding the risk of insulation layer 40 breakdown caused by localized electric field concentration. Furthermore, the symmetrical layout characteristics of the serpentine routing can compensate for alignment deviations during manufacturing, improving product yield.

[0037] Furthermore, this application also proposes that a shielding layer 50 be provided in the overlapping area of ​​the extension 31 and the connecting part 12.

[0038] The shielding layer 50 can be made of a metallic material, such as a molybdenum layer. The function of the shielding layer 50 is to reduce the impact of external interference on the second capacitance formed between the extension 31 and the connecting portion 12. Specifically, the shielding layer 50 can be disposed above or below the overlapping area of ​​the extension 31 and the connecting portion 12, or simultaneously on both the upper and lower sides. As a preferred embodiment, an insulating layer 40 can be provided between the shielding layer 50 and the extension 31 or the connecting portion 12 for isolation. The shape of the shielding layer 50 can be adjusted according to the shape of the overlapping area, for example, using a rectangle, a circle, or other suitable shapes. The thickness of the shielding layer 50 can be selected according to actual needs, typically in the range of tens to hundreds of nanometers.

[0039] Therefore, by providing a shielding layer 50 in the overlapping area of ​​the extension 31 and the connecting portion 12, the influence of external electromagnetic interference on the second capacitor can be effectively reduced, thereby improving the stability of the capacitor. Specifically, the shielding layer 50 can block the interference of external electric fields on the overlapping area, preventing fluctuations in the capacitance value. Furthermore, the shielding layer 50 can also reduce noise interference during signal transmission, improving the signal transmission quality of the display panel 100. Compared with the prior art, this technical solution can achieve improved capacitor stability through simple structural improvements, without the need for complex process adjustments, and has good practicality and feasibility.

[0040] Furthermore, this application also proposes that the display panel 100 further includes a substrate 60, on which the gate layer 10 is disposed.

[0041] The substrate 60, serving as a support structure, can be made of rigid or flexible materials. Specifically, in a preferred embodiment, the substrate 60 can be a flexible polyimide substrate 60, which possesses characteristics such as high temperature resistance, chemical corrosion resistance, and high mechanical strength. Furthermore, a buffer layer can be disposed on the surface of the substrate 60 to improve adhesion to the gate layer 10; the buffer layer material can be silicon dioxide or silicon nitride. The thickness of the substrate 60 is typically in the range of 0.1-1.0 mm, and the specific value can be adjusted according to the overall structural design requirements of the display panel 100.

[0042] This technical solution provides a stable support structure for the display panel 100 by placing a substrate 60 below the gate layer 10. The use of a flexible polyimide substrate 60 allows the display panel 100 to have bendable characteristics while maintaining good electrical performance. The introduction of the substrate 60 enables the gate layer 10 to achieve a flat deposition surface, which is beneficial for improving the uniformity and reliability of thin-film transistor devices. Compared with the conventional method of forming the gate layer 10 directly on the glass substrate 60, this solution provides the foundation for the thinner and more flexible design of the display panel 100 while maintaining structural stability.

[0043] Please see Figure 5 Another embodiment of this application also provides a display device 1000, including the display panel 100 described in the above embodiments. Since the display panel 100 has been described in detail in the above embodiments, the display panel 100 in this application will not be described in detail again.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, include: A gate layer is disposed along a first direction, and a silicon island region is disposed on the gate layer; A silicon island layer is disposed on the gate layer and located in the silicon island region; A drain layer is disposed along a second direction, wherein the first direction intersects the second direction perpendicularly; The drain layer includes an extension that extends onto the silicon island layer. The extension forms a first capacitor with the gate layer in the silicon island region. The gate layer extends a connection portion on the side away from the drain layer. The extension and the connection portion overlap to form a second capacitor.

2. The display panel according to claim 1, characterized in that, An insulating layer is provided between the connecting part and the drain layer, and the insulating layer is provided with a via. The connecting part and the drain layer are connected through the via.

3. The display panel according to claim 1, characterized in that, The silicon island layer is a hafnium dioxide layer.

4. The display panel according to claim 2, characterized in that, The insulating layer is a silicon dioxide layer.

5. The display panel according to claim 1, characterized in that, The connection part adopts a serpentine wiring structure.

6. The display panel according to claim 1, characterized in that, A shielding layer is provided in the overlapping area of ​​the extension and the connecting part.

7. The display panel according to claim 6, characterized in that, The shielding layer is a molybdenum metal layer.

8. The display panel according to claim 1, characterized in that, It also includes a substrate, wherein the gate layer is disposed on the substrate.

9. The display panel according to claim 8, characterized in that, The substrate is a polyimide flexible substrate.

10. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 9.

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