Semiconductor processing apparatus

Abstract

The application discloses a semiconductor process equipment, and belongs to the technical field of semiconductor processing. The disclosed semiconductor process equipment comprises a process chamber, a wafer support seat, a control device and a detection piece. The process chamber is provided with a detection port. The wafer support seat is arranged in the process chamber. The detection piece is arranged opposite to the detection port. The detection piece is used for detecting the inclination angle of a wafer through the detection port. The control device is connected with the detection piece. The control device is used for controlling the adsorption force of the wafer support seat on the wafer according to the inclination angle. The above scheme can solve the problem that the related art semiconductor process equipment is prone to causing low yield of wafers.

Description

Technical Field

[0001] This application belongs to the field of semiconductor processing technology, specifically relating to a semiconductor process equipment. Background Technology

[0002] In semiconductor processing equipment, wafer supports are typically used within the process chamber to hold the wafers in place, ensuring their stability during processing. After the process is complete, surface defects on the wafers can be inspected to sort out qualified wafers.

[0003] During wafer fabrication, wafers are prone to tilting or even breakage due to changes in the adhesion force of the wafer support, vibration of the wafer support, or excessive thermal stress. This can lead to a lower yield rate and consequently, lower wafer production. Therefore, the semiconductor process equipment involved in this technology is susceptible to problems that can result in lower wafer production. Utility Model Content

[0004] This application discloses a semiconductor process equipment to solve the problem that semiconductor process equipment involved in related technologies easily leads to low wafer yield.

[0005] To solve the above-mentioned technical problems, this application adopts the following technical solution: A semiconductor process apparatus includes a process chamber, a wafer support, a control device, and a testing device; The process chamber is provided with a detection port, the wafer support is disposed in the process chamber, the detection element is disposed opposite to the detection port, and the detection element is used to detect the tilt angle of the wafer through the detection port. The control device is connected to the detection element to control the magnitude of the adsorption force of the wafer support on the wafer according to the tilt angle.

[0006] The technical solution adopted in this application can achieve the following beneficial effects: In this application, during wafer processing, a detection device can detect the wafer's tilt angle through a detection port. Since the control device is connected to the detection device, it can control the magnitude of the wafer support's suction force on the wafer based on the tilt angle, ensuring the wafer returns to its initial position. This prevents breakage due to a further increase in the tilt angle, thereby improving wafer yield and output. Furthermore, because the detection device can detect the wafer's tilt angle in real-time during processing, the control device can perform relevant operations based on the tilt angle to promptly prevent wafer breakage. Therefore, the semiconductor process equipment disclosed in this application solves the problem of low wafer yield that often exists in related semiconductor process equipment. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of the structure of the semiconductor process equipment disclosed in the embodiments of this application; Figure 2 This is a schematic diagram of the structure of the process chamber disclosed in the embodiments of this application; Figure 3 and Figure 4 These are schematic cross-sectional views of the process chambers disclosed in the embodiments of this application from different perspectives; Figure 5 This is a schematic diagram of the wafer in a normal state as disclosed in the embodiments of this application; Figure 6 This is a schematic diagram of the wafer in a tilted state as disclosed in an embodiment of this application.

[0008] Explanation of reference numerals in the attached figures: 100 - Process chamber, 110 - Inspection port, 120 - Light transmission port, 130 - Side wall, 140 - Wafer transmission port; 200 - Wafer support base, 210 - Wafer support surface; 300 - Control device; 400 - Inspection piece, 410 - First inspection piece, 420 - Second inspection piece, 430 - Third inspection piece; 500-Wafer; 600 - Lighting component; 700 - Display device. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0010] The semiconductor process equipment disclosed in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0011] Please refer to Figures 1 to 6 This application discloses a semiconductor process equipment, which includes a process chamber 100, a wafer support 200, a control device 300, and a testing device 400.

[0012] The process chamber 100 is the location for processing the wafer 500, and the process chamber 100 is provided with a detection port 110. Optionally, a quartz plate with high light transmittance can be provided at the detection port 110 to serve as an isolation medium between the inside and outside of the process chamber 100, thereby ensuring the accuracy of the detection of the test piece 400 while meeting the sealing requirements of the process chamber 100. Optionally, the shape of the detection port 110 can be circular, and its diameter can be 100 mm. Of course, this embodiment of the application does not impose specific limitations on this.

[0013] The wafer support 200 is disposed in the process chamber 100 to support and adsorb the wafer 500, thereby ensuring the placement stability of the wafer 500 during the processing of the wafer 500. The detection element 400 is disposed opposite to the detection port 110 so that the detection element 400 can detect the tilt angle of the wafer 500 through the detection port 110. The control device 300 is connected to the detection element 400 to control the magnitude of the adsorption force of the wafer support 200 on the wafer 500 according to the tilt angle.

[0014] In this embodiment, since the control device 300 can control the magnitude of the adsorption force of the wafer support 200 on the wafer 500 according to the tilt angle of the wafer 500, this can prevent the wafer 500 from breaking due to excessive tilt angle during the process. In other words, this setting method can facilitate the real-time detection of the tilt degree of the wafer 500, thereby restoring it to a normal state.

[0015] In this application, during the processing of wafer 500, the detection element 400 can detect the tilt angle of wafer 500 through the detection port 110. Since the control device 300 is connected to the detection element 400, the control device 300 can control the magnitude of the adsorption force of the wafer support 200 on wafer 500 based on the tilt angle, so that wafer 500 can return to its initial position. This prevents wafer 500 from breaking due to a further increase in tilt angle, thereby improving the yield and output of wafer 500. Simultaneously, since the detection element 400 can detect the tilt angle of wafer 500 in real time during processing, the control device 300 can perform relevant operations based on the tilt angle of wafer 500 in real time to promptly prevent wafer 500 breakage. Therefore, the semiconductor process equipment disclosed in this application can solve the problem of low wafer 500 yield that often exists in related semiconductor process equipment.

[0016] Alternatively, please refer to Figure 5 and Figure 6The wafer support 200 has a wafer support surface 210 for supporting the wafer 500. In the detection direction of the detection element 400, the detection center of the detection element 400 is flush with the wafer support surface 210. That is, the detection center of the detection element 400 and the wafer support surface 210 are in the same plane parallel to the detection direction of the detection element 400. In other words, the detection center of the detection element 400 is flush with the surface of the wafer 500 facing the wafer support surface 210, thereby increasing the accuracy of the detection results obtained by the detection element 400 during the detection of the tilt angle of the wafer 500. Of course, in other embodiments, the detection center of the detection element 400 may not be flush with the wafer support surface 210.

[0017] Optionally, the process chamber 100 may be provided with a detection port 110. Correspondingly, the semiconductor process equipment may include a detection element 400, with the detection port 110 disposed opposite to the detection element 400. Alternatively, the process chamber 100 may be provided with two detection ports 110, with each detection port 110 disposed at a circumferential interval along the process chamber 100. Correspondingly, the semiconductor process equipment may include two detection elements 400, wherein each detection port 110 may correspond to one detection element 400.

[0018] In another embodiment, please refer to Figures 1 to 3 The process chamber 100 may be provided with at least three detection ports 110, which are spaced apart circumferentially along the process chamber 100. Each detection port 110 corresponds to at least one detection element 400, so as to ensure that the total detection area of ​​the multiple detection elements 400 can fully cover the wafer 500, while avoiding false detections caused by blind spots or other interferences through redundant detection. Optionally, each detection port 110 may correspond to one detection element 400, which can reduce costs to a certain extent while ensuring the above effects.

[0019] Optionally, as described above, the process chamber 100 is provided with at least three detection ports 110, each detection port 110 corresponding to at least one detection element 400. That is, the semiconductor process equipment may include at least three detection elements 400, including a first detection element 410, a second detection element 420, and a third detection element 430. Please refer to [reference needed]. Figure 1 The first detection element 410 and the second detection element 420 can be arranged opposite each other, and their detection directions are parallel. That is, the first detection element 410 and the second detection element 420 can be arranged on both sides of the wafer 500. The detection direction of the third detection element 430 intersects with the detection directions of the first detection element 410 and the second detection element 420. It should be noted that the above-mentioned at least three detection elements 400 detect simultaneously, and the synchronization error is less than 1ms.

[0020] In this embodiment, since the first detection element 410 and the second detection element 420 can be arranged on both sides of the wafer 500, that is, the two detection ports 110 corresponding to the first detection element 410 and the second detection element 420 can be arranged on both sides of the wafer 500, and the detection direction of the third detection element 430 intersects with the detection directions of the first detection element 410 and the second detection element 420, that is, the orientation direction of the detection port 110 corresponding to the third detection element 430 intersects with the orientation directions of the two detection ports 110, this allows the detection ports 110 to be basically evenly distributed along the circumference of the process chamber 100, so as to avoid affecting the structural strength of the process chamber 100 due to the concentrated arrangement of the detection ports 110. Of course, in other embodiments, the detection direction of the first detection element 410 and the detection direction of the second detection element 420 may not be parallel.

[0021] In addition, please refer to Figure 2 and Figure 4 The process chamber 100 is typically provided with a wafer transfer port 140, which is used to transfer wafers 500. To further avoid affecting the structural strength of the process chamber 100, the wafer transfer port 140 can be opposite to the detection port 110 corresponding to the third detection element 430. Furthermore, the wafer transfer port 140 and each detection port 110 can be basically spaced apart and evenly distributed along the circumference of the process chamber 100, so as to further avoid affecting the structural strength of the process chamber 100 due to the concentrated arrangement of each detection port 110 and the wafer transfer port 140.

[0022] Optionally, the detection direction of the third detection element 430 intersects with the detection directions of the first detection element 410 and the second detection element 420. For example, the detection direction of the third detection element 430 is perpendicular to the detection directions of the first detection element 410 and the second detection element 420. Specifically, the angle between the line connecting the third detection element 430 and the central axis of the process chamber 100 and the line connecting the first detection element 410 and the central axis of the process chamber 100 is the first angle, and the angle between the line connecting the third detection element 430 and the central axis of the process chamber 100 and the line connecting the second detection element 420 and the central axis of the process chamber 100 is the second angle. The first angle and the second angle can be equal, and both are 90°.

[0023] Therefore, in this embodiment, the first detection element 410, the second detection element 420, and the third detection element 430 are orthogonally arranged in the coordinate system. This arrangement allows the edge displacement of the wafer 500 to exhibit maximum pixel change in the image, thereby maximizing the sensitivity of the detection process. When the wafer 500 is tilted relative to the detection direction of the first detection element 410 and the detection direction of the second detection element 420, the first and second detection elements 410 and 420 can directly obtain the tilt angle of the wafer 500. Similarly, when the wafer 500 is tilted relative to the detection direction of the third detection element 430, the third detection element 430 can directly obtain the tilt angle of the wafer 500. In other words, the orthogonal arrangement of the first detection element 410, the second detection element 420, and the third detection element 430 allows the detection data in the X or Y direction of the coordinate system to be processed independently, obtaining the tilt state of the wafer 500 without coordinate changes. This reduces computation time and improves the real-time control performance of the control device 300. It should be noted that one of the X and Y directions is parallel to the detection direction of the third detection element 430, and the other is parallel to the detection direction of the first detection element 410 and the second detection element 420.

[0024] Alternatively, please refer to Figure 1 , Figure 2 and Figure 4 The semiconductor process equipment may also include a supplementary lighting element 600, and the process chamber 100 may also be provided with a light transmission port 120. The supplementary lighting element 600 faces the light transmission port 120, that is, the supplementary lighting element 600 can provide sufficient light into the process chamber 100 to ensure that the detection element 400 can more accurately collect information from the wafer 500, thereby accurately obtaining the tilt angle of the wafer 500. Of course, in other embodiments, the semiconductor process equipment may not include the supplementary lighting element 600.

[0025] Optionally, the power of the supplementary lighting element 600 can be between 50 and 200W. Of course, the embodiments of this application do not impose specific limitations on this.

[0026] Optionally, in the direction of extension of the central axis of the process chamber 100, the height of the light transmission port 120 may be equal to or less than the height of the detection port 110.

[0027] In another embodiment, the height of the light transmission port 120 is greater than the height of the detection port 110 in the direction of extension of the central axis of the process chamber 100. This can prevent the supplementary lighting element 600 from directly shining light into the detection element 400, so as to avoid affecting the detection result of the detection element 400 due to excessive light-dark ratio. At the same time, the supplementary lighting element 600 can provide supplementary lighting from above the entire wafer 500, which can ensure that the entire process chamber 100 is illuminated.

[0028] Optionally, the process chamber 100 may include at least two sidewalls 130. The detection port 110 and the light transmission port 120 may be respectively disposed on different sidewalls 130. That is, in the circumferential direction of the process chamber 100, the distance between the detection port 110 and the light transmission port 120 is relatively large. This can avoid the structural strength of the process chamber 100 being affected by the concentrated placement of the detection port 110 and the light transmission port 120. In addition, as can be seen from the foregoing, the number of detection ports 110 may be at least three, and the light transmission port 120 and each detection port 110 may be respectively disposed on different sidewalls 130 to further avoid the structural strength of the process chamber 100 being affected by the concentrated placement of the detection ports 110 and the light transmission port 120. Of course, in other embodiments, the detection port 110 and the light transmission port 120 may be disposed on the same sidewall 130.

[0029] Alternatively, please refer to Figure 1 The detection element 400 can be a component capable of directly detecting the tilt angle of the wafer 500. Alternatively, the detection element 400 can be a camera that acquires image information from the wafer 500 and transmits the acquired image information to the control device 300 via high-speed Ethernet. The image processing unit of the control device 300 first performs Gaussian filtering preprocessing on the acquired image information using a Gaussian kernel with δ=1.5 to eliminate noise caused by the flicker of the supplementary lighting element 600 or plasma flicker within the process chamber 100. Optionally, the detection element 400 can be an industrial-grade high-speed CMOS (Complementary Metal Oxide Semiconductor) camera.

[0030] Then, the Canny edge detection algorithm is used to extract the edge information of wafer 500. Under normal conditions, wafer 500 is horizontally arranged, and the angle between its edge, that is, the side of wafer 500, and the horizontal plane should be 90°. As the process progresses, wafer 500 will gradually shift, that is, wafer 500 will tilt. In most cases, after wafer 500 tilts, the angle between its edge and the horizontal plane is basically between 75° and 105°. Therefore, this application can set the constraint range of the Canny edge detection algorithm between 75° and 105° to reduce the computational load of the image processing device and improve the real-time performance of the detection.

[0031] After initially extracting the edge information of the image, an improved Hough transform algorithm is used to enhance the edge information of wafer 500, thereby obtaining the tilt angle of wafer 500. Specifically, the improved Hough transform algorithm uses a probability sampling scheme instead of full-image scanning, voting only on randomly selected edge points of wafer 500 to reduce computation and improve real-time detection. The voting threshold is dynamically adjusted according to the process. For example, when processing wafer 500 in shallow etching, the risk of offset (i.e., tilt risk) is low, so this application can increase the threshold to avoid false alarms; when processing wafer 500 in deep silicon etching, the risk of offset (i.e., tilt risk) is high, so this application can decrease the threshold to improve detection accuracy and reduce the false negative rate. This application can cluster and merge detected line segments, selecting the top three line segments by length as candidate edges, and then calculating the average angle of the candidate edges by length weighting. This setting can suppress noise interference from short line segments.

[0032] Finally, the image processing unit of the control device 300 can perform consistency verification on the average angle calculation results obtained from each detection unit 400, thereby determining the actual tilt angle of the wafer 500 and obtaining the tilt duration of the wafer 500. The image processing unit of the control device 300 can send the actual tilt angle of the wafer 500 to the control unit of the control device 300, so that the control unit of the control device 300 can control the magnitude of the adsorption force of the wafer support 200 on the wafer 500 according to the tilt angle. In addition, the control device 300 can send the tilt angle and tilt duration of the wafer 500 to the display device 700, which can display the current tilt degree and tilt duration of the wafer 500 for the operator to record and observe.

[0033] Optionally, the above algorithm can save 40% of the computing power of the wafer processing unit of the control device 300 and improve the real-time performance of the control device 300 to within 5ms, so that the magnitude of the adsorption force of the wafer support 200 on the wafer 500 can be controlled in a timely manner according to the tilt angle of the wafer 500 at the early stage when the wafer 500 is offset (for example, when the tilt angle of the wafer 500 is greater than 1.5°).

[0034] Optionally, when the detection device 400 is a camera, the frame rate of the detection device 400 can be greater than or equal to 50Hz, and the resolution can be 1920×1080, so as to continuously detect the wafer 500. Of course, the embodiments of this application do not impose specific limitations on this.

[0035] Optionally, to further improve the detection accuracy of the tilt angle of the wafer 500, multiple laser ranging sensors can be evenly arranged on the inner top wall of the process chamber 100, with each laser ranging sensor facing the wafer 500. This allows for the detection of the tilt angle of the wafer 500 by measuring the distance between different positions of the wafer 500 and the inner top wall of the process chamber 100. Optionally, since each laser ranging sensor is located inside the process chamber 100, this embodiment requires radio frequency protection for each laser ranging sensor.

[0036] Optionally, after obtaining the tilt angle of wafer 500, the control device 300 obtains a risk index based on the tilt angle of wafer 500, and controls the magnitude of the adsorption force of wafer support 200 on wafer 500 based on the risk index. Specifically, the control device 300 can obtain the risk index through multi-dimensional parameter fusion and quantitative modeling. The risk index satisfies the following relationship:

[0037] Wherein, RI represents the risk index. The tilt angle is expressed in degrees (°), and t represents the tilt time of wafer 500 in milliseconds (ms). This indicates the temperature fluctuation values ​​in different areas of the wafer support 200, with the unit being ℃ / cm.

[0038] In this embodiment, since the risk index is related to the tilt angle and tilt duration of the wafer 500, as well as the temperature fluctuation values ​​of different areas of the wafer support 200, the risk index can more intuitively reflect the breakage rate of the wafer 500 at the current tilt angle. In other words, the risk index can more accurately and comprehensively determine the risk of the wafer 500 breaking at the current tilt angle. Therefore, the control device 300 can more effectively prevent the wafer 500 from breaking by controlling the magnitude of the adsorption force of the wafer support 200 on the wafer 500 based on the risk index. Of course, in other embodiments, the control device 300 can also directly control the magnitude of the adsorption force of the wafer support 200 on the wafer 500 based on the tilt angle of the wafer 500.

[0039] Optionally, this application can classify the tilt state of wafer 500 according to the magnitude of the risk index. Specifically, the wafer support 200 is usually provided with an adsorption electrode. When the adsorption electrode is energized, it can generate a force to adsorb wafer 500. When the risk index is less than 0.3, the tilt state of wafer 500 can be judged as normal. That is, the tilt angle of wafer 500 corresponding to a risk index of less than 0.3 is small, or even wafer 500 is not tilted. In other words, wafer 500 is not easy to break in this state. Therefore, the semiconductor process equipment disclosed in this application can continue to process wafer 500. During this process, the control device 300 can apply a first voltage to the adsorption electrode so that the wafer support 200 applies a first adsorption force to wafer 500, thereby keeping wafer 500 in the current state.

[0040] In this embodiment, when the risk index is between 0.3 and 0.6, the tilt state of the wafer 500 can be determined as a first-level response state. That is, the tilt angle of the wafer 500 corresponding to the risk index between 0.3 and 0.6 is relatively large, and the wafer 500 is more likely to break in this state. Therefore, this application can enable the control device 300 to apply a second voltage to the adsorption electrode so that the wafer support 200 applies a second adsorption force to the wafer 500. The second voltage is greater than the first voltage, and the second adsorption force is greater than the first adsorption force.

[0041] Therefore, when the tilt state of wafer 500 is determined to be a first-level response state, this application can increase the adsorption force of wafer support 200 on wafer 500 so that the tilt state of wafer 500 can be restored to a normal state. This can prevent wafer 500 from breaking, thereby avoiding economic losses. Of course, in other embodiments, when the risk index is between 0.3 and 0.6, the control device 300 can control wafer support 200 to directly stop applying adsorption force to wafer 500, that is, directly stop the operation of processing wafer 500.

[0042] Optionally, the second voltage can be increased by 10% to 20% relative to the first voltage, that is, the second voltage can be 1.1 to 1.2 times the first voltage. Of course, the embodiments of this application do not impose specific limitations on this.

[0043] Optionally, if the tilt state of wafer 500 is determined to be a first-level response state, the control device 300 can send a first-level alarm signal to the operator through the display device 700 to realize real-time non-contact monitoring and fragment prediction of wafer 500.

[0044] Optionally, during the processing of wafer 500, the bottom of the process chamber 100 supplies heat transfer gas to the back side of wafer 500 and the back side of wafer support 200. After passing through wafer support 200, the heat transfer gas transfers heat from wafer support 200 to wafer 500. If the tilt state of wafer 500 is determined to be a first-level response state, this embodiment can reduce the flow rate of the heat transfer gas to prevent uneven heating and breakage of wafer 500 due to varying distances between different parts of wafer 500 and wafer support 200. Optionally, the heat transfer gas can be helium.

[0045] Therefore, when the tilt state of wafer 500 is determined to be a first-level response state, this application can increase the adsorption force on wafer 500 while reducing the flow rate of heat transfer gas to further prevent wafer 500 from breaking. In this process, the semiconductor process equipment disclosed in this application can continue to process wafer 500 to reduce yield loss and maintenance cycle, and continuously monitor the tilt state of wafer 500.

[0046] Optionally, the wafer support 200 typically has two adsorption electrodes. The wafer support 200 can adsorb the wafer 500 in two modes: unipolar adsorption and bipolar adsorption. In unipolar adsorption, both adsorption electrodes on the wafer support 200 are connected to negative electrodes. In this case, the present application can utilize the adsorption force generated between the positively charged plasma generated in the process chamber 100 and the two negatively charged adsorption electrodes to achieve the effect of adsorbing the wafer 500. In bipolar adsorption, one of the two adsorption electrodes on the wafer support 200 is connected to a positive electrode and the other is connected to a negative electrode. In this case, an adsorption force is generated between the two adsorption electrodes to achieve the effect of adsorbing the wafer 500.

[0047] In this embodiment, the adsorption force generated by the unipolar adsorption mode satisfies the following relationship:

[0048] The adsorption force generated by the bipolar adsorption mode satisfies the following relationship:

[0049] Where Fs represents the adsorption force generated in the unipolar adsorption mode, F d The value represents the adsorption force generated in the bipolar adsorption mode, Q represents the total charge, E represents the electric field strength, ε represents the dielectric constant of the insulating layer between the two adsorption electrodes, A represents the surface charge density, V represents the voltage applied to the two adsorption electrodes, and D represents the distance between the two adsorption electrodes.

[0050] Normally, the wafer support 200 adsorbs the wafer 500 in a bipolar adsorption mode. For example, when the tilt state of the wafer 500 is determined to be a normal state or a first-order response state, the wafer support 200 adsorbs the wafer 500 in a bipolar adsorption mode.

[0051] Optionally, when the risk index is between 0.6 and 0.9, the tilt state of the wafer 500 can be determined as a second-order response state. That is, the tilt angle of the wafer 500 corresponding to the risk index between 0.6 and 0.9 is larger, and the wafer 500 is more likely to break in this state. Therefore, this application can make the control device 300 apply negative pressure to the adsorption electrode so that the wafer support 200 applies a third adsorption force to the wafer 500, and the third adsorption force is greater than the second adsorption force.

[0052] In this embodiment, because the control device 300 applies negative pressure to the adsorption electrodes, meaning both adsorption electrodes on the wafer support 200 are connected to the negative terminal, the adsorption mode of the wafer support 200 on the wafer 500 switches from a bipolar adsorption mode to a unipolar adsorption mode. At this time, the adsorption force on the wafer 500 is four times that in the bipolar adsorption mode. This configuration can significantly increase the adsorption force of the wafer support 200 on the wafer 500, making it easier for the wafer 500 to return to its normal state. Of course, in other embodiments, when the risk index is between 0.6 and 0.9, the adsorption mode of the wafer support 200 on the wafer 500 can still be a bipolar adsorption mode, and the control device 300 can apply a third voltage to the adsorption electrodes, where the third voltage is greater than the second voltage.

[0053] Optionally, after the wafer support 200 switches the adsorption mode of the wafer 500 from bipolar adsorption mode to unipolar adsorption mode, if the risk index decreases to 0.4 or below within a preset time, this application can continue to maintain the unipolar adsorption mode to adsorb the wafer 500 and continue to complete the wafer 500 processing operation, so as to maximize the continuity of wafer 500 processing and reduce economic losses. Optionally, the preset time can be 50ms; of course, this application embodiment does not specifically limit this.

[0054] Optionally, if the tilt state of wafer 500 is determined to be a level two response state, the control device 300 can send a level two alarm signal to the operator through the display device 700 to realize real-time non-contact monitoring and fragment prediction of wafer 500.

[0055] Optionally, when the risk index is greater than 0.9, the tilt state of the wafer 500 can be determined as a level three response state, that is, the tilt angle of the wafer 500 corresponding to the risk index being greater than 0.9 further increases. At this time, the wafer 500 is on the verge of breaking. Therefore, this application can enable the control device 300 to control the wafer support 200 to stop applying adsorption force to the wafer 500. In other words, this application can make the adsorption electrodes on the wafer support 200 uncharged to avoid damage to various parts of the process chamber 100 caused by the breakage of the wafer 500, thereby shortening the maintenance time of the semiconductor process equipment. That is, this setting method can protect the semiconductor process equipment in extreme cases.

[0056] Furthermore, when the risk index is greater than 0.9, this application can also stop the processing of wafer 500. Specifically, the power of the radio frequency power supply used to generate plasma in the process chamber 100 can be reduced to zero, and the flow of process gas into the process chamber 100 can be stopped. Then, purge gas is immediately used to purge the residual process gas and process byproducts from the process chamber 100. Finally, wafer 500 can be lifted and transferred outside the process chamber 100. During this process, the control device 300 can display a three-level alarm signal to the operator via the display device 700 to alert the operator. Of course, in other embodiments, when the risk index is greater than 0.9, this application can further increase the adsorption force of the wafer support 200 on the wafer 500 to restore the wafer 500 to its normal state.

[0057] Optionally, if the wafer support 200 fails to switch the adsorption mode of the wafer 500 from bipolar adsorption mode to unipolar adsorption mode when the tilt state of the wafer 500 is determined to be a level two response state, the operation corresponding to the tilt state of the wafer 500 being determined to be a level three response state will be executed to further prevent the wafer 500 from breaking due to the continued increase in the tilt angle.

[0058] Optionally, if the tilt state of the wafer 500 is determined to be a level two response state, and the bipolar adsorption mode is successfully switched to a unipolar adsorption mode, and if the risk index does not decrease to 0.4 or below within the preset time, the adsorption mode of the wafer support 200 on the wafer 500 can first be switched from a unipolar adsorption mode to a bipolar adsorption mode. Then, the operation corresponding to the tilt state of the wafer 500 being determined to be a level three response state is executed to avoid the wafer 500 from "flying up" due to uncontrolled force in the process chamber 100 and breaking because the adsorption electrodes on the wafer support 200 are de-energized.

[0059] Optionally, this application can reduce the fragmentation rate of wafer 500 from 3% in the traditional solution to below 0.3% through the above method, saving more than RMB 2 million per year for a single semiconductor process equipment (calculated based on a unit price of RMB 5,000 for a 12-inch wafer 500). At the same time, it can shorten the cleaning downtime of process chamber 100 caused by fragmentation, thereby increasing the capacity of semiconductor process equipment by 12%.

[0060] The above embodiments of this application focus on describing the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be described in detail here.

[0061] The above description is merely an embodiment of this application and is not intended to limit the scope of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of the claims of this application.

Claims

1. A semiconductor process apparatus, characterized in that, It includes a process chamber (100), a wafer support (200), a control device (300), and a testing component (400); The process chamber (100) is provided with a detection port (110), the wafer support (200) is disposed in the process chamber (100), the detection element (400) is disposed opposite to the detection port (110), and the detection element (400) is used to detect the tilt angle of the wafer (500) through the detection port (110). The control device (300) is connected to the detection element (400) to control the magnitude of the adsorption force of the wafer support (200) on the wafer (500) according to the tilt angle.

2. The semiconductor process equipment according to claim 1, characterized in that, The wafer support (200) has a wafer support surface (210), and in the detection direction of the detection element (400), the detection center of the detection element (400) is flush with the wafer support surface (210).

3. The semiconductor process equipment according to claim 1, characterized in that, The process chamber (100) is provided with at least three detection ports (110), and each detection port (110) is arranged at circumferential intervals along the process chamber (100). Each detection port (110) corresponds to at least one detection element (400).

4. The semiconductor process equipment according to claim 3, characterized in that, The semiconductor process equipment includes at least three detection elements (400), including a first detection element (410), a second detection element (420) and a third detection element (430). The first detection element (410) and the second detection element (420) are arranged opposite to each other and their detection directions are parallel. The detection direction of the third detection element (430) intersects with the detection directions of the first detection element (410) and the second detection element (420).

5. The semiconductor process equipment according to claim 1, characterized in that, The semiconductor process equipment also includes a light-enhancing component (600), and the process chamber (100) is also provided with a light transmission port (120), with the light-enhancing component (600) facing the light transmission port (120).

6. The semiconductor process equipment according to claim 5, characterized in that, In the direction of extension of the central axis of the process chamber (100), the height of the light transmission port (120) is greater than the height of the detection port (110).

7. The semiconductor process equipment according to claim 5, characterized in that, The process chamber (100) includes at least two side walls (130), and the detection port (110) and the light transmission port (120) are respectively disposed on different side walls (130).

8. The semiconductor process equipment according to claim 1, characterized in that, The control device (300) is used to obtain a risk index based on the tilt angle, and to control the magnitude of the adsorption force of the wafer support (200) on the wafer (500) based on the risk index. The risk index satisfies the following relationship: Wherein, RI represents the risk index. The tilt angle is expressed in degrees (°), and t represents the tilt duration of the wafer (500) in milliseconds (ms). The temperature fluctuation values ​​of different regions of the wafer support (200) are expressed in °C / cm.

9. The semiconductor process equipment according to claim 8, characterized in that, The wafer support (200) is provided with an adsorption electrode. When the risk index is less than 0.3, the control device (300) applies a first voltage to the adsorption electrode so that the wafer support (200) applies a first adsorption force to the wafer (500). When the risk index is between 0.3 and 0.6, the control device (300) applies a second voltage to the adsorption electrode so that the wafer support (200) applies a second adsorption force to the wafer (500), wherein the second voltage is greater than the first voltage and the second adsorption force is greater than the first adsorption force.

10. The semiconductor process equipment according to claim 9, characterized in that, When the risk index is between 0.6 and 0.9, the control device (300) applies a negative pressure to the adsorption electrode so that the wafer support (200) applies a third adsorption force to the wafer (500), the third adsorption force being greater than the second adsorption force.

11. The semiconductor process equipment according to claim 9, characterized in that, If the risk index is greater than 0.9, the control device (300) controls the wafer support (200) to stop applying adsorption force to the wafer (500).

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