Semiconductor structure

Abstract

A semiconductor structure includes: an interconnect structure over a semiconductor substrate and having a top metal feature; a liner over the interconnect structure; and an extended conductive line having a proximal end electrically connected to the liner and extending to a distal end, wherein the extended conductive line includes: a proximal portion extending in a first direction; and a non-proximal portion extending in a second direction transverse to the first direction, and wherein the extended conductive line is electrically connected to the top metal feature.

Description

Technical Field

[0001] This disclosure relates to a semiconductor structure, and more particularly to a semiconductor structure with conductive lines having a crack-reducing geometry. Background Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing an insulating or dielectric layer, a conductive layer, and a semiconductor material layer on a semiconductor substrate; and patterning each material layer using photolithography and etching processes to form circuit components and elements on these material layers.

[0003] The semiconductor industry continues to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by constantly shrinking the minimum feature size, which allows more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise in each process used, and these additional problems must be addressed. Utility Model Content

[0004] According to some embodiments disclosed herein, a semiconductor structure is provided. The semiconductor structure includes an interconnect structure, a pad, and an extended conductive line. The interconnect structure is located above a semiconductor substrate and has a top metal feature. The pad is located above the interconnect structure. The extended conductive line has a proximal end electrically connected to the pad and extending to a distal end. The extended conductive line includes a proximal end portion and a non-proximal end portion. The proximal end portion extends along a first direction. The non-proximal end portion extends along a second direction transverse to the first direction, and wherein the extended conductive line is electrically connected to the top metal feature.

[0005] According to some embodiments disclosed herein, a semiconductor structure is provided. The semiconductor structure includes an interconnect structure, a first pad, a plurality of first extended conductive lines, a second pad, and a plurality of second extended conductive lines. The interconnect structure is located above a semiconductor substrate and has a plurality of top metal features. The first pad is located above the interconnect structure. The plurality of first extended conductive lines have a plurality of proximal ends electrically connected to the first pad and extending to a plurality of distal ends. The second pad is located above the interconnect structure. The plurality of second extended conductive lines have a plurality of proximal ends electrically connected to the second pad and extending to a plurality of distal ends. The first and second extended conductive lines are interleaved. Adjacent first and second extended conductive lines are spaced apart from each other by a first distance at their proximal ends. At least one of adjacent first and second extended conductive lines is non-linear, such that the non-proximal portions of the first and second extended conductive lines are spaced apart by a second distance, the second distance being different from the first distance.

[0006] According to some embodiments disclosed herein, a semiconductor structure is provided. The semiconductor structure includes an interconnect structure, a pad, and an extended conductive line. The interconnect structure is located above a semiconductor substrate and has a top metal feature. The pad is located above the interconnect structure. The extended conductive line has a proximal end electrically connected to the pad and extending to a distal end. The extended conductive line includes a proximal portion, an intermediate portion, and a terminal portion. The proximal portion extends along a first direction. The intermediate portion extends along a second direction transverse to the first direction. The terminal portion is connected to the intermediate portion and extends along the first direction and is aligned with the proximal portion. Attached Figure Description

[0007] The various aspects of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, in accordance with industry standard practice, the features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the features may be arbitrarily increased or decreased.

[0008] Figures 1 to 10 A cross-sectional view illustrating the intermediate processing steps for forming semiconductor grains according to an embodiment;

[0009] Figure 11 A top view of a pad having a main body and an extended connecting line with a non-linear geometry according to an embodiment of this article;

[0010] Figure 12 According to the embodiments herein Figure 11 Top view of the extended connecting lines;

[0011] Figure 13 A top view of a pad having a main body and an extended connecting line with a non-linear geometry according to an embodiment of this article;

[0012] Figure 14 This is a top view of two adjacent pads according to an embodiment of the present invention, wherein each pad has a body and an extended connecting line of non-linear geometry, and the extended connecting line is intersecting.

[0013] Figure 15 A focal top view of adjacent extended connecting lines having nonlinear geometry from two adjacent pads, according to an embodiment of this article;

[0014] Figure 16 and Figure 17 According to the embodiments herein Figure 15 A cross-sectional view of the device;

[0015] Figures 18 to 20 This is a top view of two adjacent pads according to an embodiment of the present invention, wherein each pad has a body and an extending connecting line, and the extending connecting lines are intersecting.

[0016] Figure 21 According to the embodiments herein Figure 20 Top view of the extended connecting lines;

[0017] Figures 22 to 33 This is a top view of two adjacent pads according to an embodiment of the present invention, wherein each pad has a body and an extending connecting line, and the extending connecting lines are intersecting.

[0018] Figure 34 A flowchart illustrating a method for manufacturing a semiconductor structure according to embodiments herein.

[0019] [Symbol Explanation]

[0020] 16-16, 17-17: Line

[0021] 99: Probe

[0022] 100: Grain

[0023] 101:Substrate

[0024] 103: Active device

[0025] 105: Interconnection Structure

[0026] 107: Electrical conductivity characteristics

[0027] 109: Dielectric layer

[0028] 111: Top metal layer

[0029] 113: Passivation layer

[0030] 115: Redistribution Through Hole

[0031] 115', 1220', 2220': Position

[0032] 200: Padding

[0033] 201: Main Body

[0034] 205: End face

[0035] 208: Contact surface / top surface

[0036] 220: Extension cable

[0037] 221: First sidewall / sidewall

[0038] 222: Second sidewall / sidewall

[0039] 224: Proximal / End Wall

[0040] 225: Terminal / Remote / Endwall

[0041] 230: Continuous bottom surface

[0042] 250: floors

[0043] 255: First Opening

[0044] 260: First photoresist

[0045] 270: Second photoresist

[0046] 275: Second opening

[0047] 280: Third photoresist

[0048] 281: Third opening

[0049] 283: Fourth opening

[0050] 300: Proximal linear portion

[0051] 301, 503, 701: Long sidewalls

[0052] 303, 501, 703: Short sidewalls

[0053] 310, 510, 710: Rectangular Polygons

[0054] 330, 720: Triangles and polygons

[0055] 400: Proximal transition section

[0056] 500: Intermediate linear portion

[0057] 520: Near-end triangle polygon

[0058] 530: Distant triangle polygon

[0059] 600: Remote Transition Section

[0060] 700: Terminal Linear Section

[0061] 801: Seed Crystal Layer

[0062] 803: Sheet Metal

[0063] 900: Grain

[0064] 901, 1001: First solder pad

[0065] 903, 1003: Second solder pad

[0066] 1000: Encapsulated Components

[0067] 1005: Dielectric layer

[0068] 1200, 2200: Padding

[0069] 1205, 2205: End face

[0070] 1220, 2220: Extension cable / connector

[0071] 1224, 2224: End wall

[0072] 1225, 2225: Terminal

[0073] 3011, 3031, 5011: Plane

[0074] 3400: Method

[0075] Blocks 3402, 3404, 3406, 3408, and 3410

[0076] D1, D7, D8: Direction

[0077] D2, D3, D4, D5: Distance / Width / Length

[0078] D6: Parallel length / distance Detailed Implementation

[0079] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements described below are used to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0080] Furthermore, for ease of description, spatial relative terms such as “above,” “overlapping,” “above,” “upper,” “top,” “top,” “below,” “submerged,” “below,” “under,” “lower,” “bottom,” “side,” etc., may be used herein to describe the relationship between one element or feature and another illustrated in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0081] Furthermore, when using terms such as "about," "approximately," etc., to describe a number or range of numbers, this term is intended to encompass a reasonable range of numbers that take into account variations inherent in manufacturing, as understood by one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with the characteristics of a manufacturing process having properties related to this number, a number or range of numbers encompasses a reasonable range including said number, such as within + / - 10% of said number. For example, a material layer with a thickness of "about 5 nm" may encompass a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerances associated with the deposited material layer are known to one of ordinary skill in the art to be + / - 15%. Additionally, element symbols and / or letters may be repeated in various instances in this disclosure. Such repetition is for simplicity and clarity and does not determine the relationship between the various embodiments and / or configurations discussed.

[0082] In some embodiments herein, a “material structure” is a structure comprising at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of an identified material; and a structure formed from the “material” comprises at least 50% by weight of an identified material, such as at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of an identified material. For example, in some embodiments, each of the tungsten structure and the structure formed from tungsten is at least 50% by weight, at least 60% by weight, at least 75% by weight, at least 90% by weight, at least 95% by weight, or at least 99% by weight of a tungsten structure.

[0083] For the sake of brevity, this document may not describe in detail the conventional techniques associated with the manufacture of conventional semiconductor devices. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive procedures or processes with additional functionalities not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known; therefore, for the sake of brevity, many processes will be mentioned only briefly or omitted entirely without providing well-known process details. Those skilled in the art will readily understand upon fully reading this disclosure that the structures disclosed herein can be used with a variety of techniques and incorporated into a variety of semiconductor devices and products. Furthermore, it should be noted that semiconductor device structures include varying numbers of components, and a single component shown in the description may represent multiple components.

[0084] This document describes embodiments of semiconductor devices and methods for manufacturing them. This disclosure relates more specifically to the interconnect structures of integrated circuit devices. The methods described herein can be easily integrated into current process flows.

[0085] The device structures shown in the figures of this disclosure are simplified and do not describe or elaborate on all features of the device structure. The device structures shown in the figures may be part of an IC chip, a system-on-a-chip (SoC), or a portion thereof, and may include various passive and active microelectronic devices, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor (CMOS) transistors, bipolar junction transistors (BJTs), laterally diffused MOS (LDMOS) transistors, high-voltage transistors, high-frequency transistors, other suitable components, or combinations thereof.

[0086] The embodiments described herein provide extension lines from an aluminum bushing that are selectively twisted or bent to reduce stresses that could lead to cracking. Some embodiments provide adjustable parallel lengths and spacing of the selectively twisted extension lines. Some embodiments provide an adjustable number of interconnects between redistributed vias and the twisted extension lines.

[0087] Figure 1 The illustration shows a side view of the die 100, including substrate 101. Substrate 101 may be a bulk silicon substrate, although other semiconductor materials, including those of Group III, IV, and V elements, may also be used. Active devices 103 (such as transistors) may be formed in and / or on substrate 101. For example, active devices may be two-dimensional planar devices, three-dimensional FinFET devices, and / or three-dimensional gate-all-around (GAA) devices.

[0088] An interconnect structure 105 is formed over a substrate 101. In some embodiments, the interconnect structure 105 may include at least one dielectric layer formed of a low-k dielectric material having a k-value (e.g., below about 4.0). In some embodiments, the dielectric layer of the interconnect structure 105 may be made of, for example, silicon oxide, SiCOH, etc. As shown, the interconnect structure 105 includes metal lines and metal vias (i.e., connections) formed in the dielectric layer. For example, the interconnect structure 105 may include multiple metal layers interconnected vias. The metal lines and vias may be formed of copper or a copper alloy, or other metals. The metal lines and vias may be formed by etching openings in the dielectric layer, filling the openings with a conductive material, and performing planarization (such as CMP) to make the top surface of the metal lines and vias flush with the top surface of the dielectric layer.

[0089] A top metal layer 111 is formed over the interconnect structure 105. The top metal layer 111 includes a dielectric layer 109 and conductive features 107. The top metal layer 111 is formed by depositing the dielectric layer 109 on the top surface of the interconnect structure 105. The dielectric layer 109 can be deposited using chemical vapor deposition (CVD), physical vapor deposition (PVD), or the like. The dielectric layer may contain the same material as the dielectric layer of the interconnect structure 105. For example, in some embodiments, the dielectric layer 109 may be made of silicon oxide, SiCOH, or the like.

[0090] The dielectric layer 109 can then be etched to form openings on the top surface of the exposed interconnect structure 105. Conductive features 107 can be deposited in the openings, for example, by an electroplating process. The conductive features 107 can then be planarized by a process such as chemical mechanical polishing (CMP). The conductive features 107 can be made of copper or a copper alloy. Other materials such as aluminum or aluminum alloys can also be used to form the conductive features 107. Figure 1 As shown, the conductive feature 107 can be a discrete feature. For example, the conductive feature 107 can be separated and electrically isolated from each other by the dielectric layer 109. According to other embodiments, the conductive feature 107 can be a portion of a continuous metallic feature.

[0091] A passivation layer 113 may be formed over the top metal layer 111. In embodiments, the passivation layer 113 may be polybenzoxazole (PBO), although any suitable material may also be used, such as benzocyclobutene (BCB), polyimide, or a polyimide derivative. The passivation layer 113 may be placed using, for example, a spin-coating process, although any suitable method may also be used.

[0092] A redistributed via 115 can be formed in the passivation layer 113. For example, the passivation layer 113 can be patterned to form openings, exposing one of the conductive features 107 through the openings. The passivation layer 113 can be patterned using photolithography. The redistributed via 115 can then be formed in the openings of the passivation layer 113. The redistributed via 115 can be made of aluminum, aluminum alloy, copper, or copper alloy, although other metallic materials can also be used.

[0093] Figure 2 The formation of pad 200 is explained. Pad 200 is formed above and in contact with redistribution via 115. Pad 200 is electrically coupled to active device 103 via conductive features (such as metal wires and vias formed in interconnect structure 105, conductive feature 107, and redistribution via 115). Pad 200 may be formed of aluminum or an aluminum alloy, although other metallic materials may also be used. Pad 200 may be formed by a blanket deposition process. For example, an aluminum layer may be deposited on the surface of passivation layer 113 and redistribution via 115 using CVD, PVD, etc. A photoresist layer (not described separately) may then be formed over the aluminum layer, and the aluminum layer may be etched to form pad 200.

[0094] like Figure 2 As shown, the gasket 200 may be composed of a body 201 and an extending connecting line 220. The gasket 200 has an upper contact surface 208 formed by the body 201. Although Figure 2 The main body 201 and the extension connecting line 220 are integrally formed and share a continuous bottom surface 230. However, in other embodiments, the extension connecting line 220 may be formed at a lower level, while the main body 201 may be formed above the extension connecting line 220. As shown, the main body 201 has an end face 205, and the extension connecting line 220 extends from the end face 205 of the main body 201 to a terminal 225. In some embodiments, the main body 201 is not located directly above the redistribution via 115, while the extension connecting line 220 extends to a position directly above the redistribution via 115. In this way, the gasket 200 can be formed to be electrically connected to a selected redistribution via 115 without positioning the main body 201 and the top surface 208 directly above the redistribution via 115.

[0095] According to at least one embodiment, the pad 200 and the redistributed via 115 can be formed simultaneously. For example, a passivation layer 113 can be formed over the top metal layer 111 and patterned to expose one of the conductive features 107. The pad 200 and the redistributed via 115 can be formed by blanket deposition. For example, an aluminum layer can be deposited on the surface of the passivation layer 113, in the openings formed in the passivation layer 113, and on the exposed conductive features 107 using CVD, PVD, etc. A photoresist layer (not described separately) can then be formed over the aluminum layer, and the aluminum layer can be etched to form the pad 200.

[0096] Figure 3 The probing procedure is described, and may be part of a wafer acceptance test or circuit test. Probing is performed to verify the functionality of the active device 103 and its corresponding electrical connections (e.g., connections in interconnect structure 105, conductive features 107, and redistribution vias 115). Probing can be performed by contacting the contact surface 208 of the pad 200 with probe 99. Probe 99 may be part of a probe card with multiple probes, for example, a probe card connected to test equipment (not described separately). If die 100 passes the wafer acceptance test, the die is a known good die (KGD).

[0097] Figure 4 The formation of layer 250 is described. Layer 250 may be a passivation layer. Layer 250 may be a bonding layer. Layer 250 is deposited above the top surface of passivation layer 113 and above the top surface and sides of pad 200. Layer 250 may be used for fusion bonding (also known as oxide-oxide bonding). According to some embodiments, layer 250 is formed of a silicon-containing dielectric material (such as silicon oxide, silicon nitride, etc.). Layer 250 may be deposited using any suitable method, such as CVD, high-density plasmachemical vapor deposition (HDPCVD), PVD, atomic layer deposition (ALD), etc. For example, layer 250 may be planarized in a chemical mechanical polishing (CMP) process. The top surface of layer 250 is higher than the top surface of pad 200. Layer 250 may be referred to as a passivation layer or a dielectric layer.

[0098] Figure 5 The first opening 255 is formed in layer 250 to expose the pad 200. A first photoresist 260 is applied to and patterned on the top surface of layer 250. Layer 250 is then etched using the first photoresist 260 to form the first opening 255. Layer 250 can be etched by dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, etc. According to some embodiments of this disclosure, the etching terminates on the pad 200, such that the pad 200 is exposed via the first opening 255 in layer 250.

[0099] Figure 6The description describes forming a second opening 275 in layer 250 and passivation layer 113 to expose conductive feature 107. A second photoresist 270 is applied to the top surface of layer 250 and pad 200 and in the first opening 255, and the second photoresist 270 is patterned. Then, layer 250 and passivation layer 113 are etched using the second photoresist 270 and one or more etching methods to form the second opening 275. The etching used to form the second opening 275 may be the same as or different from the etching used to form the first opening 255, and may include dry etching (e.g., RIE or NBE), wet etching, etc. According to some embodiments of this disclosure, the etching terminates on conductive feature 107, such that conductive feature 107 is exposed via the second opening 275 in layer 250 and passivation layer 113.

[0100] Figure 7 Optionally, a third opening 281 and a fourth opening 283 are formed in layer 250 to widen portions of the first opening 255 and the second opening 275, respectively. A third photoresist 280 is applied to the top surface of layer 250, the pad 200, and the conductive feature 107, and in the first opening 255 and the second opening 275. The third photoresist 280 is patterned and then used to etch layer 250 to form the third opening 281 and the fourth opening 283. Layer 250 can be etched by dry etching (e.g., RIE or NBE), wet etching, etc. The third opening 281 may be formed above the first opening 255 and the pad 200. The fourth opening 283 may be formed above the second opening 275 and the conductive feature 107.

[0101] Figure 8 The first opening 255, the second opening 275, the third opening 281, and the fourth opening 283 are filled with a seed layer 801 and plate metal 803. The seed layer 801 can be deposited as a blanket on the top surface of layer 250, pad 200, and conductive feature 107, and on the sidewalls of the first opening 255, the second opening 275, the third opening 281, and the fourth opening 283. The seed layer 801 may contain a copper layer. The seed layer 801 can be deposited using processes such as sputtering, evaporation, or plasma-enhanced chemical vapor deposition (PECVD), depending on the desired material. The plate metal 803 can be deposited on the seed layer 801 via an electroplating process (such as electroplating or electroless plating). The plate metal 803 may contain copper, copper alloys, etc. The plate metal 803 can be a filler material. Before the seed layer 801, a barrier layer (not described separately) may be deposited on the top surface of layer 250, pad 200, and conductive feature 107, as well as on the sidewalls of the first opening 255, second opening 275, third opening 281, and fourth opening 283. The barrier layer may contain titanium, titanium nitride, tantalum, tantalum nitride, etc.

[0102] Figure 9 The description includes the grain 900 of the first pad 901 and the second pad 903. In the filler... Figure 8 After the first opening 255, second opening 275, third opening 281, and fourth opening 283 shown, a planarization process, such as CMP, is performed to remove excess conductive material from the seed layer 801 and the plate metal 803, thereby forming the first pad 901 and the second pad 903. The first pad 901 may contact the pad 200, while the second pad 903 may contact the conductive feature 107. According to at least one embodiment, the top surfaces of the first pad 901 and the second pad 903 are coplanar with each other and with the top surface of the layer 250. The top portion of the first pad 901 fills the third opening 281 and may be referred to as pad metal. The top portion of the second pad 903 fills the fourth opening 283 and may also be referred to as pad metal. The lower portion of the first pad 901 fills the first opening 255 and may be referred to as a pad via. The lower portion of the second pad 903 fills the second opening 275 and may also be referred to as a pad via.

[0103] Figure 10 This is a cross-sectional view illustrating the processing steps of bonding die 900 to package assembly 1000. According to some embodiments of this disclosure, package assembly 1000 is a device die, an interposer die, a package substrate, or a package. According to an embodiment, package assembly 1000 may be a device die, which is a mirror image of die 900. Package assembly 1000 includes a first bonding pad 1001, a second bonding pad 1003, and a dielectric layer 1005. The first bonding pad 1001 may be similar to the first bonding pad 901, the second bonding pad 1003 may be similar to the second bonding pad 903, and the dielectric layer 1005 may be similar to layer 250. For example, the top surface of dielectric layer 1005 is coplanar with the top surfaces of the first bonding pad 1001 and the second bonding pad 1003. The first bonding pad 1001 and the second bonding pad 1003 may contain a conductive material, such as copper, a copper alloy, etc. The dielectric layer 1005 may include a silicon-containing dielectric layer, such as a silicon oxide layer or a silicon nitride layer.

[0104] In some embodiments, die 900 is bonded to package assembly 1000 by, for example, hybrid bonding. After planarization of the top surfaces of die 900 and package assembly 1000, the top surfaces of die 900 and package assembly 1000 may be activated. Activation of the top surfaces of die 900 and package assembly 1000 may include dry processing, wet processing, plasma processing, exposure to an inert gas, exposure to H2, exposure to N2, exposure to O2, or combinations thereof, as examples. In embodiments using wet processing, RCA cleaning may be used, for example. In another embodiment, the activation process may include other types of processing. The activation process facilitates hybrid bonding of die 900 and package assembly 1000; advantageously, it allows for the use of lower pressures and temperatures in subsequent hybrid bonding processes.

[0105] Following the activation process, chemical rinsing can be used to clean the die 900 and the package assembly 1000. The wafer assembly is then subjected to heat treatment and contact pressure to hybrid bond the die 900 to the package assembly 1000. The die 900 and package assembly 1000 can withstand pressures of about 200 kPa or less and temperatures between about 200°C and about 400°C to fuse layer 250 and dielectric layer 1005. The die 900 and package assembly 1000 can then withstand temperatures at or above the eutectic point of the materials of the first solder pad 901, the second solder pad 903, and the first solder pad 1001 and the second solder pad 1003, for example, between about 150°C and about 650°C, to fuse the metal solder pads. In this manner, the fusion of the die 900 and the package assembly 1000 forms a hybrid bonding device. In some embodiments, the bonded die is baked, annealed, pressed, or otherwise treated to strengthen or complete the bonding.

[0106] In other embodiments, die 900 may be bonded to package assembly 1000 via direct surface bonding, metal-to-metal bonding, or other bonding processes. Direct surface bonding involves cleaning and / or surface activation processes followed by applying pressure, heat, and / or other bonding process steps to the bonding surfaces to form an oxide-oxide bond or substrate-to-substrate bond. In some embodiments, die 900 and package assembly 1000 are bonded via metal-to-metal bonding, which is achieved by fusing conductive elements. For example, first pad 1001 and second pad 1003 are bonded to first pad 901 and second pad 903, respectively, via metal-to-metal bonding.

[0107] Forming a first solder pad 901 that contacts the backing pad 200 can increase the number of connections that can be made with the active device 103 in the die 900. Furthermore, the first solder pad 901 that contacts the backing pad 200 can increase the pin-out area of ​​devices excluding the first solder pad 901. For example, the pin-out area of ​​the die 900 can be approximately 30% or more than that of a conventional die, which is approximately 3,000 pins to approximately 700 pins.

[0108] It has been discovered that, according to Figures 1 to 10 During the formation of semiconductor grain 900, cracks may occur near long extension lines 220, such as between adjacent extension lines 220 parallel to the conductive features 107 of the top metal layer 111.

[0109] The embodiments described herein can reduce or eliminate such cracks by providing an extended connecting line 220 with a non-linear geometry.

[0110] See Figure 11 This displays a pad 200 with a main body 201 and an extension connecting line 220. Figure 11In the middle, the extension connecting line 220 has a non-linear geometry. Figure 11 This is a top view, illustrating the top metallic conductive feature 107 located below the nonlinear extension connecting line 220.

[0111] like Figure 11 As shown, the extension connecting line 220 extends along direction D1 from the proximal end 224 adjacent to the end face 205 of the body 201 to the terminal end 225. In some embodiments, direction D1 is perpendicular to the end face 205 and perpendicular to the terminal end 225. The extension connecting line 220 has a first sidewall 221 and an opposing second sidewall 222.

[0112] The underlying redistribution via 115 shows the conductive feature 107 of the top metal beneath the electrical connection and the nonlinear extension connection line 220. Unused redistribution via locations 115' are indicated by dashed lines.

[0113] Figure 12 As a key focus Figure 11 Top view of the non-linear extension connecting line 220.

[0114] exist Figure 12 In this design, the nonlinear extension connector 220 is considered to comprise several parts. Specifically, the nonlinear extension connector 220 includes a proximal linear portion 300, an intermediate linear portion 500, and a terminal linear portion 700. The proximal linear portion 300 is connected to the intermediate linear portion 500 via a proximal transition portion 400. The intermediate linear portion 500 is connected to the terminal linear portion 700 via a distal transition portion 600. Although the proximal linear portion 300, the proximal transition portion 400, the intermediate linear portion 500, the distal transition portion 600, and the terminal linear portion 700 are described as separate geometric elements, they are structurally integrated, i.e., a single unit.

[0115] As shown in the figure, the proximal linear portion 300 is formed by a rectangular polygon 310 and a triangular polygon 330. Therefore, the proximal linear portion 300 has a long sidewall 301 and a short sidewall 303 interconnected by an end wall 224. As shown in the figure, the long sidewall 301 is longer than the short sidewall 303 in direction D1. The rectangular polygon 310 forms the proximal end 224 and extends along direction D1 to the interface with the triangular polygon 330.

[0116] As shown in the figure, the intermediate linear portion 500 is formed by a rectangular polygon 510, a near-end triangular polygon 520, and a far-end triangular polygon 530. Therefore, the intermediate linear portion 500 has short sidewalls 501 and long sidewalls 503. As shown in the figure, the long sidewall 503 is longer than the short sidewall 501 in direction D1. The rectangular polygon 510 forms an interface with the near-end triangular polygon 520 and extends along direction D1 to the interface with the far-end triangular polygon 530.

[0117] As shown in the figure, the terminal linear portion 700 is formed by a rectangular polygon 710 and a triangular polygon 720. Therefore, the terminal linear portion 700 has a long sidewall 701 and a short sidewall 703. As shown in the figure, the long sidewall 701 is longer than the short sidewall 703 in direction D1. The rectangular polygon 710 forms the distal end 225. As shown in the figure, the rectangular polygon 710 extends from the interface with the triangular polygon 720 to the distal end 225 in direction D1.

[0118] As shown in the figure, the proximal transition portion 400 interconnects the triangular polygon 330 and the proximal triangular polygon 520. Furthermore, the distal transition portion 600 interconnects the distal triangular polygon 530 and the triangular polygon 720.

[0119] The rectangular polygon 310 may have a width D2, measured along a direction perpendicular to direction D1. In other words, the end wall 224 may have a length D2, and the long side wall 301 may be separated from the short side wall 303 by a distance D2. For example, the long side wall 301 may define a plane 3011 and be coplanar with plane 3011, and the short side wall 303 may define a plane 3031 and be coplanar with plane 3031. As shown, the distance D2 between plane 3031 and plane 3011 is measured along a direction perpendicular to direction D1.

[0120] As further shown, the short sidewall 501 defines plane 5011 and is coplanar with plane 5011. As shown in the figure, plane 5011 is separated from plane 3011 by a distance D3, measured along a direction perpendicular to direction D1.

[0121] In the illustrated embodiment, distance D3 is greater than distance D2. For example, distance D3 may be at least 101% of distance D2, such as at least 102%, at least 103%, at least 104%, at least 105%, at least 106%, at least 107%, at least 108%, at least 109%, at least 110%, at least 115%, at least 120%, at least 125%, at least 130%, at least 135%, at least 140%, at least 145%, at least 150%, at least 155%, at least 160%, at least 165%, at least 170%, at least 175%, at least 180%, at least 185%, at least 190%, at least 195%, at least 200%, at least 220%, at least 240%, at least 260%, at least 280%, or at least 300% of distance D2. Furthermore, distance D3 can be up to 101% of distance D2, for example, up to 102%, up to 103%, up to 104%, up to 105%, up to 106%, up to 107%, up to 108%, up to 109%, up to 110%, up to 115%, up to 120%, up to 125%, up to 130%, up to 135%, up to 140%, up to 145%, up to 150%, up to 155%, up to 160%, up to 165%, up to 170%, up to 175%, up to 180%, up to 185%, up to 190%, up to 195%, up to 200%, up to 220%, up to 240%, up to 260%, up to 280%, or up to 300% of distance D2.

[0122] In other embodiments, distance D2 is equal to distance D3.

[0123] In other embodiments, distance D2 is greater than distance D3. For example, distance D2 may be at least 101% of distance D3, such as at least 102%, at least 103%, at least 104%, at least 105%, at least 106%, at least 107%, at least 108%, at least 109%, at least 110%, at least 115%, at least 120%, at least 125%, at least 130%, at least 135%, at least 140%, at least 145%, at least 150%, at least 155%, at least 160%, at least 165%, at least 170%, at least 175%, at least 180%, at least 185%, at least 190%, at least 195%, at least 200%, at least 220%, at least 240%, at least 260%, at least 280%, or at least 300% of distance D3. Furthermore, distance D2 can be up to 101% of D3, such as up to 102%, up to 103%, up to 104%, up to 105%, up to 106%, up to 107%, up to 108%, up to 109%, up to 110%, up to 115%, up to 120%, up to 125%, up to 130%, up to 135%, up to 140%, up to 145%, up to 150%, up to 155%, up to 160%, up to 165%, up to 170%, up to 175%, up to 180%, up to 185%, up to 190%, up to 195%, up to 200%, up to 220%, up to 240%, up to 260%, up to 280%, or up to 300% of distance D3.

[0124] As shown in the figure, the distance between the proximal wall 224 and the distal wall 225 in direction D1 is D4. Distance D4 is greater than distance D2. For example, the D2:D4 ratio can be at least 1:30, such as at least 1:25, at least 1:20, at least 1:18, at least 1:15, at least 1:12, at least 1:10, at least 1:9, at least 1:8, at least 1:6, at least 1:5, or at least 1:4. The D2:D4 ratio can be at most 1:30, such as at most 1:25, at most 1:20, at most 1:18, at most 1:15, at most 1:12, at most 1:10, at most 1:9, at most 1:8, at most 1:6, at most 1:5, or at most 1:4.

[0125] Figure 13 The gasket 200 may include more than one extension connecting line 220. For example, the gasket 200 includes three extension connecting lines 220. The gasket 200 may include any desired number of extension connecting lines 220. Figure 13 In the middle, the three extended connecting lines 220 each have a non-linear geometry. In fact, in Figure 13In this configuration, the three extended connecting lines 220 each have the same nonlinear geometry. However, the pad 200 can be formed with both linear and nonlinear extended connecting lines 220. Furthermore, the pad 200 can be formed with nonlinear extended connecting lines 220 that have different geometries or shapes. Figure 13 In this configuration, each extended connecting line 220 is located directly above the corresponding top metal conductive feature 107 and is electrically connected through the corresponding redistributed via 115.

[0126] Figure 14 The following describes two pads 1200 and 2200 constructed according to the pad 200 described above. As shown in the figure, pads 1200 and 2200 are adjacent to each other and have extending connecting lines 1220 and 2220 extending toward each other. The extending connecting lines 1220 and 2220 are staggered such that connecting lines 1220 / 2220 from the other pad 1200 / pad 2200 are located between each pair of adjacent connecting lines 2220 / 1220 of pad 2200 / pad 1200.

[0127] Figure 15 illustrate Figure 14 Part of the device. Specifically, two adjacent extension connecting lines 1220 and 2220 are described. As shown, in a direction perpendicular to direction D1, each pair of adjacent extension connecting lines 1220 and 2220 are separated by a distance D5 from sidewall 222 to sidewall 221.

[0128] Figure 16 for Figure 15 A cross-sectional view of the device, along Figure 15 Intercepted by line 16-16 perpendicular to direction D1. As shown in the figure, in Figure 16 In the middle, the extension connecting line 1220 moves laterally relative to the position 1220' of the extension connecting line 1220 at the end wall 1224, toward the extension connecting line 2220. The extension connecting line 2220 does not move laterally.

[0129] Figure 17 for Figure 15 A cross-sectional view of the device, along Figure 15 Intercepted at line 17-17 perpendicular to direction D1. For example... Figure 17 As shown, the extension connecting line 1220 moves laterally relative to its position 1220' at end wall 1224, toward the extension connecting line 2220. Furthermore, the extension connecting line 2220 moves laterally relative to its position 2220' at end wall 2224, away from the extension connecting line 1220.

[0130] Cross-reference Figures 15 to 17The distance D5 between adjacent sidewalls 221 and 222 varies along the length of the extension connecting line 1220 and the extension connecting line 2220 in the direction D1.

[0131] Figures 18 to 33 Various designs of other embodiments are described, wherein the extension connecting lines 1220 and 2220 of adjacent pads 1200 and 2200 are formed with non-linear geometry.

[0132] For example, in Figure 18 In this configuration, each extension connection line 1220 and extension connection line 2220 is electrically connected to two corresponding redistributed vias 115. More specifically, each extension connection line 1220 and extension connection line 2220 is electrically connected to a corresponding redistributed via 115 adjacent to the proximal end 224 and to a corresponding redistributed via 115 adjacent to the terminal 225. Of the four extension connection lines 1220 and extension connection lines 2220 described, there are connections to eight redistributed vias 115.

[0133] exist Figure 19 In the middle, the extension connecting line 1220 has a connection with Figure 18 A similar structure exists, but the extension connection line 2220 is linear. Among the four extension connection lines 1220 and 2220 described, there are connections to sixteen redistributed vias 115.

[0134] exist Figure 20 In the middle, the extension connecting line 2220 has the same as... Figure 18 A similar structure exists, but the extension connection line 1220 is linear. Among the four extension connection lines 1220 and 2220 described, there are connections to sixteen redistributed vias 115.

[0135] Figure 21 for Figure 20 A focal view of the extension connecting line 1220 and extension connecting line 2220 of the embodiment is shown. As shown, the extension connecting line 2220 has a parallel length equal to a distance D6, a thickness equal to a distance D2, and a line spacing equal to a distance D5. As described above, the line spacing varies along the length of the extension connecting line 2220.

[0136] Figure 22 An embodiment with linear extension connection line 1220, nonlinear extension connection line 1220, linear extension connection line 2220, and nonlinear extension connection line 2220 is described. Among the four extension connection lines 1220 and 2220 described, there are connections to sixteen redistributed vias 115.

[0137] Figure 23An embodiment with nonlinear extension connection line 1220, linear extension connection line 2220, and nonlinear extension connection line 2220 is described. Among the four extension connection lines 1220 and 2220 described, there are connections to twelve redistributed vias 115.

[0138] exist Figure 24 In this configuration, both extension connecting lines 1220 and 2220 have non-linear geometries. Furthermore, each extension connecting line 1220 and 2220 includes connections to three corresponding redistributed vias 115. Of the four extension connecting lines 1220 and 2220 described, there are connections to twelve redistributed vias 115.

[0139] exist Figure 25 In this configuration, both extension connecting lines 1220 and 2220 have non-linear geometries. Furthermore, each extension connecting line 1220 and 2220 includes connections to four corresponding redistributed vias 115. Of the four described extension connecting lines 1220 and 2220, there are connections to sixteen redistributed vias 115.

[0140] exist Figure 26 In this configuration, both extension connecting lines 1220 and 2220 have non-linear geometries. Furthermore, each extension connecting line 1220 and 2220 includes connections to four corresponding redistributed vias 115. Of the four described extension connecting lines 1220 and 2220, there are connections to sixteen redistributed vias 115.

[0141] exist Figure 27 In this configuration, extension connecting lines 1220 and 2220 both have non-linear geometries. Furthermore, each extension connecting line 1220 and 2220 includes connections to four corresponding redistributed vias 115. Of the four extension connecting lines 1220 and 2220 described, there are connections to sixteen redistributed vias 115.

[0142] exist Figure 27 In this configuration, extension connecting line 1220 bends along direction D7, while extension connecting line 2220 bends along direction D8. In other words, adjacent pairs of extension connecting lines 1220 and 2220 bend towards each other.

[0143] exist Figure 28 In this configuration, both extension connecting lines 1220 and 2220 have non-linear geometries. Furthermore, each extension connecting line 1220 and 2220 includes connections to three corresponding redistributed vias 115. Figure 28In this configuration, the redistribution vias 115 are connected near the proximal end 224, with each end remaining disconnected. Among the four extended connecting lines 1220 and 2220 described, there are connections to the twelve redistribution vias 115.

[0144] Figure 29 Explanation and Figure 28 Similar embodiments, but in which adjacent pairs of extended connecting lines 1220 and 2220 bend toward each other (similar to...). Figure 27 In addition, in Figure 29 In this configuration, extension connection line 1220 includes connections to three corresponding redistribution vias 115, while extension connection line 2220 includes connections to four corresponding redistribution vias 115. In the four extension connection lines 1220 and 2220 described, there are connections to fourteen redistribution vias 115.

[0145] Figure 30 The description is similar to Figure 29 The embodiment includes an extension connection line 1220 that includes connections to four corresponding redistribution vias 115, and an extension connection line 2220 that includes connections to three corresponding redistribution vias 115. Of the four extension connection lines 1220 and 2220 described, there are connections to fourteen redistribution vias 115.

[0146] exist Figure 31 In this context, both extension connecting line 1220 and extension connecting line 2220 have non-linear geometric shapes. Figure 31 In the middle, adjacent pairs of extended connecting lines 1220 and 2220 bend toward each other (similar to...). Figure 27 Furthermore, each extension connection line 1220 and extension connection line 2220 includes a connection to four corresponding redistribution vias 115. Of the four extension connection lines 1220 and 2220 described, there are connections to sixteen redistribution vias 115.

[0147] exist Figure 32 In this configuration, extension connection line 1220 is linear, while extension connection line 2220 is non-linear. Each extension connection line 1220 is electrically connected to six redistribution vias 115, and each extension connection line 2220 is electrically connected to three redistribution vias 115. Of the four extension connection lines 1220 and 2220 described, there are connections to eighteen redistribution vias 115.

[0148] exist Figure 33In this configuration, extension connection line 1220 is linear, while extension connection line 2220 is non-linear. Each extension connection line 1220 is electrically connected to six redistributed vias 115, and each extension connection line 2220 is electrically connected to four redistributed vias 115. Among the four extension connection lines 1220 and 2220 described, there are connections to twenty redistributed vias 115.

[0149] Various embodiments include an extension connecting line that connects to a redistributed through-hole 115 adjacent to the proximal end 224 and to a redistributed through-hole 115 adjacent to the distal end 225, thereby forming a closed bend, i.e., the middle portion of the extension connecting line is not aligned with the underlying top metal feature. Other embodiments include an extension connecting line that connects to a redistributed through-hole 115 adjacent to the proximal end 224 and is not connected to a redistributed through-hole 115 adjacent to the distal end 225, thereby forming an open bend, i.e., the terminal portion of the extension connecting line is not aligned with the underlying top metal feature.

[0150] Although certain structural designs have been illustrated and described above in conjunction with various accompanying drawings, it should be noted that any design feature in one embodiment may be used in another embodiment. For example, an extension connecting line illustrated in one embodiment may be combined with an extension connecting line illustrated in another embodiment.

[0151] Furthermore, the extension connectors can be designed to have any suitable geometry and any suitable number of connections with redistributed vias as needed.

[0152] Cross-reference Figure 12 and Figures 18 to 33 It should be noted that the length of the long sidewall 301 can be selected to determine the number of redistributed vias, and the proximal linear portion 300 can be located directly above the redistributed vias and electrically connected to them. Similarly, in an embodiment where the terminal linear portion 700 is located directly above the redistributed vias, the length of the long sidewall 701 can be selected to determine the number of redistributed vias, and the terminal linear portion 700 can be located directly above the redistributed vias and electrically connected to them.

[0153] In some embodiments, the parallel length D6 is 45 μm and the distance D5 is 2.25 μm. In some embodiments, the parallel length D6 is 60 μm and the distance D5 is 3 μm. In some embodiments, the parallel length D6 is 90 μm and the distance D5 is 4.5 μm. In some embodiments, the parallel length D6 is 5000 μm and the distance D5 is 250 μm.

[0154] In some embodiments, the parallel length D6 may be at least 20 μm, such as at least 30 μm, at least 40 μm, at least 45 μm, at least 50 μm, at least 60 μm, at least 70 μm, at least 80 μm, at least 90 μm, at least 100 μm, at least 200 μm, at least 500 μm, at least 1000 μm, at least 2000 μm, at least 3000 μm, at least 4000 μm, or at least 5000 μm. Furthermore, the parallel length D6 may be at most 20 μm, such as at most 30 μm, at most 40 μm, at most 45 μm, at most 50 μm, at most 60 μm, at most 70 μm, at most 80 μm, at most 90 μm, at most 100 μm, at most 200 μm, at most 500 μm, at most 1000 μm, at most 2000 μm, at most 3000 μm, at most 4000 μm, or at most 5000 μm.

[0155] In some embodiments, the parallel length D6 may be at least 1 μm, such as at least 1.5 μm, at least 1.75 μm, at least 2 μm, at least 2.25 μm, at least 2.5 μm, at least 2.75 μm, at least 3 μm, at least 3.25 μm, at least 3.5 μm, at least 3.75 μm, at least 4 μm, at least 4.25 μm, at least 4.5 μm, at least 4.75 μm, at least 5 μm, at least 6 μm, at least 7 μm, at least 8 μm, at least 9 μm, at least 10 μm, at least 25 μm, at least 50 μm, at least 100 μm, at least 150 μm, at least 200 μm, at least 250 μm, or at least 300 μm. In some embodiments, the parallel length D6 may be at most 1 μm, such as at most 1.5 μm, at most 1.75 μm, at most 2 μm, at most 2.25 μm, at most 2.5 μm, at most 2.75 μm, at most 3 μm, at most 3.25 μm, at most 3.5 μm, at most 3.75 μm, at most 4 μm, at most 4.25 μm, at most 4.5 μm, at most 4.75 μm, at most 5 μm, at most 6 μm, at most 7 μm, at most 8 μm, at most 9 μm, at most 10 μm, at most 25 μm, at most 50 μm, at most 100 μm, at most 150 μm, at most 200 μm, at most 250 μm, or at most 300 μm.

[0156] In some embodiments, the distance D5 is at least 5% of the parallel length D6, for example, at least 10%, at least 15%, at least 20%, at least 25%, at least 33%, or at least 50% of the parallel length D6. In some embodiments, the distance D5 is at most 5% of the parallel length D6, for example, at most 10%, at most 15%, at most 20%, at most 25%, at most 33%, or at most 50% of the parallel length D6.

[0157] Figure 34This is a flowchart illustrating a method 3400 for manufacturing an apparatus. At block 3402, method 3400 includes the step of determining the length of extended conductive lines of one or more pads.

[0158] At block 3404, method 3400 includes the following steps: determining the spacing between adjacent extended conductive lines.

[0159] At block 3406, method 3400 includes the following steps: determining the number of via connections between each extended conductive line and the underlying top metal feature via redistribution vias.

[0160] At block 3408, method 3400 includes the following steps: designing the geometry of each extended conductive line, including linear and non-linear geometries.

[0161] At block 3410, method 3400 includes the following steps: manufacturing an apparatus for extending conductive wires having a designed geometry.

[0162] In one embodiment, a semiconductor structure includes: an interconnect structure located above a semiconductor substrate and having a top metal feature; a pad located above the interconnect structure; and an extended conductive line having a proximal end electrically connected to the pad and extending to a distal end, wherein the extended conductive line includes: a proximal portion extending along a first direction; and a non-proximal portion extending along a second direction transverse to the first direction, wherein the extended conductive line is electrically connected to the top metal feature.

[0163] In some embodiments of the semiconductor structure, the extended conductive lines are integrated with the pads.

[0164] In some embodiments of the semiconductor structure, extended conductive lines are electrically connected to a top metal feature via redistributed vias.

[0165] In some embodiments of the semiconductor structure, extended conductive lines are electrically connected to a top metal feature through a selected number of redistributed vias.

[0166] In some embodiments of the semiconductor structure, the non-proximal end is divided into an intermediate portion; the extended conductive line further includes a terminal portion connected to the intermediate portion; and the terminal portion extends along a first direction and is aligned with the proximal end portion.

[0167] In some embodiments of the semiconductor structure, the proximal portion of the extended conductive line is electrically connected to a top metal feature through a selected number of redistributed vias.

[0168] In some embodiments of the semiconductor structure, the terminal portions of the extended conductive lines are electrically connected to a top metal feature via a selected number of redistributed vias.

[0169] In another embodiment, a semiconductor structure includes: an interconnect structure located above a semiconductor substrate and having a top metal feature; a first pad located above the interconnect structure; a first extended conductive line having a proximal end electrically connected to the first pad and extending to a distal end; a second pad located above the interconnect structure; and a second extended conductive line having a proximal end electrically connected to the second pad and extending to a distal end; wherein the first extended conductive line and the second extended conductive line are interleaved, wherein adjacent first extended conductive lines and second extended conductive lines are spaced apart from each other by a first distance at their proximal ends; and wherein at least one of the adjacent first extended conductive lines and second extended conductive lines is non-linear, such that the non-proximal portions of the first extended conductive lines and second extended conductive lines are spaced apart by a second distance, the second distance being different from the first distance.

[0170] In some embodiments of the semiconductor structure, adjacent first and second extended conductive lines bend toward each other.

[0171] In some embodiments of the semiconductor structure, adjacent first and second extended conductive lines are bent away from each other.

[0172] In some embodiments of the semiconductor structure, adjacent first extended conductive lines have: a linear proximal portion extending along a first direction; and a non-proximal portion extending along a second direction transverse to the first direction.

[0173] In some embodiments of the semiconductor structure, adjacent first extended conductive lines have linear distal portions that extend along a first direction and are collinear with the proximal portions.

[0174] In some embodiments of the semiconductor structure, the proximal portion of each extended conductive line is electrically connected to a corresponding top metal feature via a selected number of redistributed vias.

[0175] In some embodiments of the semiconductor structure, the linear distal portion of each extended conductive line is electrically connected to a corresponding top metal feature via a selected number of redistributed vias.

[0176] In some embodiments of the semiconductor structure, each extended conductive line is electrically connected to a corresponding top metal feature through at least one redistribution via.

[0177] In some embodiments of the semiconductor structure, each extended conductive line is electrically connected to a corresponding top metal feature through a selected number of redistributed vias.

[0178] In another embodiment, a semiconductor structure is provided. The semiconductor structure includes an interconnect structure, a pad, and an extended conductive line. The interconnect structure is located above a semiconductor substrate and has a top metal feature. The pad is located above the interconnect structure. The extended conductive line has a proximal end electrically connected to the pad and extending to a distal end. The semiconductor structure includes a proximal portion, a middle portion, and a terminal portion. The proximal portion extends along a first direction. The middle portion extends along a second direction laterally to the first direction. The terminal portion is connected to the middle portion, extends along the first direction, and is aligned with the proximal portion. In some embodiments, the proximal portion of the extended conductive line is electrically connected to the top metal feature through a selected number of redistributed vias.

[0179] In another embodiment, a method for manufacturing a semiconductor structure is provided, comprising the steps of: determining the length of an extended conductive line for interconnecting pads to redistributed vias; determining an initial spacing between the extended conductive lines; determining the number of via connections from each extended conductive line to a corresponding redistributed via; designing the geometry of each extended conductive line to provide a desired spacing between non-proximal portions of the extended conductive lines; and manufacturing a semiconductor structure including extended conductive lines having the designed geometry and desired spacing, wherein at least one extended conductive line has a non-linear geometry.

[0180] In some embodiments of the method, the pads include a first pad and a second pad; the extended conductive lines include: a first extended conductive line for interconnecting the first pads to a first redistribution via; and a second extended conductive line for interconnecting the second pads to a second redistribution via; and an initial spacing between adjacent first and second extended conductive lines.

[0181] In some embodiments of the method, the first pad and the second pad are electrically connected.

[0182] In some embodiments of the method, it is desirable that the spacing be at least 5% of the length.

[0183] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of this disclosure.

Claims

1. A semiconductor structure, characterized in that, Include: An interconnect structure located above a semiconductor substrate and having a top metal feature; A pad is located above the interconnect structure; and An extended conductive wire having a proximal end electrically connected to the pad and extending to a distal end, wherein the extended conductive wire includes: a proximal portion extending along a first direction; and a non-proximal portion extending in a second direction transverse to the first direction, wherein the extended conductive line is electrically connected to the top metal feature.

2. The semiconductor structure as described in claim 1, characterized in that, The extended conductive line is integrated with the pad.

3. The semiconductor structure as described in claim 1, characterized in that, The extended conductive line is electrically connected to the top metal feature through a redistributed via.

4. The semiconductor structure as described in claim 1, characterized in that, The extended conductive line is electrically connected to the top metal feature through a selected number of redistributed vias.

5. A semiconductor structure, characterized in that, Include: An interconnect structure located above a semiconductor substrate and having multiple top metal features; A first pad is located above the interconnect structure; Multiple first extended conductive lines having multiple proximal ends electrically connected to the first pad and extending to multiple distal ends; A second pad is located above the interconnect structure; and Multiple second extended conductive lines having multiple proximal ends electrically connected to the second pad and extending to multiple distal ends; The plurality of first extended conductive lines and the plurality of second extended conductive lines are interleaved. The adjacent first and second extended conductive lines are spaced apart by a first distance at the plurality of proximal ends; and At least one of the adjacent first and second extended conductive lines is non-linear, such that the non-proximal portions of the first and second extended conductive lines are spaced apart by a second distance, which is different from the first distance.

6. The semiconductor structure as described in claim 5, characterized in that, The adjacent first and second extended conductive lines bend toward each other.

7. The semiconductor structure as described in claim 5, characterized in that, The adjacent first and second extended conductive lines bend away from each other.

8. The semiconductor structure as described in claim 5, characterized in that, The adjacent first extended conductive line has: a linear proximal portion extending along a first direction; and a non-proximal portion extending along a second direction transverse to the first direction.

9. A semiconductor structure, characterized in that, Include: An interconnect structure located above a semiconductor substrate and having a top metal feature; A pad is located above the interconnect structure; and An extended conductive wire having a proximal end electrically connected to the pad and extending to a distal end, wherein the extended conductive wire includes: A proximal portion, extending along a first direction; A middle portion, extending along a second direction transverse to the first direction; and A terminal portion is connected to the intermediate portion, the terminal portion extending along the first direction and aligned with the proximal portion.

10. The semiconductor structure of claim 9, wherein the proximal portion of the extended conductive line is electrically connected to the top metal feature via a selected number of redistributed vias.

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