A power module top heat dissipation packaging structure

Abstract

The utility model provides a kind of power module top heat dissipation packaging structure, is set by substrate reverse side copper foil, and shell is only formed in the front of substrate, so that the reverse side of substrate is directly exposed to module top, form continuous, low resistance top heat dissipation surface, multiple power chips are arranged according to the circuit topology structure corresponding to power module on the front side of substrate, avoid cross bridge arm jumper and multilayer wiring, greatly simplify wiring complexity and reduce occupied area, at the same time, form shorter heat dissipation path between top heat dissipation surface, by top exposed metal as public heat dissipation substrate, directly transfer the heat generated by chip to external radiator, shorten heat conduction path, greatly reduce the conduction thermal resistance, solve the temperature equalization problem between multiple chips.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging applications, specifically to a top heat dissipation packaging structure for a power module. Background Technology

[0002] As electronic devices evolve towards higher power density and miniaturization, heat dissipation issues in power semiconductor devices are becoming increasingly prominent. Traditional heat dissipation methods for power semiconductor devices primarily employ a bottom-level heat dissipation path, where heat is transferred from the chip through the solder layer, substrate, solder layer again, PCB, and TIM material before finally reaching the heat sink. This heat dissipation path is relatively long, and the low thermal conductivity of the PCB severely impacts heat transfer efficiency, leading to overheating problems in high-power applications.

[0003] In the field of power module packaging, CN119403204A proposes a multi-layer heat dissipation packaging structure with chip stacking. This structure achieves multi-layer heat dissipation through upper and lower single-sided copper-clad laminates and a middle copper-layer circuit board. While this shortens the heat dissipation path, the structure is complex and requires advanced manufacturing processes. Regarding temperature monitoring, CN104241209A discloses a dedicated power module for outdoor power supplies, integrating a thermistor for temperature monitoring. However, this module is primarily designed for outdoor power applications and is not specifically tailored to the specific needs of three-phase full-bridge circuits. In terms of power module integration, CN219499196U discloses a hermetically sealed power module suitable for high-frequency and low-temperature applications. This module integrates the three-phase inverter bridge circuit, optimizes the commutation loop layout, and uses Kelvin connections to reduce common-source inductance. However, this module uses a metal hermetically sealed package, resulting in high cost and failing to adequately address the heat dissipation efficiency issue.

[0004] Due to the inefficiency, complex wiring, and large area occupied by traditional bottom heat dissipation paths, there is an urgent need for a top heat dissipation packaging structure for power modules that can effectively solve the above problems, thereby improving heat dissipation efficiency, enabling temperature monitoring, enhancing system integration, ensuring three-phase current balance, and reducing system costs. Utility Model Content

[0005] To address the problems of insufficient efficiency, complex wiring, and large footprint of traditional bottom heat dissipation paths in existing technologies, this invention provides a top heat dissipation packaging structure for power modules. By integrating multiple chips into a single package, the system integration is improved. Furthermore, by using copper plating on the reverse side of the substrate and forming the outer shell only on the front side of the substrate, the reverse side of the substrate is directly exposed to the top of the module, forming a continuous, low-resistance top heat dissipation surface. Multiple power chips are arranged on the front side of the substrate according to the circuit topology corresponding to the power module, avoiding bridge arm jumpers and multi-layer wiring, significantly simplifying wiring complexity and reducing footprint. Simultaneously, a shorter heat dissipation path is formed between the chip and the top heat dissipation surface. Using the exposed metal on top as a common heat dissipation substrate, the heat generated by the chips is directly transferred to the external heat sink, shortening the heat conduction path, greatly reducing thermal resistance, and solving the problem of temperature uniformity among multiple chips.

[0006] The objective of this utility model is achieved through the following solution: This utility model provides a top heat dissipation packaging structure for a power module, which includes at least: a substrate, multiple power chips, pin components, and a housing; The multiple power chips are arranged on the front side of the substrate according to the circuit topology corresponding to the power module. The circuit topology is used for the electrical interconnection of the multiple power chips to realize the corresponding functions of the power module. The reverse side of the substrate is provided with a copper-clad layer for heat dissipation and conduction at the top; The power chip is connected to the pin assembly and is located on the front side of the substrate; the pin assembly is used to connect to the PCB. The outer shell is formed on the front side of the substrate.

[0007] Preferably, the power module includes a three-phase full-bridge MOS module, and the circuit topology includes at least a plurality of base islands disposed on the front side of the substrate, the plurality of base islands including an upper bridge base island and three lower bridge base islands; the upper bridge base island and the three lower bridge base islands are respectively connected to a plurality of pins of the pin assembly; The upper bridge base island and the three lower bridge base islands are distributed vertically, and the pin assemblies are led out from the upper bridge base island and the lower bridge base island respectively, and are arranged on both sides.

[0008] Preferably, it also includes a thermistor and a temperature detection circuit topology distributed on the front side of the substrate. The thermistor and temperature detection circuit topology are located at the edge of the substrate and on the same side of the three lower bridge base islands, wherein the thermistor is close to the upper bridge base island.

[0009] Preferably, the three-phase full-bridge MOS module includes three upper-bridge power chips and three lower-bridge power chips. The three upper-bridge power chips are integrally mounted on the upper-bridge base island, and the three lower-bridge power chips are respectively mounted on the three lower-bridge base islands.

[0010] Preferably, the lead assembly includes: a power supply pin, an output pin, a control pin, a sampling pin, and a temperature detection pin; The upper bridge base island and the three lower bridge base islands are respectively connected to control pins; The power supply pins, output pins, and control pins connected to the upper bridge base island are arranged in an array on the upper bridge side; The output pins, temperature detection pins, and control pins connected to the lower bridge base island are arranged in an array on the lower bridge side.

[0011] Preferably, the pins of the pin assembly are made of copper alloy.

[0012] Preferably, the substrate is an alumina ceramic substrate with a thickness between 0.38 mm and 0.8 mm and a thermal conductivity between 24 W / (m·K) and 30 W / (m·K).

[0013] Preferably, a thermally conductive layer is provided between the substrate and the power chip, the thermally conductive layer having a thickness of 0.2 mm to 0.5 mm and a thermal conductivity of not less than 3 W / (m·K).

[0014] Preferably, the top heat dissipation surface of the substrate, which has a copper-clad layer, is bonded to an external heat sink through a thermally conductive material to form a heat conduction path.

[0015] Preferably, the thermal conductivity of the thermally conductive material is 3W / (m·K) to 15W / (m·K), and the thickness is 0.05mm to 0.2mm.

[0016] Compared with the prior art, the present invention has the following beneficial effects: By using copper plating on the reverse side of the substrate and forming the outer shell only on the front side of the substrate, the reverse side of the substrate is directly exposed to the top of the module, forming a continuous, low-resistance top heat dissipation surface. By using the exposed metal on the top as a common heat dissipation substrate, the heat generated by the chip is directly transferred to the external heat sink, shortening the heat conduction path, greatly reducing the thermal resistance, and solving the problem of temperature uniformity among multiple chips. By arranging multiple power chips on the front side of the substrate according to the circuit topology corresponding to the power module, the bridge arm jumpers and multi-layer traces are avoided, greatly simplifying the wiring complexity and reducing the occupied area, while forming a shorter heat dissipation path between the chip and the top heat dissipation surface. The bidirectional pin arrangement design allows for a more balanced current flow, reducing the likelihood of electromagnetic field concentration and thus lowering electromagnetic interference. This design significantly improves signal integrity, especially for high-speed signal transmission. It integrates a thermistor, which can monitor temperature changes in real time, thereby achieving over-temperature protection. It supports double-sided PCB layout, optimizes PCB space, and systematically increases power density; Practical alumina ceramic substrates offer lower costs while maintaining equivalent performance, making them suitable for large-scale industrial production. Attached Figure Description

[0017] The embodiments of this utility model will be further described below with reference to the accompanying drawings: Figure 1 Overall structural diagram provided for embodiments of this utility model; Figure 2 The front view of the top heat dissipation module provided in this embodiment of the utility model; Figure 3 The back of the heat dissipation module provided in this embodiment of the utility model; Figure 4 The side of the top heat dissipation module provided in this embodiment of the utility model; Figure 5 The internal structure of the top heat dissipation module provided in this embodiment of the utility model; Figure 6 A circuit topology diagram of the top heat dissipation module provided for an embodiment of this utility model; Figure 7 This is a conventional packaging heat dissipation path provided in the embodiments of this utility model; Figure 8 This is a schematic diagram of heat dissipation at the bottom of a conventional package provided in an embodiment of the present invention; Figure 9 The improved heat dissipation path for the packaging provided in this embodiment of the utility model; Figure 10 A schematic diagram of the improved package heat dissipation provided for an embodiment of this utility model.

[0018] In the above figures: 1. Substrate; 11. Distributed copper plating layer; 111. Upper bridge first base island; 112. Lower bridge first base island; 113. Lower bridge second base island; 14. Lower bridge third base island; 12. Integral copper plating layer; 2. Housing; 3. Pin assembly; 4. Heat sink; 5. Thermal grease; 6. Thermistor. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the scope of the present utility model.

[0020] Example 1 The first aspect of this embodiment provides a top heat dissipation packaging structure for a power module, such as... Figures 1-5Includes: substrate 1, power chip, thermistor 6, pin assembly 3 and housing 2; Multiple power chips are arranged on the front side of substrate 1 according to the circuit topology corresponding to the power module. The circuit topology is used for the electrical interconnection of multiple power chips to realize the corresponding functions of the power module. A copper-clad layer is provided on the reverse side of substrate 1 for heat dissipation conduction at the top; The conductive pattern of the power chip is connected to the pin assembly 3 and is located on the front side of the substrate; the pin assembly 3 is used to connect to the PCB. The outer shell 2 is formed on the front side of the substrate 1.

[0021] In this embodiment, the back of the substrate 1 is copper-clad, and the outer shell is formed only on the front of the substrate, so that the back of the substrate is directly exposed to the top of the module, forming a continuous, low-resistance top heat dissipation surface. This directly transfers the heat generated by the chip to the external heat sink, shortens the heat conduction path, greatly reduces the conduction thermal resistance, and solves the problem of temperature uniformity among multiple chips. By arranging multiple power chips on the front side of the substrate according to the circuit topology corresponding to the power module, the bridge arm jumpers and multi-layer traces are avoided, greatly simplifying the wiring complexity and reducing the occupied area. At the same time, a shorter heat dissipation path is formed between the chip and the top heat dissipation surface.

[0022] Specifically, in this embodiment, the side of the substrate 1 where the power chip is disposed is defined as the front side. The front side of the substrate 1 is a distributed copper plating layer 11, and the back side of the substrate 11 is an integral copper plating layer 12. The integral copper plating layer 12 is exposed outside the housing 2 and forms a top heat dissipation surface that can be directly attached to the external heat sink 4.

[0023] The power module includes a three-phase full-bridge MOS module. The circuit topology includes at least multiple base islands disposed on the front side of substrate 1. The circuit topology also includes bonding wires for direct functional connection of the base islands. The multiple base islands include an upper bridge base island and three lower bridge base islands. The upper bridge base island includes an upper first base island 111. The three lower bridge base islands include a lower first base island 112, a lower second base island 113, and a lower third base island 114. The upper bridge base island and the three lower bridge base islands are respectively connected to multiple pins of the pin assembly 3. The three-phase full-bridge MOS module includes three upper bridge power chips Q4 to Q6 and three lower bridge power chips Q1 to Q3. The three upper bridge power chips Q4 to Q6 are mounted as a whole on the upper bridge base island, and the three lower bridge power chips Q1 to Q3 are respectively mounted on the three lower bridge base islands, specifically, the lower bridge power chips Q1 to Q3 are mounted on the lower first base island 112, the lower second base island 113, and the lower third base island 114. The upper bridge base island and three lower bridge base islands are arranged vertically, with pin assemblies 3 extending from both the upper and lower bridge base islands and arranged on both sides. The pins are arranged in a bidirectional manner, meaning pins are located on both sides of the module body, forming a symmetrical arrangement. This bidirectional arrangement facilitates application and installation and improves wiring flexibility.

[0024] Pin assembly 3 forms an electrical connection with the upper-bridge power chips Q4-Q6 and the lower-bridge power chips Q1-Q3. Pin assembly 3 includes a power supply pin VDD, output pins S1-S3, control pins G1-G6, sampling pins S4-S6, and temperature control pins T1-T2. The pin assembly 3 is arranged as follows: the power supply pin VDD, the gate control pins G4 / G5 / G6 connected to the upper-bridge power chips Q4-Q6, and the sampling pins S4-S6 connected to the upper-bridge power chips Q4-Q6 are located on the upper side of the upper bridge base island; the temperature control pins T1-T2 connected to the thermistor 6, the gate control pins G1 / G2 / G3 connected to the lower-bridge power chips Q1-Q3, and the output pins S1 / S2 / S3 connected to the lower-bridge power chips Q1-Q3 are located on the lower side of the lower bridge base island. The pins are arranged bidirectionally, reducing the number of pins on one side, allowing for a corresponding reduction in module width, effectively reducing module size, shortening trace distance, and facilitating wiring. During module operation, the electromagnetic fields generated by the internal power chips will interfere with each other. The bidirectional pin arrangement design allows for a more balanced current flow, reducing the likelihood of electromagnetic field concentration and thus lowering electromagnetic interference. This design significantly improves signal integrity, especially for high-speed signal transmission.

[0025] The power supply pin VDD serves as the main current path for the module, responsible for transferring power from the external power supply to the load. Output pins S1-S3 drive the load by outputting pulsed voltages modulated by the bridge arms. Control pins include gate control pins G1-G6, which control the conduction and shutdown of the internal channels of the upper-bridge power chips Q4-Q6 and the lower-bridge power chips Q1-Q3, and temperature control pins T1-T2, which connect to thermistor 6. When the junction temperature exceeds the threshold, temperature control pins T1-T2 output a low level, triggering the external control circuit to turn off the gate signal, preventing the MOSFET from overheating and burning out. Sampling pins S4-S6 are Kelvin source pins, separating the drive signal and power current path through independent source pins, avoiding power circuit interference, ensuring gate control accuracy, and significantly improving current detection accuracy and switching performance. The upper-bridge power chips Q4-Q6 constitute the upper bridge of the three-phase full-bridge circuit, and the lower-bridge power chips Q1-Q3 constitute the lower bridge of the three-phase full-bridge circuit. The upper-bridge power chips Q4-Q6 and the lower-bridge power chips Q1-Q3 are connected by bonding wires. The upper-bridge power chips Q4-Q6 and the lower-bridge power chips Q1-Q3 are also connected to pin assembly 3 by bonding wires. The bonding wires can be made of aluminum wire, copper wire, gold wire, aluminum strip, or copper sheet. The connection method between the power chips and the pins is as follows: the drains of the upper-bridge power chips Q4-Q6 are soldered to the first base island 111 of the upper bridge, which is connected to the power supply pin VDD; the drains of the lower-bridge power chips Q1-Q3 are soldered to the first base island 112, the second base island 113, and the third base island 114 of the lower bridge, respectively. The gates of the upper-bridge power chips Q4-Q6 are thermo-ultrasonically bonded to control pins G4-G6 using bonding wires. The gates of the lower-bridge power chips Q1-Q3 are thermo-ultrasonically bonded to control pins G1-G3 using bonding wires. The sources of the upper-bridge power chips Q4-Q6 are thermo-ultrasonically bonded to the lower-bridge third base island 114 / lower-bridge second base island 113 / lower-bridge first base island 112, which are connected to the drains of the lower-bridge power chips Q1-Q3, using bonding wires. The sources of the upper-bridge power chips Q4-Q6 are bonded to the corresponding sampling pins S4-S6 using bonding wires. The sources of the lower-bridge power chips Q1-Q3 are bonded to the corresponding output pins S1-S3 using bonding wires. Figure 6 As shown, Q6 of the upper bridge power chips Q4 to Q6 and Q1 of the lower bridge power chips Q1 to Q3 form a U-phase output; Q5 of the upper bridge power chips Q4 to Q6 and Q2 of the lower bridge power chips Q1 to Q3 form a V-phase output; and Q4 of the upper bridge power chips Q4 to Q6 and Q3 of the lower bridge power chips Q1 to Q3 form a W-phase output.

[0026] The upper bridge power chips Q4 to Q6 and the lower bridge power chips Q1 to Q3 are soldered to the upper bridge base island and the lower bridge base island using solder paste, solder pads or nano silver paste.

[0027] Among them, the pins of pin assembly 3 are made of copper alloy material to enhance current carrying capacity and heat dissipation.

[0028] The outer shell is made of silicone gel shell 2. The fluidity of silicone gel helps to fill the gaps inside the module, provides insulation protection, enhances the support of internal bonding wires and power chips, and improves the reliability of the module.

[0029] To avoid interference from complex wiring, this embodiment also includes a thermistor 6 and a temperature detection circuit topology distributed on the front side of the substrate. The thermistor 6 and the temperature detection circuit topology are located at the edge of the substrate and on the same side of the three lower bridge base islands. The thermistor 6 is close to the upper bridge base island, which facilitates accurate acquisition of the internal chip temperature. The temperature detection circuit topology is the temperature control pins T1 to T2. By placing the thermistor 6 and the temperature detection circuit topology at the edge of the substrate, the thermistor 6 is specially designed at the edge pin position of the module and close to the upper bridge base island. It can accurately detect the internal temperature of the module without occupying the internal space of the module. This position can effectively sense the average temperature inside the module and will not be excessively affected by a local hot spot, nor will it be inaccurate due to being too far from the heat source. At the same time, it can avoid electromagnetic interference to the module caused by the stray inductance generated during overcurrent. This solves the problem that a single MOSFET is required to build a three-phase full bridge, which requires 6 independent devices. When independent MOSFETs form a three-phase full bridge, the parameters are inconsistent, resulting in an imbalance of the three-phase current, thus improving the reliability of the module.

[0030] In practical applications, this embodiment can be easily integrated into various electronic devices. Due to the bidirectional pin arrangement, engineers can design circuit boards more flexibly, eliminating the need to concentrate all connections on one side and greatly simplifying wiring. Simultaneously, the accurate temperature detection function of the thermistor 6 allows the module to monitor its own temperature status in real time, taking timely protective measures in case of abnormal temperatures, thus improving the module's stability and lifespan.

[0031] The main factor that enables this embodiment to reduce thermal resistance and improve heat dissipation efficiency is that, Figure 7 and 8 As shown, this is a traditional bottom-heat-dissipating package. Traditional bottom-heat-dissipating paths are long, resulting in complex PCB wiring and a large footprint. The PCB also has low thermal conductivity, leading to insufficient heat dissipation efficiency. Furthermore, traditional bottom-heat-dissipating devices require a large PCB area, limiting the improvement of system power density. For example... Figure 9 and 10 The diagram shows the heat dissipation path of the top-heat-dissipating package in this embodiment. The junction temperature of the power chip is mainly dissipated through the DBC, with little heat dissipation through the bonding wires and the housing. In contrast, the bottom-heat-dissipating package of this embodiment has a PCB board between the heat sink and the bottom heat sink of the module, which reduces the heat dissipation efficiency. The top-heat-dissipating package can directly connect the module to the heat sink, thereby shortening the heat dissipation path, improving heat dissipation, and reducing thermal resistance.

[0032] Compared to traditional discrete component solutions, the top-heat-dissipating packaging structure of the power module of this invention has the following advantages: Firstly, during customer application installation, automated surface mount technology can directly solder the module, increasing assembly efficiency by more than 5 times compared to soldering 6 discrete components, making it suitable for mass production. Secondly, compared to a three-phase circuit formed by soldering six single tubes onto a board, this module reduces some components and shrinks the PCB area. Furthermore, the traditional bottom heat dissipation path is chip → solder layer → substrate → solder layer → PCB → TIM material → heat sink, requiring heat conduction through the PCB. However, the PCB has low thermal conductivity, significantly impacting heat transfer efficiency. The power chip junction temperature is primarily dissipated through the DBC, with minimal heat dissipation through bonding wires and the casing. In contrast, the traditional bottom heat dissipation path, compared to the top-heat-dissipating packaging of this embodiment, involves a PCB layer between the heat sink and the module's bottom heat sink, reducing heat dissipation efficiency. Figure 2 As shown, this embodiment uses the exposed metal at the top as a common heat dissipation substrate to directly transfer the heat generated by the chip to the external heat sink, shortening the heat conduction path, greatly reducing the thermal resistance, and solving the problem of temperature uniformity among multiple chips.

[0033] Example 2 This embodiment provides a substrate structure for use in the top heat dissipation packaging structure of a power module. The substrate is an alumina ceramic substrate. Since power modules made from existing high-performance ceramic substrates such as aluminum nitride and silicon nitride are costly and not conducive to large-scale industrial applications, this embodiment uses an alumina ceramic substrate, which improves integration while reducing system cost.

[0034] The alumina ceramic substrate is the core carrier of the entire module, possessing excellent thermal conductivity and electrical insulation. Metallized conductive patterns are distributed on the alumina ceramic substrate for electrical interconnection of the chips. The thickness of the alumina ceramic substrate is between 0.38 mm and 0.8 mm, preferably 0.635 mm. The thermal conductivity of the alumina ceramic substrate is between 24 W / (m·K) and 30 W / (m·K), a material choice that allows heat to be rapidly conducted from the chip to the heat dissipation structure.

[0035] The distributed copper plating 11 on the front side of the DBC ceramic substrate directly contacts the back side of the power chip, forming a common heat dissipation path. The distributed copper plating 12 on the back side of the DBC ceramic substrate has a thickness of 1.0mm to 2.0mm, preferably 1.5mm. This distributed copper plating 12 is exposed to the outside of the module and can directly contact an external heat sink, achieving efficient heat dissipation through thermal grease or thermal adhesive (TIM) materials. This heat dissipation structure shortens the heat conduction path; the heat transfer path is: chip → DBC ceramic substrate → TIM material → heat sink, significantly reducing thermal resistance.

[0036] The encapsulation uses a silicone gel shell to encapsulate the power chip, thermistor 6 temperature sensor, and DBC ceramic substrate together via bonding wires. The back side exposes the distributed copper plating 12 on the reverse side of the DBC ceramic substrate and the bottom pin assembly 3. The silicone gel shell has excellent insulation properties and mechanical strength, protecting the internal structure from external environmental influences.

[0037] In a preferred embodiment, the six power chips are identical MOSFET chips with a rated current of 30A, a rated voltage of 100V, and an on-resistance of 2.8mΩ. The six power chips are interconnected by bonding wires to form a three-phase full-bridge circuit, which can drive a three-phase brushless DC motor or a three-phase AC load.

[0038] In another preferred embodiment, a layer of thermally conductive silicone with a thickness of 0.2 mm to 0.5 mm and a thermal conductivity of not less than 3 W / (m·K) is added between the top heat dissipation metal plate and the MOS six-in-one module to improve contact thermal resistance.

[0039] Example 3 This embodiment provides a heat dissipation structure for a top heat dissipation package structure of a power module, including a substrate 1, a housing 2, a pin assembly 3, and upper-bridge power chips Q4-Q6 and lower-bridge power chips Q1-Q3, which are placed in pairs. The substrate 1 serves as the carrier for the power chips, and the metal layer of the substrate 1 can serve as the electrode leads and current transmission path for power devices IGBTs or MOSFETs. Complex circuit wiring is formed through etching processes to achieve electrical connection between the chips and external circuits. It also supports integrated design for multi-chip packaging, simplifying the module structure. The insulation breakdown voltage of the ceramic layer can effectively isolate high-voltage circuits from metal components such as the heat sink and housing, preventing leakage or short circuits. Furthermore, the ceramic substrate and copper foil have high thermal conductivity, and their combination forms a low thermal resistance path of "chip-copper foil-ceramic-heat sink," which can quickly dissipate most of the heat generated by the chip, avoiding localized overheating.

[0040] In a preferred embodiment, the thermal conductivity of the thermally conductive material is 3 W / (m·K) to 15 W / (m·K), and the thickness is 0.05 mm to 0.2 mm.

[0041] The electronic component with a heat dissipation structure provided in this embodiment is a high-efficiency heat dissipation electronic packaging structure using an alumina ceramic substrate. This electronic component packaging structure includes a DBC alumina ceramic substrate, a power chip, a pin assembly 3, and a thermistor 6. The DBC ceramic substrate serves as the carrier for the power chip and possesses excellent thermal conductivity and electrical insulation properties. The power chip is soldered and fixed to the copper-clad layer 11 on the front side of the DBC ceramic substrate using conductive adhesive or lead-tin-silver solder, and is electrically connected to the pin assembly 3 via bonding wires. A thermally conductive soldering material layer is disposed below the power chip, which is in close contact with the chip surface for efficient heat conduction. A heat sink is installed at the top of this embodiment and connected to the integral copper-clad layer 12 on the back side of the DBC ceramic substrate, forming a complete heat conduction path.

[0042] The thickness of the alumina ceramic substrate can be between 0.25 mm and 2.0 mm, preferably between 0.5 mm and 1.0 mm. The alumina content can be between 96% and 99.6%, and the higher the alumina content, the better the thermal conductivity.

[0043] In a preferred embodiment, a 99.5% high-purity alumina ceramic substrate is used, which has a thermal conductivity of over 25 W / m·K, effectively improving the overall heat dissipation efficiency.

[0044] During operation, the top heat dissipation package structure of the power module is soldered to the PCB board via bottom pins, and the top heat dissipation metal plate contacts the heat sink through thermal grease. When the module is working, the heat generated by the six power chips is directly transferred to the heat sink through the top heat dissipation metal plate, achieving efficient heat dissipation. Simultaneously, a thermistor 6 monitors the internal temperature of the module in real time. When the temperature exceeds a set threshold, the external control circuit can take corresponding measures to protect the module. The top heat dissipation package structure adopts a direct heat dissipation design, directly mounting the heat sink on top of this embodiment, connected only by a single layer of highly thermally conductive material. This structural design shortens the heat conduction path from the chips to the heat sink, reducing the heat conduction distance by 30% to 60% compared to traditional side or bottom heat dissipation designs.

[0045] The thermally conductive material layer uses materials with high thermal conductivity, such as thermal grease, phase change materials, or metal-based thermal adhesives, with thermal conductivity ranging from 3 W / m·K to 15 W / m·K. The thickness of the thermally conductive material layer is controlled between 0.05 mm and 0.2 mm; the thinner the layer, the lower the thermal resistance.

[0046] In a preferred embodiment, a phase change material with a thermal conductivity of 8 W / m·K and a thickness of 0.1 mm is used, which can minimize thermal resistance while ensuring good contact.

[0047] The packaging structure also includes a shell 2 made of silicone gel material to protect the power chip and metal wires from external environmental influences. The silicone gel shell covers the chip, bonding wires, DBC ceramic substrate, and the top of the thermistor 6, leaving the top open to allow for the installation of the heat sink 4. This partially sealed design ensures the reliability of the electronic components without compromising heat dissipation efficiency.

[0048] In practical applications, this packaging structure is suitable for electronic components that generate a lot of heat, such as power semiconductor devices, microprocessors, and RF modules. By combining an alumina ceramic substrate with a top heat dissipation packaging structure, the thermal resistance of this electronic component is reduced by 40% to 65% compared to traditional packaging structures, and the operating temperature is reduced by 15°C to 30°C, significantly improving the stability and lifespan of the component.

[0049] In high-power-density applications, forced air cooling or liquid cooling systems can be added to the top heat dissipation structure to further improve heat dissipation efficiency. Forced air cooling systems include small fans and air ducts to guide airflow to the heatsink surface; liquid cooling systems include microchannel cooling plates and circulation pumps, utilizing the high thermal conductivity of liquids to further improve heat dissipation efficiency.

[0050] This embodiment uses an alumina ceramic substrate and electronic components with a top heat dissipation packaging structure. By shortening the heat transfer path, the heat dissipation efficiency is greatly improved, solving the technical problem of insufficient heat dissipation in high power density electronic devices and providing a reliable guarantee for the miniaturization and high performance of electronic devices.

[0051] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications, or technological improvements in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A top heat dissipation package structure for a power module, comprising at least: A substrate, multiple power chips, pin assemblies, and a housing; characterized in that, The multiple power chips are arranged on the front side of the substrate according to the circuit topology corresponding to the power module. The circuit topology is used for the electrical interconnection of the multiple power chips to realize the corresponding functions of the power module. The reverse side of the substrate is provided with a copper-clad layer for heat dissipation and conduction at the top; The power chip is connected to the pin assembly and is located on the front side of the substrate; the pin assembly is used to connect to the PCB. The outer shell is formed on the front side of the substrate.

2. The power module top heat dissipation packaging structure according to claim 1, characterized in that, The power module includes a three-phase full-bridge MOS module, and the circuit topology includes at least a plurality of base islands disposed on the front side of the substrate. The plurality of base islands include an upper bridge base island and three lower bridge base islands. The upper bridge base island and the three lower bridge base islands are respectively connected to a plurality of pins of the pin assembly. The upper bridge base island and the three lower bridge base islands are distributed vertically, and the pin assemblies are led out from the upper bridge base island and the lower bridge base island respectively, and are arranged on both sides.

3. The power module top heat dissipation packaging structure according to claim 2, characterized in that, It also includes a thermistor and a temperature detection circuit topology distributed on the front side of the substrate. The thermistor and temperature detection circuit topology are located at the edge of the substrate and on the same side of the three lower bridge base islands, wherein the thermistor is close to the upper bridge base island.

4. The power module top heat dissipation packaging structure according to claim 1, characterized in that, The three-phase full-bridge MOS module includes three upper-bridge power chips and three lower-bridge power chips. The three upper-bridge power chips are mounted as a whole on the upper-bridge base island, and the three lower-bridge power chips are respectively mounted on the three lower-bridge base islands.

5. The power module top heat dissipation packaging structure according to claim 4, characterized in that, The lead assembly includes: a power supply pin, an output pin, a control pin, a sampling pin, and a temperature detection pin; The upper bridge base island and the three lower bridge base islands are respectively connected to control pins; The power supply pins, output pins, and control pins connected to the upper bridge base island are arranged in an array on the upper bridge side; The output pins, temperature detection pins, and control pins connected to the lower bridge base island are arranged in an array on the lower bridge side.

6. The power module top heat dissipation packaging structure according to claim 5, characterized in that, The pins of the pin assembly are made of copper alloy.

7. The power module top heat dissipation packaging structure according to any one of claims 1-6, characterized in that, The substrate is an alumina ceramic substrate with a thickness between 0.38 mm and 0.8 mm and a thermal conductivity between 24 W / (m·K) and 30 W / (m·K).

8. The power module top heat dissipation packaging structure according to claim 7, characterized in that, A thermally conductive layer is disposed between the substrate and the power chip. The thickness of the thermally conductive layer is 0.2 mm to 0.5 mm, and the thermal conductivity is not less than 3 W / (m·K).

9. The power module top heat dissipation packaging structure according to claim 7, characterized in that, The top heat dissipation surface of the substrate, which has a copper-clad layer, is bonded to an external heat sink through a thermally conductive material to form a heat conduction path.

10. The power module top heat dissipation packaging structure according to claim 9, characterized in that, The thermal conductivity of the thermally conductive material is 3W / (m·K) to 15W / (m·K), and the thickness is 0.05mm to 0.2mm.

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