Layout structure of a power module

Abstract

The application provides a layout structure of a power module, which comprises an insulating substrate, a first conductive film on both sides of the insulating substrate, a plurality of upper bridge chips formed on the first conductive film, a second conductive film on the middle surface of the insulating substrate, a plurality of lower bridge chips and an upper bridge source formed on the second conductive film, the sources of the plurality of upper bridge chips being connected to the second conductive film through bonding wires and then being commonly connected to the upper bridge source through the second conductive film, a plurality of upper bridge current-sharing grooves penetrating through the second conductive film, a third conductive film on the middle surface of the insulating substrate, a lower bridge source formed on the third conductive film, the sources of the plurality of lower bridge chips being connected to the third conductive film through bonding wires and then being commonly connected to the lower bridge source through the third conductive film, and a plurality of lower bridge current-sharing grooves penetrating through the third conductive film.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a layout structure of a power module. Background Technology

[0002] Electric vehicles prioritize ultra-fast charging, low power loss, and long driving range, widely employing silicon carbide power modules (hereinafter referred to as power modules) as their core power conversion components. Especially in the main drive system of electric vehicles, the electrothermal performance of the power module directly affects the overall vehicle performance.

[0003] The upper and lower bridges of a power module each consist of several chips connected in parallel. Ideally, these chips should turn on and off simultaneously (current sharing). However, due to manufacturing differences and layout variations, the chips do not turn on and off simultaneously, resulting in current imbalance. This current imbalance caused by manufacturing differences can be addressed by selecting chips with identical electrical parameters and connecting them in parallel. When chip parameters are consistent, chip layout becomes crucial, especially at the chip control gate level. In current power modules, the distances of several chips from the source differ, resulting in different current path lengths and varying impedances from the source to the chip. Consequently, the gate-level signals obtained by these chips differ, leading to current imbalance.

[0004] Therefore, it is necessary to provide more effective and reliable technical solutions to achieve current sharing from the chip to the source in the power module. Utility Model Content

[0005] This application provides a layout structure for a power module that enables the switching speeds of multiple parallel chips to become more consistent, which is beneficial for current sharing among the chips and improves the current output capability of the module.

[0006] This application provides a layout structure for a power module, comprising: an insulating substrate; a first conductive film located on both sides of the insulating substrate, on which a plurality of upper bridge chips are formed; a second conductive film located on the middle surface of the insulating substrate, on which a plurality of lower bridge chips and upper bridge sources are formed, wherein the sources of the plurality of upper bridge chips are connected to the second conductive film via bonding wires and are then electrically connected to the upper bridge source via the second conductive film; a plurality of upper bridge current sharing grooves penetrating the second conductive film, wherein the upper bridge current sharing grooves are used to reduce the current path length difference between the sources of the plurality of upper bridge chips and the upper bridge source; a third conductive film located on the middle surface of the insulating substrate, on which a lower bridge source is formed, wherein the sources of the plurality of lower bridge chips are connected to the third conductive film via bonding wires and are then electrically connected to the lower bridge source via the third conductive film; and a plurality of lower bridge current sharing grooves penetrating the third conductive film, wherein the lower bridge current sharing grooves are used to reduce the current path length difference between the sources of the plurality of lower bridge chips and the lower bridge source.

[0007] In some embodiments of this application, there are two first conductive films, which are symmetrical about the central axis of the insulating substrate; the second conductive film is located between the two first conductive films and is in a "Y" shape; the third conductive film is located between the "Y" bifurcation regions of the second conductive film.

[0008] In some embodiments of this application, the plurality of upper bridge chips are symmetrical about the "Y"-shaped main body region of the second conductive film, the plurality of upper bridge current equalization grooves are located in the "Y"-shaped main body region of the second conductive film, and the plurality of lower bridge chips are located in the "Y"-shaped bifurcation region of the second conductive film and are symmetrically distributed.

[0009] In some embodiments of this application, the "Y"-shaped bifurcation regions of the second conductive film are also electrically connected to each other via upper bridge current-sharing bonding wires.

[0010] In some embodiments of this application, the plurality of upper bridge flow equalization grooves are annular grooves, and the plurality of lower bridge flow equalization grooves are annular grooves.

[0011] In some embodiments of this application, a portion of the upper bridge current sharing groove near the upper bridge source electrode extends to the boundary of the second conductive film, and a portion of the lower bridge current sharing groove near the lower bridge source electrode extends to the boundary of the third conductive film.

[0012] In some embodiments of this application, the surface of the insulating substrate further includes an upper bridge gate conductive film, an upper bridge gate on the upper bridge gate conductive film, a lower bridge gate conductive film, and a lower bridge gate on the lower bridge gate conductive film. The gates of the plurality of upper bridge chips are connected to the upper bridge gate conductive film via bonding wires and are then electrically connected to the upper bridge gate through the upper bridge gate conductive film. The gates of the plurality of lower bridge chips are connected to the lower bridge gate conductive film via bonding wires and are then electrically connected to the lower bridge gate through the lower bridge gate conductive film.

[0013] In some embodiments of this application, the surface of the insulating substrate in the middle of the plurality of upper bridge current sharing grooves has an upper bridge gate island, and the gates of the plurality of upper bridge chips are first connected to the upper bridge gate island and then connected to the upper bridge gate conductive film through bonding wires. The surface of the insulating substrate in the middle of the plurality of lower bridge current sharing grooves has a lower bridge gate island, and the gates of the plurality of lower bridge chips are first connected to the lower bridge gate island and then connected to the lower bridge gate conductive film through bonding wires.

[0014] In some embodiments of this application, the lower bridge gate conductive film separates a portion of the third conductive film, and the separated portions of the third conductive film are also electrically connected to each other via lower bridge current sharing bonding wires.

[0015] In some embodiments of this application, the surface of the insulating substrate further has an upper bridge drain conductive film and an upper bridge drain located on the upper bridge drain conductive film. The drains of the plurality of upper bridge chips are interconnected through the first conductive film and then connected to the upper bridge drain conductive film through bonding wires, and then electrically connected to the upper bridge drain through the upper bridge drain conductive film.

[0016] This application provides a layout structure for a power module. This layout structure, by setting current-sharing grooves on an insulating substrate, allows the switching speeds of multiple parallel chips to tend to be consistent, which is beneficial for current sharing among the chips and improves the module's current output capability. Simultaneously, this layout structure reduces the parasitic inductance of the module by decreasing the length of the chip bonding wires. Attached Figure Description

[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0018] Figure 1 This is a schematic diagram of the layout structure of the power module described in the embodiment of this application. Detailed Implementation

[0019] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0020] The technical solution of this utility model will be described in detail below with reference to the embodiments and accompanying drawings.

[0021] Figure 1 This is a schematic diagram of the layout structure of the power module according to an embodiment of this application. The layout structure of the power module according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.

[0022] refer to Figure 1 As shown, some embodiments of this application provide a layout structure for a power module, including: an insulating substrate 100; a first conductive film 110 located on both sides of the insulating substrate 100, on which a plurality of upper bridge chips 111 are formed; a second conductive film 120 located on the middle surface of the insulating substrate 100, on which a plurality of lower bridge chips 121 and an upper bridge source 112 are formed, wherein the sources of the plurality of upper bridge chips 111 are connected to the second conductive film 120 via bonding wires and are then electrically connected to the upper bridge source 112 via the second conductive film 120; and a plurality of upper bridge current sharing grooves 113 penetrating the second conductive film 100. 20. The upper bridge current sharing groove 113 is used to reduce the current path length difference from the source of the plurality of upper bridge chips 111 to the upper bridge source 112; the third conductive film 130 is located on the middle surface of the insulating substrate 100, and a lower bridge source 122 is formed on the third conductive film 130. The sources of the plurality of lower bridge chips 121 are connected to the third conductive film 130 through bonding wires and then electrically connected to the lower bridge source 122 through the third conductive film 130; a plurality of lower bridge current sharing grooves 123 penetrate the third conductive film 130, and the lower bridge current sharing grooves 123 are used to reduce the current path length difference from the source of the plurality of lower bridge chips 121 to the lower bridge source 122. The layout structure of the power module is an axisymmetric structure, which further improves the current sharing effect.

[0023] Continue to refer to Figure 1 As shown, in some embodiments of this application, the number of the first conductive film 110 is two (see attached figure). Figure 1As shown (one on each side), the two first conductive films 110 are symmetrical about the central axis of the insulating substrate 100; the second conductive film 120 is located between the two first conductive films 110 and is in a "Y" shape; the third conductive film 130 is located between the "Y" bifurcated areas of the second conductive film 120. The "Y" structure includes a vertical main body area and bifurcated areas extending from the main body area to both sides.

[0024] In some embodiments of this application, the conductive films are actually metal films, such as copper films, located on the insulating substrate 100. The number of upper bridge chips 111 and lower bridge chips 121 is at least two, depending on the specific needs.

[0025] Continue to refer to Figure 1 As shown, in some embodiments of this application, the plurality of upper bridge chips 111 are symmetrical about the “Y”-shaped main body region of the second conductive film 120, the plurality of upper bridge flow equalization grooves 113 are located in the “Y”-shaped main body region of the second conductive film 120, and the plurality of lower bridge chips 121 are located in the “Y”-shaped bifurcation region of the second conductive film 120 and are symmetrically distributed.

[0026] Continue to refer to Figure 1 As shown, in some embodiments of this application, the "Y"-shaped bifurcation regions of the second conductive film 120 are also electrically connected to each other through the upper bridge current sharing bonding wire 114, further improving the current sharing effect.

[0027] Continue to refer to Figure 1 As shown, in some embodiments of this application, the plurality of upper bridge current sharing slots 113 are annular slots, and the plurality of lower bridge current sharing slots 123 are annular slots. In different power modules, depending on the number of chips, the chip positions, and the shape and size of the conductive film, the specific shape, size, number, and position of the plurality of upper bridge current sharing slots 113 and the plurality of lower bridge current sharing slots 123 can be set according to actual needs, as long as they can achieve the effect of reducing the current path length difference from the source of the plurality of upper bridge chips 111 to the upper bridge source 112 and reducing the current path length difference from the source of the plurality of lower bridge chips 121 to the lower bridge source 122.

[0028] In conventional designs, different chips are positioned differently, resulting in different current paths from their sources to the upper or lower bridge sources. This leads to varying switching speeds and affects the performance of the power module. However, the technical solution in this application addresses this by incorporating current-sharing slots along the current paths of the chip sources and the upper and lower bridge sources. This alters the current paths, reducing the current path differences between different chips. Consequently, the switching speeds of multiple parallel chips tend to be more consistent, promoting current sharing and improving the module's current output capability.

[0029] Continue to refer to Figure 1 As shown, in some embodiments of this application, a portion of the upper bridge current sharing groove 113 near the upper bridge source 112 extends to the boundary of the second conductive film 120, and a portion of the lower bridge current sharing groove 123 near the lower bridge source 122 extends to the boundary of the third conductive film 130. This design can interrupt the current path at the boundary of the second conductive film 120 and the third conductive film 130, thereby rerouting the source current path of the nearest chip and improving the current sharing effect.

[0030] Continue to refer to Figure 1 As shown, in some embodiments of this application, the surface of the insulating substrate 100 further includes an upper bridge gate conductive film 115, an upper bridge gate 116 located on the upper bridge gate conductive film 115, a lower bridge gate conductive film 125, and a lower bridge gate 126 located on the lower bridge gate conductive film 125. The gates of the plurality of upper bridge chips 111 are connected to the upper bridge gate conductive film 115 via bonding wires and are then electrically connected to the upper bridge gate 116 via the upper bridge gate conductive film 115. The gates of the plurality of lower bridge chips 121 are connected to the lower bridge gate conductive film 125 via bonding wires and are then electrically connected to the lower bridge gate 126 via the lower bridge gate conductive film 125.

[0031] Continue to refer to Figure 1 As shown, in some embodiments of this application, the surface of the insulating substrate 100 between the plurality of upper bridge current sharing trenches 113 has an upper bridge gate island 117. The gates of the plurality of upper bridge chips 111 are first connected to the upper bridge gate island 117 and then to the upper bridge gate conductive film 115 via bonding wires. The surface of the insulating substrate 100 between the plurality of lower bridge current sharing trenches 123 has a lower bridge gate island 127. The gates of the plurality of lower bridge chips 121 are first connected to the lower bridge gate island 127 and then to the lower bridge gate conductive film 125 via bonding wires. By first connecting the gates of different chips in parallel through the gate islands and then connecting them to the upper and lower bridge gates, the current sharing effect is further improved.

[0032] Continue to refer to Figure 1 As shown, in some embodiments of this application, the lower bridge gate conductive film 125 separates a portion of the third conductive film 130, and the separated portions of the third conductive film 130 are also electrically connected to each other through the lower bridge current sharing bonding wire 124.

[0033] Continue to refer to Figure 1As shown, in some embodiments of this application, the surface of the insulating substrate 100 further has an upper bridge drain conductive film 150 and an upper bridge drain 151 located on the upper bridge drain conductive film 150. The drains of the plurality of upper bridge chips 111 are interconnected through the first conductive film 110 and then connected to the upper bridge drain conductive film 150 through bonding wires, and then electrically connected to the upper bridge drain 151 through the upper bridge drain conductive film 150.

[0034] This application provides a layout structure for a power module. This layout structure, by setting current-sharing grooves on an insulating substrate, allows the switching speeds of multiple parallel chips to tend to be consistent, which is beneficial for current sharing among the chips and improves the module's current output capability. Simultaneously, this layout structure can also reduce the length of the chip bonding wires, thereby reducing the module's parasitic inductance.

[0035] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0036] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0037] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0038] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0039] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A layout structure for a power module, characterized in that, include: Insulating substrate; A first conductive film is located on both sides of the insulating substrate, and a plurality of bridge chips are formed on the first conductive film. The second conductive film is located on the middle surface of the insulating substrate. A plurality of lower bridge chips and upper bridge sources are formed on the second conductive film. The sources of the plurality of upper bridge chips are connected to the second conductive film through bonding wires and then electrically connected to the upper bridge source through the second conductive film. A plurality of upper bridge current sharing grooves penetrate the second conductive film, the upper bridge current sharing grooves being used to reduce the current path length difference from the source of the plurality of upper bridge chips to the source of the upper bridge; A third conductive film is located on the middle surface of the insulating substrate. A lower bridge source is formed on the third conductive film. The sources of the plurality of lower bridge chips are connected to the third conductive film through bonding wires and then electrically connected to the lower bridge source through the third conductive film. Several lower bridge current sharing grooves penetrate the third conductive film. The lower bridge current sharing grooves are used to reduce the current path length difference between the source of the several lower bridge chips and the source of the lower bridge.

2. The layout structure of the power module as described in claim 1, characterized in that, There are two first conductive films, which are symmetrical about the central axis of the insulating substrate; the second conductive film is located between the two first conductive films and is in a "Y" shape; the third conductive film is located between the "Y" bifurcation areas of the second conductive film.

3. The layout structure of the power module as described in claim 2, characterized in that, The plurality of upper bridge chips are symmetrical about the "Y"-shaped main body region of the second conductive film, the plurality of upper bridge current equalization grooves are located in the "Y"-shaped main body region of the second conductive film, and the plurality of lower bridge chips are located in the "Y"-shaped bifurcation region of the second conductive film and are symmetrically distributed.

4. The layout structure of the power module as described in claim 3, characterized in that, The "Y"-shaped bifurcation regions of the second conductive film are also electrically connected to each other through the upper bridge current-equalizing bonding wire.

5. The layout structure of the power module as described in claim 1, characterized in that, The plurality of upper bridge flow equalization grooves are annular grooves, and the plurality of lower bridge flow equalization grooves are annular grooves.

6. The layout structure of the power module as described in claim 5, characterized in that, The portion of the upper bridge current equalization groove near the upper bridge source electrode extends to the boundary of the second conductive film, and the portion of the lower bridge current equalization groove near the lower bridge source electrode extends to the boundary of the third conductive film.

7. The layout structure of the power module as described in claim 1, characterized in that, The surface of the insulating substrate also has an upper bridge gate conductive film, an upper bridge gate on the upper bridge gate conductive film, a lower bridge gate conductive film, and a lower bridge gate on the lower bridge gate conductive film. The gates of the plurality of upper bridge chips are connected to the upper bridge gate conductive film through bonding wires and are then electrically connected to the upper bridge gate through the upper bridge gate conductive film. The gates of the plurality of lower bridge chips are connected to the lower bridge gate conductive film through bonding wires and are then electrically connected to the lower bridge gate through the lower bridge gate conductive film.

8. The layout structure of the power module as described in claim 7, characterized in that, The insulating substrate surface in the middle of the plurality of upper bridge current sharing grooves has an upper bridge gate island. The gates of the plurality of upper bridge chips are first connected to the upper bridge gate island and then to the upper bridge gate conductive film via bonding wires. The insulating substrate surface in the middle of the plurality of lower bridge current sharing grooves has a lower bridge gate island. The gates of the plurality of lower bridge chips are first connected to the lower bridge gate island and then to the lower bridge gate conductive film via bonding wires.

9. The layout structure of the power module as described in claim 7, characterized in that, The lower bridge gate conductive film separates a portion of the third conductive film, and the portions of the third conductive film are also electrically connected to each other through the lower bridge current sharing bonding wire.

10. The layout structure of the power module as described in claim 1, characterized in that, The surface of the insulating substrate also has an upper bridge drain conductive film and an upper bridge drain located on the upper bridge drain conductive film. The drains of the plurality of upper bridge chips are interconnected through the first conductive film and then connected to the upper bridge drain conductive film through bonding wires, and then electrically connected to the upper bridge drain through the upper bridge drain conductive film.

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