A system-in-package structure based on TO-263 frame
Patent Information
- Application Number
- CN202522128370.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-09
- Publication Date
- 2026-10-20
- Estimated Expiration
- 2035-10-09
AI Technical Summary
[0002]随着电子设备的小型化和高性能化,传统的封装技术已经难以满足现代电子系统的需求
本实用新型设计的封装不更换原有封装形式,在原有的封装基础上,充分利用原有封装空间通过打线的方式将所有系统所应用的器件连接起来,通过IC封装体保证了产品使用效果增加系统稳定性和系统质量降低成本。
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Figure CN224875395U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the field of semiconductor testing technology, and in particular to a system-in-package structure based on the TO-263 framework. Background Technology
[0002] With the miniaturization and increasing performance of electronic devices, traditional packaging technologies are no longer sufficient to meet the demands of modern electronic systems. The TO-263 frame, as a widely used packaging form, offers excellent heat dissipation and mechanical stability. Currently, TO-263 frame packaging primarily involves a single chip, but the actual area of the frame's base island is much smaller than the actual base island area, resulting in significant resource waste. Many MOS products are controlled by external systems, and these external control chips require various packages, further occupying external PCB board space. This application also leads to substantial resource waste, while external solutions increase system instability, reduce product performance, and cause excessive power consumption. Utility Model Content
[0003] The technical problem to be solved by this utility model is to provide a system-level packaging structure based on the TO-263 framework to address the shortcomings of the above-mentioned technical solutions and solve the problems existing in the prior art.
[0004] A system-in-package (SIP) structure based on the TO-263 framework includes: a MOSFET chip, a system control chip, electronic components, and a ceramic substrate. The electronic component is a capacitor. The ceramic substrate is a novel substrate using a nickel-palladium-gold plating process. The wire bonding is gold wire and aluminum wire, but not limited to gold wire and aluminum wire. The ceramic substrate, the MOSFET chip, the system control chip, and the electronic components are connected by insulating adhesive. The MOSFET chip and the system control chip are connected by solder paste.
[0005] Preferably, the total length of the packaging structure is 10.9 mm, the total width is 9.5 mm, the total height is 5.675 mm, and the width of the main body of the packaging structure is 3.475 mm.
[0006] Preferably, the package structure further includes three pins: two anode pins and one cathode pin. The two anode pins are located at the bottom of the package structure and are symmetrically distributed. Each pin has a width of 2.54 mm and a center distance of 5.08 mm between the two pins. The cathode pin is located at the top of the package and has a width of 4.6 mm.
[0007] Preferably, the system control chip is located above the ceramic substrate and is connected to the electronic components via wire bonding.
[0008] Preferably, the electronic component comprises two electronic components; the electronic components are located below the ceramic substrate.
[0009] Preferably, the electronic component is one of a capacitor, a resistor, or an inductor.
[0010] Preferably, the electronic components are connected to the system control chip and other components via wire bonding.
[0011] Preferably, the system control chip and the electronic components are connected by wire bonding.
[0012] Based on the above technical solution, the present invention provides a system-level packaging structure based on the TO-263 frame, which has the following technical effects: The packaging design of this utility model does not change the original packaging form. On the basis of the original packaging, it makes full use of the original packaging space and connects all the devices used in the system by wire bonding. The IC package ensures the product performance, increases system stability and quality, and reduces costs. Attached Figure Description
[0013] The accompanying drawings, which form part of this document, are used to provide a further understanding of the document. The illustrative embodiments and descriptions herein are used to explain the document and do not constitute an undue limitation thereof. In the drawings: Figure 1 This is a schematic diagram of a system-level packaging structure based on the TO-263 framework provided in an embodiment of this application. Detailed Implementation
[0014] To make the objectives, technical solutions, and advantages of the embodiments described herein clearer, the technical solutions in the embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments described herein, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments described herein without creative effort are within the scope of protection of this document. It should be noted that, unless otherwise specified, the embodiments and features described herein can be arbitrarily combined with each other.
[0015] Unless the context explicitly requires it, the words "comprising," "including," and similar terms throughout the specification and claims should be interpreted as encompassing rather than being exclusive or exhaustive; that is, meaning "including but not limited to."
[0016] Example 1: To achieve the above objective, as follows... Figure 1 As shown, a system-level encapsulation structure based on the TO-263 framework includes: The system comprises a MOS chip 1, a system control chip 2, an electronic component 4, and a ceramic substrate 3, wherein the electronic component is a single unit. In this embodiment, the electronic component 4 is a capacitor, the ceramic substrate 3 is a novel substrate using a nickel-palladium-gold plating process, and the wire bonding is gold wire and aluminum wire, but not limited to gold wire and aluminum wire. The ceramic substrate, the MOS chip 1, the system control chip 2, and the electronic component 4 are connected by insulating adhesive, and the MOS chip 1 and the system control chip 2 are connected by solder paste, but not limited to solder paste.
[0017] The total length of the packaging structure is 10.9 mm, the total width is 9.5 mm, the total height is 5.675 mm, and the width of the main body of the packaging structure is 3.475 mm.
[0018] The package structure also includes three pins: two anode pins and one cathode pin. The two anode pins (which together constitute electronic component 4) are located at the bottom of the package structure and are symmetrically distributed. Each pin is 2.54 mm wide and the center distance between the two pins is 5.08 mm. The cathode pin is located at the top of the package and is 4.6 mm wide.
[0019] The system control chip 2 is located above the ceramic substrate 3. The system control chip 2 is the core of the entire package structure, responsible for controlling and managing the operation of the entire system. It is connected to the electronic component 4 via wire bonding. The electronic component 4 includes two electronic components located below the ceramic substrate. These electronic components can be passive components such as capacitors, resistors, and inductors. The electronic component 4 is connected to the system control chip and other components via wire bonding. The entire system-in-package structure based on the TO-263 frame is located on a ceramic substrate 3. The ceramic substrate 3 is a high thermal conductivity and high insulation material suitable for packaging power electronic devices. The circuitry on the ceramic substrate 3 is designed to achieve electrical connections between the chip and the electronic components. The system control chip and the electronic components are connected via wire bonding.
[0020] Those skilled in the art will understand that the embodiments described herein can be provided as an apparatus (device). Therefore, this document may take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects.
[0021] Although preferred embodiments have been described herein, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this document.
[0022] Obviously, those skilled in the art can make various modifications and variations to this document without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the intent of this document also includes such modifications and variations.
[0023] Although preferred embodiments have been described herein, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this document.
[0024] Obviously, those skilled in the art can make various modifications and variations to this document without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims and their equivalents, the intent of this document also includes such modifications and variations.
Claims
1. A system-level encapsulation structure based on the TO-263 framework, characterized in that: include: MOSFET chip, system control chip, electronic components, ceramic substrate, wherein the electronic component is one piece; The electronic component is a capacitor, the ceramic substrate is a novel substrate using a nickel-palladium-gold plating process, the wire bonding is gold wire and aluminum wire, but not limited to gold wire and aluminum wire, the ceramic substrate, the MOS chip, the system control chip, and the electronic components are connected by insulating adhesive, and the MOS chip and the system control chip are connected by solder paste.
2. The system-level packaging structure based on the TO-263 framework according to claim 1, characterized in that, The total length of the packaging structure is 10.9 mm, the total width is 9.5 mm, the total height is 5.675 mm, and the width of the main body of the packaging structure is 3.475 mm.
3. A system-level packaging structure based on the TO-263 framework according to claim 2, characterized in that, The package structure also includes three pins: two anode pins and one cathode pin. The two anode pins are located at the bottom of the package structure and are symmetrically distributed. Each pin is 2.54 mm wide and the center distance between the two pins is 5.08 mm. The cathode pin is located at the top of the package and is 4.6 mm wide.
4. A system-level packaging structure based on the TO-263 framework according to claim 1, characterized in that, The system control chip is located above the ceramic substrate and is connected to the electronic components via wire bonding.
5. A system-level packaging structure based on the TO-263 framework according to claim 1, characterized in that, The electronic components include two electronic components; the electronic components are located below the ceramic substrate.
6. A system-level packaging structure based on the TO-263 framework according to claim 5, characterized in that, The electronic component is one of the following: capacitor, resistor, or inductor.
7. A system-level packaging structure based on the TO-263 framework according to claim 5, characterized in that, The electronic components are connected to the system control chip via wire bonding.