A power semiconductor package module

Abstract

The utility model provides a kind of power semiconductor packaging module, by N-phase power inverter pad architecture, N high side power chip is co-located in a power input pad, and let N low side power chip be set in corresponding floating phase node pad separately, N low side power chip is connected to power loop pad by second electrical connection group, i.

Description

Technical Field

[0001] This utility model relates to the field of semiconductors, specifically to a power semiconductor packaging module. Background Technology

[0002] In power electronic applications, bridge circuits are a crucial type of drive circuit, including half-bridge, H-bridge, and three-phase full-bridge circuits. To package bridge circuits, two main packaging schemes are employed:

[0003] One approach is a discrete device combination scheme, which involves soldering multiple independent power semiconductor chips (such as IGBTs and MOSFETs), driver chips, freewheeling diodes, and other discrete components onto a substrate, then connecting them with wires or copper busbars to form topologies such as half-bridges and H-bridges, and finally using an external heat sink for heat dissipation.

[0004] The second option is the integrated module solution, which uses traditional power module packaging technology to integrate the chips required for the bridge circuit (such as upper and lower bridge arm switches and diodes) onto the same insulating substrate (such as Al2O3 ceramic substrate or Si3N4 ceramic substrate). The chips are electrically connected to the lead frame through wire bonding or flip-chip bonding. The external packaging is made of plastic or metal shells, and the input control pins and power pins are brought out. Heat dissipation is achieved through contact between the bottom of the substrate and the heat sink.

[0005] Taking the three-phase full-bridge circuit packaging in a new energy vehicle motor controller as an example, traditional integrated module solutions typically employ a three-layer structure of "chip-substrate-heat sink": the power chip is soldered onto a ceramic insulating substrate (DBC), and the bottom of the substrate is mechanically connected to a metal heat sink; the chip's gate and source (or emitter) are bonded to a lead frame via metal wires, while the drain (or collector) is directly led out through the substrate's metal layer; the drive circuit and protection circuit are integrated on a separate PCB board and connected to the power module pins via connectors. This type of solution is widely used in medium-to-high power scenarios such as industrial frequency converters, photovoltaic inverters, and new energy vehicle motor drives, and its core design goal is to reduce system assembly complexity through integration.

[0006] However, the source and drain pins of the aforementioned existing solutions are mostly discretely designed, requiring multiple external copper busbars to form a bridge arm circuit, further increasing the system size and assembly difficulty. The packaging architecture disclosed in Chinese patent application "CN222261050U" requires two independent, sufficiently large output pads for the two upper transistors to support and dissipate heat, while the lower transistor also needs a fixed position and interconnection space. This symmetrical layout limits further miniaturization of the package structure to some extent. The Chinese patent applications disclosed in Chinese patent applications "CN221176218U" or "CN117525047A" show that the power module has many or thick internal wirings, resulting in strong mutual interference between internal components, i.e., significant internal stray power, requiring further optimization. Furthermore, Chinese invention patent with announcement number "CN120091620A" discloses a concept for an integrated source and drain configuration. However, in the implementation of this module, only some embodiments integrate the drain via metal interconnects. This method adds a wire bonding process step, and due to the lack of a fixed and stable support, it is prone to detachment during subsequent potting or encapsulation, affecting the reliability of the power device. In addition, the heat dissipation of this application relies solely on the metal interconnect layer where the power chip is located. Under excessively high external conditions or prolonged loads, the power chip faces the risk of high-temperature failure. Therefore, the heat dissipation capability of existing power chips or modules needs further optimization. Utility Model Content

[0007] To address the problems of low integration, poor heat dissipation efficiency, and poor module stability in existing technologies, this invention provides a power semiconductor packaging module. Through an N-phase power inverter pad architecture, N high-side power chips are placed on a single power input pad, while N low-side power chips are discretely positioned on corresponding floating phase node pads. These N low-side power chips are connected to the power loop pad via a second electrical connector group; that is, the source and drain of the N low-side power chips are connected together to the power loop pad. This completes the electrical interconnection of the two-phase half-bridge within the same package module. By optimizing the pad layout, the chip arrangement is optimized based on the optimized pad layout, and further optimizing the wiring arrangement between the chips, the chip integration is gradually improved. The copper layer of the power input pad simultaneously serves as the main heat sink for the N high-side power chips, and the copper layer of the power loop pad simultaneously serves as the main heat sink for the N low-side power chips, improving heat dissipation efficiency and enhancing module stability while ensuring high integration.

[0008] The objective of this utility model is achieved through the following solution:

[0009] This utility model provides a power semiconductor packaging module, including:

[0010] Power input pad, configured as a power input terminal;

[0011] Power circuit pads are configured as power circuit terminals;

[0012] N power inverter pads, where N is an integer greater than or equal to 1, are located on the same metal layer plane as the power input pads and the power loop pads and are electrically isolated from each other;

[0013] N high-side power chips are placed on the power input pad;

[0014] N low-side power chips are respectively disposed on the corresponding power inverter pads;

[0015] Each of the high-side power chips is connected to a corresponding power inverter pad via a first electrical connector;

[0016] Each of the low-side power chips is connected to the power loop pad via a second electrical connection group.

[0017] Preferably, by configuring the value of N, the packaging module constitutes a basic power module:

[0018] When N=1, it forms a half-bridge power unit;

[0019] When N=2, it forms an H-bridge power unit;

[0020] When N=3, it forms a three-phase full-bridge power unit.

[0021] Preferably, it further includes at least 2N power control terminals, wherein the control electrodes of the N high-side power chips and the N low-side power chips are respectively connected to the corresponding power control terminals.

[0022] Preferably, each of the N high-side power chips and the N low-side power chips is provided with a power sampling terminal, which is used to sample each power chip.

[0023] Preferably, the high-side power chip is disposed on the front or back of the power input pad; the low-side power chip is disposed independently on the front or back of the power pad.

[0024] Preferably, the power input pad, the power loop pad, and at least one of the N shared power pads have an auxiliary heat dissipation metal sheet attached to at least one side.

[0025] Preferably, the power input pad, the power loop pad, and the side of the N shared power pads without power chips are all provided with a semi-etched step structure.

[0026] Preferably, it also includes a thermistor and a temperature-checking power terminal for connecting the thermistor, for real-time detection and output of the operating temperature signal of the packaged module.

[0027] Preferably, the power input pads, power loop pads, and N power inputs are provided with mounting slots for external application mounting; and / or, thermally conductive vias are provided in the area near the corners within the top view of the pads.

[0028] Preferably, each of the N high-side power chips and the N low-side power chips is provided with a power sampling terminal, which is used to sample each power chip.

[0029] Preferably, it also includes a package that encapsulates the structure except for the pad mounting surface and the heat dissipation surface.

[0030] Compared with the prior art, the present invention has the following beneficial effects:

[0031] 1. The first and second power inverter pads are electrically independent and insulated from the power input and power loop pads, forming a floating phase node. Therefore, the first and second power inverter pads can operate in parallel within the same package, reducing the external radiation area, while allowing the phase potential to switch freely between 0 and VDD. This avoids bus short circuits and ensures controllable common-mode / differential-mode circuits, achieving a highly integrated and reliable multiphase power module. This not only achieves superior electrical performance and compactness at the chip level but also provides unparalleled scalability and integration efficiency at the system level.

[0032] 2. By unifying the power input pad and power loop pad bus structure, the power path becomes more regular, improving integration.

[0033] 3. By optimizing the heat dissipation of existing power devices and setting the power chip to face the PCB board, the stability of power devices or modules in high-temperature environments has been further improved.

[0034] 4. The internal and external connection pads are equipped with mounting slots, through holes, and semi-etched steps to improve product assembly speed, product packaging stability, and product end-application stability;

[0035] 5. By using a shared source and drain configuration for the power device package structure, multiple external power terminals are no longer needed to form a bridge arm circuit, which reduces the system size and assembly difficulty, and can effectively reduce the cost of power devices. Attached Figure Description

[0036] The embodiments of this utility model will be further described below with reference to the accompanying drawings:

[0037] Figure 1 A schematic diagram of the packaging layout provided for an embodiment of this utility model;

[0038] Figure 2 A schematic diagram of the bridging component provided in an embodiment of this utility model;

[0039] Figure 3 A schematic diagram of the through hole and mounting groove provided in an embodiment of this utility model;

[0040] Figure 4 A schematic diagram of the overall packaging shell provided for an embodiment of this utility model;

[0041] Figure 5 A power semiconductor packaging module suitable for reverse-mounted power chips is provided for embodiments of this utility model;

[0042] Figure 6 The semi-etched step structure provided in this embodiment of the utility model;

[0043] Figure 7 The heat dissipation packaging structure provided in the embodiments of this utility model;

[0044] Figure 8 A schematic diagram of the sampling terminal layout provided for an embodiment of this utility model;

[0045] Figure 9 This invention provides a semiconductor packaging module based on existing DPIM packaging design for embodiments of the present invention.

[0046] In the above attached figures:

[0047] VDD, Power Input Pad; VSS, Power Loop Pad; V, First Power Inverter Pad; U, Second Power Inverter Pad; Q1, First Power Chip; Q2, Second Power Chip; Q3, Third Power Chip; Q4, Fourth Power Chip; G1-G4, Power Control Terminals; S1-S4, Power Sampling Terminals; T1-T2, Temperature Sampling Terminals; Rt, Thermistor;

[0048] 10. Packaging module; 11. Metal strip; 12. Bridging component; 13. Mounting slot; 14. Through hole; 15. Semi-etched step; 16. Top heat sink; 17. Bottom heat sink; 18. Ceramic substrate. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present utility model and are not intended to limit the scope of the present utility model.

[0050] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation", "connection", and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0051] Example 1

[0052] As one possible implementation, this embodiment provides a power semiconductor packaging module. As a first implementation, it includes:

[0053] The power input pad VDD is configured as a power input terminal.

[0054] The power loop pad VSS is configured as the power loop terminal.

[0055] There are N power inverter pads, where N is an integer greater than or equal to 1. The N power inverter pads are on the same metal layer plane as the power input pad VDD and the power loop pad VSS and are electrically isolated from each other.

[0056] N high-side power chips are placed together on the power input pad VDD;

[0057] N low-side power chips are respectively set on the corresponding power inverter pads;

[0058] Each high-side power chip is connected to a corresponding power inverter pad via a first electrical connector;

[0059] Each low-side power chip is connected to the power loop pad VSS via a second electrical connection group.

[0060] This embodiment utilizes an N-phase power inverter pad architecture, placing N high-side power chips on a single power input pad VDD, and discretely mounting N low-side power chips on corresponding floating phase node pads. These N low-side power chips are connected to the power loop pad VSS via a second electrical connection group; that is, the source and drain terminals of the N low-side power chips are connected together to the power loop pad VSS, thus enabling them to operate within the same package module.

[0061] Within 10 days, all electrical interconnections of the two-phase half-bridge were completed. By optimizing the pad layout, the chip settings were optimized based on the optimized pad layout, and the wiring arrangement between the chips was further optimized to gradually improve the chip integration. The copper layer of the power input pad VDD simultaneously became the main heat sink for N high-side power chips, and the copper layer of the power circuit pad VSS simultaneously became the main heat sink for N low-side power chips, improving heat dissipation efficiency and improving the stability of the module while ensuring high integration.

[0062] Specifically, this embodiment can be applied to half-bridge power units, H-bridge power units, or three-phase bridge power units. By configuring the value of N, the encapsulation module...

[0063] 10 constitute a basic power module: when N=1, it constitutes a half-bridge power unit; when N=2, it constitutes an H-bridge power unit; when N=3, it constitutes a three-phase bridge power unit. When configuring the value of N, when N≥2, multiple half-bridge power units in the layout structure share the power input pad VDD and the power loop pad VSS.

[0064] In this embodiment, at least 2N power control terminals G1-G4 are also included, with the control electrodes of N high-side power chips and N low-side power chips respectively connected to the corresponding power control terminals G1-G4. Each of the N high-side power chips and N low-side power chips is provided with a power sampling terminal S1-S4, which is used to sample each power chip. The high-side power chips are disposed on the front or back of the power input pad VDD; the low-side power chips are independently disposed on the front or back of the power pad. The power input pad VDD, the power loop pad VSS, and at least one of the N shared power pads have auxiliary heat dissipation metal sheets attached to at least one side.

[0065] Example 2

[0066] like Figure 1 As shown, this embodiment provides a power semiconductor packaging module suitable for H-bridges, as a second implementation method, including:

[0067] The power input pad VDD is configured as a power input terminal.

[0068] The power loop pad VSS is configured as the power loop terminal.

[0069] Two power inverter pads, including a first power inverter pad V and a second power inverter pad U, are electrically isolated from each other in structure, and are on the same metal layer plane as the power input pad VDD and the power loop pad VSS and are electrically isolated from each other.

[0070] N high-side power chips are placed on the power input pad, including the first power chip Q1 and the second power chip Q2;

[0071] N low-side power chips are respectively set on the corresponding power inverter pads, including the third power chip Q3 and the fourth power chip Q4;

[0072] The first power chip Q1 and the second power chip Q2 are connected to the first power inverter pad V and the second power inverter pad U respectively via electrical connectors.

[0073] The third power chip Q3 and the fourth power chip Q4 are connected to the power loop pad VSS via an electrical connector group.

[0074] In this embodiment, the first power chip Q1 and the second power chip Q2 are placed together on the power input pad VDD, the third power chip Q3 is placed on the first power inverter pad V, and the fourth power chip Q4 is placed on the second power inverter pad U. Then, the source and drain terminals of the third power chip Q3 and the fourth power chip Q4 are connected together to the power loop pad VSS via an electrical connector group. This completes the electrical interconnection of the two-phase half-bridge within the same package module 10, improving chip integration. The power input pad VDD simultaneously serves as the main heat sink for the first power chip Q1 and the second power chip Q2, while the power loop pad VSS simultaneously serves as the main heat sink for the third power chip Q3 and the fourth power chip Q4, achieving partial or complete double-sided heat dissipation and improving heat dissipation efficiency. This results in a balanced distribution within the package module 10, ensuring high integration while improving module stability.

[0075] Specifically, in this embodiment, the power input pad VDD is located in the center or on one side of the package module layout. The first power inverter pad V and the second power inverter pad U are symmetrically arranged side by side with respect to the power input pad VDD along the axial direction. The power loop pad VSS is located on the side opposite to the first power inverter pad V and the second power inverter pad U and away from the power input pad VDD. After the current starts from the power input pad VDD, it can flow to the first power inverter pad V and the second power inverter pad U along two conductive paths of equal length, equal width, and equal cross-section, respectively, and then return to the power loop pad VSS along the same axial direction. This can greatly reduce the return current area and improve the switching reliability and efficiency of the device. Specifically, based on the shared circuit formed by the power input pad VDD and the power loop pad VSS, the power input pad VDD, the first power inverter pad V, the second power inverter pad U, and the power loop pad VSS are sequentially occupied along an axis to form a single-axis four pads. They can be mirrored left and right within the package without the need for cross-wire bonding or buried jumper layers, thus improving integration density.

[0076] The power input pad VDD is centered (or on one side) and becomes the center of the heat source. The first power inverter pad V and the second power inverter pad U are symmetrically attached to its two sides. The heat flow is forced to spread out in both directions in equal amounts, and the heat diffusion angle is maximized, thereby improving the heat dissipation power.

[0077] like Figure 2 As shown, the first power chip Q1 and the third power chip Q3 form the first half-bridge arm, with its output node being the first power inverter pad V; the second power chip Q2 and the fourth power chip Q4 form the second half-bridge arm, with its output node being the second power inverter pad U; the two half-bridge arms have power input pads VDD and power loop pads VSS. Connecting the four power chips into two half-bridges, sharing the power input pad VDD and the power loop pad VSS, is equivalent to completing one arm of a single-phase or three-phase inverter bridge within the package module 10, simplifying wiring. This achieves uniform current density and heat distribution, avoiding localized overheating and current bias.

[0078] The power semiconductor package module suitable for H-bridge also includes at least four power control terminals G1-G4, wherein the four power control terminals G1-G4 are respectively arranged in pairs on the power input pad VDD side and the power loop pad VSS side. The control of the first power chip Q1, the second power chip Q2, the third power chip Q3, and the fourth power chip Q4 are connected to the corresponding power control terminals G1-G4 with the shortest distance. The power control terminals G1-G4 are arranged on the same side as the power input pad VDD and the power loop pad VSS, so the drive traces do not need to cross the copper surface or take long routes; they can be completed on one side.

[0079] like Figure 4 As shown, the above technical features can be combined according to actual application needs to meet the stable operation requirements of more key components of new energy vehicles with low voltage platforms. This solution uses epoxy resin for encapsulation to obtain the encapsulation body 10.

[0080] This embodiment mainly provides a bridge drive circuit for H-bridge. The packaging structure of this embodiment can also be applied to bridge drive circuits for half-bridge and three-phase full-bridge.

[0081] Example 3

[0082] As one possible implementation method, such as Figure 3As shown, while reducing the integration density, in order to ensure the heat dissipation efficiency on the pads, this embodiment provides a packaging structure based on embodiment 1. Mounting slots 13 for external application mounting are provided on the power input pad VDD, the first power inverter pad V, the second power inverter pad U, and the power loop pad VSS. Furthermore, through holes 14 are provided near the corners of the top view contours of the power input pad VDD, the first power inverter pad V, the second power inverter pad U, and the power loop pad VSS. The through holes 14 further enhance the adhesion of the pads, firmly "anchor" the power devices inside the package module, and eliminate mechanical stress concentration, preventing damage to the pads during thermal cycling.

[0083] Example 4

[0084] As one possible implementation method, based on Example 2, such as Figure 5 As shown, this embodiment provides a power semiconductor packaging module suitable for reverse-mounting power chips, including: a power input pad VDD, a power loop pad VSS, a first power inverter pad V, a second power inverter pad U, a first power chip Q1, a second power chip Q2, a third power chip Q3, a fourth power chip Q4, and power control pins G1-G4 connected to the control electrodes of the power chips. The first power chip Q1, the second power chip Q2, the third power chip Q3, and the fourth power chip Q4 are respectively disposed on the power input pad VDD, the first power inverter pad V, and the second power inverter pad U. The first power chip Q1, the second power chip Q2, the third power chip Q3, and the fourth power chip Q4 are all disposed on the metal layer of the corresponding pads; and the active surfaces of the first power chip Q1 and the second power chip Q2 are disposed away from the metal layer and facing the mounting surface of the packaging module. That is, the power chips are reverse-mounted to the side of the semiconductor packaging module facing the PCB application, which can keep the package size unchanged, eliminate the need for additional heat sinks, and achieve high heat dissipation capacity through the frame itself.

[0085] like Figure 6 As shown, the power input pad, the first power inverter pad, the second power inverter pad, and the power loop pad all have a semi-etched step 15 structure on the side without a power chip. This increases the enclosure effect of the molding compound or package module 10 and improves product reliability. Since the step is located on the back of the pad (opposite to the power chip mounting surface), it serves as a support surface for soldering to the PCB, ensuring coplanarity. The semi-etched step 15 can be a shallow groove around the back of the pad, creating a top heat dissipation path, thus simultaneously improving reliability and heat dissipation.

[0086] like Figure 7As shown, in this embodiment, the encapsulation module 10 is encapsulated with epoxy resin, which is suitable for new energy BDC brushed DC motors. Simultaneously, in this embodiment, auxiliary heat dissipation metal sheets can be provided on at least one pad of the semiconductor encapsulation module 10 facing the PCB and / or on the opposite side. Auxiliary heat dissipation metal sheets are provided along both sides of the module for the power input pad VDD, the first power inverter pad V, the second power inverter pad U, and the power loop pad VSS. These auxiliary heat dissipation metal sheets include a top heat dissipation metal sheet 16 and a bottom metal heat dissipation sheet 17, used to improve the heat dissipation capacity of the power devices and the reliability of end applications, achieving multi-path heat dissipation.

[0087] like Figure 8 As shown, to further enhance the reliability of power device terminal applications, this embodiment can also set power sampling terminals S1-S4 corresponding to the first power chip Q1, the second power chip Q2, the third power chip Q3, and the fourth power chip Q4 respectively on the lower bridge power chip or the upper and lower bridges. These terminals can sense the current magnitude, junction temperature, and on-state voltage drop of each transistor in real time, detect the overcurrent condition of the power device, and send analog signals to an external controller, improving system safety and real-time feedback reliability. Simultaneously, a thermistor Rt can be placed at the edge of the power device and connected to the temperature monitoring power terminals T1-T2 to monitor the operating temperature of the power device package structure in real time, preventing the power device from overheating and burning out, which could lead to external circuit failure. By equipping the thermistor Rt connected to the temperature monitoring power terminals T1-T2 and the power sampling terminals S1-S4, the temperature sensitivity and reliability of the power package structure are improved, making it suitable for high-temperature and high-humidity application environments.

[0088] Example 5

[0089] As one possible implementation, based on embodiment 1 or 2, such as Figure 9 As shown, this embodiment provides a semiconductor packaging module based on existing DPIM packaging design, including a package body and a power semiconductor packaging module. The package body encapsulates the structure except for the pad mounting surface and the heat dissipation surface using DPIM packaging, specifically including:

[0090] The ceramic substrate 18 comprises a first power chip Q1, a second power chip Q2, a third power chip Q3, a fourth power chip Q4, power control terminals G1-G4, and a packaging module 10. In the three-layer structure of the ceramic substrate 18, the electrical metal layer is set according to the implementation method of Embodiment 1 or Embodiment 2, and the internal electrical topology remains largely unchanged. This embodiment, by adopting DPIM packaging, is more suitable for the high power requirements of new energy vehicles, applicable to motor drives and specific automotive applications, and has good insulation and heat dissipation performance, as well as cost advantages.

[0091] The semiconductor packaging module in this embodiment can be encapsulated using silicone gel, which further improves the thermal conductivity and insulation performance of the power device packaging structure and reduces costs.

[0092] The semiconductor packaging module in this embodiment can also be made of epoxy resin.

[0093] In this embodiment, the multiple power chips are preferably MOSFETs, but they can also be IGBTs and FRDs in parallel, or power chips such as SiC and GaN.

[0094] In this embodiment, the power control terminals G1-G4 and other pins can also be selected as pins, Z-type, or S-type; no specific restrictions are imposed in this embodiment.

[0095] The packaging structure of this embodiment is designed to meet the needs of different voltages and application platforms in new energy vehicles. It is suitable for motor control modules such as motor drivers, specific automotive applications, DC brushed motors, seats, door locks, tailgates, electric suction doors, window regulators, and sunroofs. It has strong compatibility and broad application prospects.

[0096] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles of the embodiments, practical applications, or technological improvements in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A power semiconductor package module, characterized in that, include: Power input pad, configured as a power input terminal; Power circuit pads are configured as power circuit terminals; N power inverter pads, where N is an integer greater than or equal to 1, are located on the same metal layer plane as the power input pads and the power loop pads and are electrically isolated from each other; N high-side power chips are placed on the power input pad; N low-side power chips are respectively disposed on the corresponding power inverter pads; Each of the high-side power chips is connected to a corresponding power inverter pad via a first electrical connector; Each of the low-side power chips is connected to the power loop pad via a second electrical connection group.

2. The power semiconductor packaging module according to claim 1, characterized in that, By configuring the value of N, the packaging module constitutes a basic power module: When N=1, it forms a half-bridge power unit; When N=2, it forms an H-bridge power unit; When N=3, it forms a three-phase full-bridge power unit.

3. The power semiconductor packaging module according to claim 1, characterized in that, It also includes at least 2N power control terminals, with the control electrodes of the N high-side power chips and the N low-side power chips respectively connected to the corresponding power control terminals.

4. The power semiconductor packaging module according to claim 1, characterized in that, Each of the N high-side power chips and N low-side power chips is provided with a corresponding power sampling terminal, which is used to sample each power chip.

5. The power semiconductor packaging module according to claim 1, characterized in that, The high-side power chip is disposed on the front or back of the power input pad; the low-side power chip is disposed independently on the front or back of the power pad.

6. The power semiconductor packaging module according to claim 1, characterized in that, The power input pad, the power loop pad, and at least one of the N shared power pads are provided with an auxiliary heat dissipation metal sheet on at least one side.

7. The power semiconductor packaging module according to claim 1, characterized in that, The power input pad, power loop pad, and the side of the N shared power pads without power chips are all provided with a semi-etched step structure.

8. A power semiconductor packaging module according to claim 1, characterized in that, The power input pads, power loop pads, and N power inputs are provided with mounting slots for external application installation; and / or, thermally conductive vias are provided in the area near the corners within the top view of the pads.

9. The power semiconductor package module according to any one of claims 1-8, characterized in that, It also includes a thermistor and a temperature-checking power terminal for connecting the thermistor, used to detect and output the operating temperature signal of the packaged module in real time.

10. The power semiconductor package module according to any one of claims 1-8, characterized in that, It also includes a package that encapsulates the structure except for the pad mounting surface and the heat dissipation surface.

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