Packaging structure

Abstract

The utility model provides a kind of packaging structure, the packaging structure includes first substrate, including first mold seal layer, the first passive element being embedded by first mold seal layer and first circuit layer, wherein, one end of first passive element connects first circuit layer, another end is exposed by first mold seal layer;Second substrate is set in first substrate upper, and second substrate includes second mold seal layer, the second passive element being embedded by second mold seal layer, wherein, one end of second passive element is exposed by second mold seal layer and electrically connected first circuit layer of first substrate. By layer by layer making multilayer substrate, to achieve the structure of multilayer embedding, and can avoid the problem that laser via technology is prone to cause product damage.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor packaging technology, and specifically to a packaging structure. Background Technology

[0002] Currently, most embedded component technologies involve embedding passive or active components into cavities within dielectric materials. During manufacturing, laser-guided via (LHB) technology is typically used to connect terminals to chip pads. LHB technology requires special copper layers on both the terminals and chip pads to withstand the high temperatures of the laser drilling process. Without this protective layer, the laser may melt the soldered terminals or aluminum chip pads, damaging the product. Furthermore, if grinding is used instead, cracks may form at the contact surfaces of the different materials, severely impacting the quality and reliability of the final product. Utility Model Content

[0003] This utility model proposes a packaging structure.

[0004] Firstly, this utility model proposes a packaging structure, including:

[0005] The first substrate includes a first molding layer, a first passive component embedded in the first molding layer, and a first circuit layer, wherein one end of the first passive component is connected to the first circuit layer, and the other end is exposed by the first molding layer;

[0006] A second substrate is disposed above the first substrate. The second substrate includes a second molding layer and a second passive element embedded in the second molding layer. One end of the second passive element is exposed by the second molding layer and electrically connected to the first circuit layer of the first substrate.

[0007] In some optional embodiments, the packaging structure further includes:

[0008] Metal paste is applied between the second passive element and the first circuit layer.

[0009] In some optional embodiments, the packaging structure further includes:

[0010] A third substrate is disposed above the second substrate and includes a third passive element, which is electrically connected to the second substrate.

[0011] In some alternative embodiments, the first substrate further includes a first active element configured to be embedded within the first molding layer.

[0012] In some alternative embodiments, the second substrate further includes a second active element configured to be embedded within the second molding layer.

[0013] In some alternative embodiments, the second substrate further includes a second circuit layer, and the other end of the second passive element is electrically connected to the second circuit layer.

[0014] In some optional embodiments, the third substrate further includes a third molding layer and a third active element, wherein the third active element and the third passive element are disposed within the third molding layer, and one end of the third passive element is exposed by the third molding layer and electrically connected to the second circuit layer of the second substrate.

[0015] In some alternative embodiments, the third substrate further includes a third circuit layer, and the other end of the third passive element is electrically connected to the third circuit layer.

[0016] In some alternative implementations, there is a gap between the first active element and the first passive element.

[0017] In some alternative embodiments, the second passive element is disposed above the first passive element.

[0018] To address the issue that using laser-guided vias (LBV) to connect terminals to chip pads can lead to product damage due to the risk of the laser melting the soldered terminals or aluminum chip pads without a special copper layer, this invention provides a packaging structure. By fabricating multiple substrates (a first substrate and a second substrate) layer by layer to achieve a multi-layer embedded structure, the problem of product damage easily caused by LBV is avoided. Furthermore, by placing a first passive element and a first circuit layer in the first substrate, with one end of the first passive element connected to the first circuit layer, and placing a second passive element in the second substrate, with one end of the second passive element electrically connected to the first circuit layer of the first substrate, an electrical connection between the first and second substrates can be achieved through the first and second passive elements. Attached Figure Description

[0019] Other features, objects, and advantages of this invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0020] Figure 1 This is a schematic diagram of an existing embedded wiring package structure;

[0021] Figure 2 This is a schematic diagram of an existing embedded active component packaging structure;

[0022] Figure 3 This is a schematic diagram of an existing embedded passive component packaging structure;

[0023] Figure 4This is a schematic diagram of the packaging structure 4a according to an embodiment of the present invention;

[0024] Figure 5 This is a schematic diagram of the packaging structure 5a according to an embodiment of the present invention;

[0025] Figure 6 This is a schematic diagram of the packaging structure 6a according to an embodiment of the present invention;

[0026] Figure 7 This is a schematic diagram of the packaging structure 7a according to an embodiment of the present invention;

[0027] Figures 8-28 This is a schematic diagram of the manufacturing steps of the packaging structure 4a according to an embodiment of the present invention;

[0028] Figures 29-49 This is a schematic diagram of the manufacturing steps of the packaging structure 5a according to an embodiment of the present invention;

[0029] Figures 50-70 This is a schematic diagram of the manufacturing steps of the packaging structure 6a according to an embodiment of the present invention;

[0030] Figures 71-89 This is a schematic diagram of the manufacturing steps of the packaging structure 7a according to an embodiment of the present invention.

[0031] Explanation of reference numerals / symbols in the attached diagram:

[0032] 101-Carrier; 102-First circuit layer; 103-Second circuit layer; 104-Copper pillar; 105-Dielectric layer; 106-Passive component; 107-Active component; 201-First substrate; 202-Second substrate; 203-Third substrate; 204-Metal paste; 205-Fourth active component; 206-Fourth passive component; 207-Fourth molding layer; 208-Solder ball; 209-First carrier; 210-First dielectric layer; 211-Second carrier; 212-Second dielectric layer; 213-Metal pillar; 214-Seed layer; 215-Dry film; 2011-First mold sealing layer; 2012-First passive element; 2013-First circuit layer; 2014-First active element; 2015-Fourth circuit layer; 2021-Second mold sealing layer; 2022-Second passive element; 2023-Second circuit layer; 2024-Second active element; 2031-Third mold sealing layer; 2032-Third passive element; 2033-Third circuit layer; 2034-Third active element. Detailed Implementation

[0033] The specific embodiments of this utility model will be described below with reference to the accompanying drawings and examples. Those skilled in the art can easily understand the technical problems solved by this utility model and the resulting technical effects from the content described herein. It is understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, for ease of description, only the parts relevant to the invention are shown in the accompanying drawings.

[0034] It should be readily understood that the meanings of "on," "above," and "on top of" in this utility model should be interpreted in the broadest sense, such that "on" not only means "directly on something," but also means "on something" including intermediate components or layers existing between the two.

[0035] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship of one element or component to another element or component shown in the accompanying drawings. In addition to the orientations described in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90° or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0036] As used herein, the term "layer" refers to a portion of material comprising a region of a certain thickness. A layer may extend over the entirety of an underlying or upper layer structure, or may have a extent smaller than that of the underlying or upper layer structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure, with a thickness less than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a single layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A single layer may include multiple layers. For example, a semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0037] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may comprise a wide variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers. Further alternatively, the substrate may have semiconductor devices or circuits formed therein.

[0038] It should be noted that the structures, proportions, sizes, etc., shown in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and to facilitate understanding and reading of the contents described in the specification. They are not intended to limit the implementation conditions of this utility model and therefore have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by this utility model, should still fall within the scope of the technical content disclosed in this utility model. Furthermore, the terms such as "above," "first," "second," and "a" used in this specification are merely for clarity of description and are not intended to limit the scope of implementation of this utility model. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered within the scope of implementation of this utility model.

[0039] It should also be noted that the longitudinal section corresponding to the embodiment of this utility model can be the section corresponding to the front view direction, the transverse section can be the section corresponding to the right view direction, and the horizontal section can be the section corresponding to the top view direction.

[0040] Furthermore, where there is no conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0041] refer to Figure 1 , Figure 1 This is a schematic diagram of an existing embedded wiring package structure.

[0042] like Figure 1 The embedded wiring package structure shown may include a carrier 101, a first circuit layer 102, a second circuit layer 103, and a copper pillar 104.

[0043] refer to Figure 2 , Figure 2 This is a schematic diagram of an existing embedded active component packaging structure.

[0044] like Figure 2 The embedded active component package structure shown may include copper pillars 104, dielectric layer 105, and passive component 106.

[0045] refer to Figure 3 , Figure 3 This is a schematic diagram of an existing embedded passive component packaging structure.

[0046] like Figure 3 The embedded passive component package structure shown may include copper pillars 104, dielectric layer 105, and active component 107.

[0047] It can be seen that, regardless of whether it is an embedded wiring package structure, an embedded active component package structure, or an embedded passive component package structure, the reference... Figure 1 , Figure 2 and Figure 3 The dotted lines represent areas where laser-guided vias (LHs) are formed using copper pillars 104 to connect circuit pads or terminals to chip pads. LH technology requires special copper layers on both terminals and chip pads to withstand the high temperatures of the laser drilling process. Without this protective layer, the laser could melt the soldered terminals or aluminum chip pads, damaging the product. Furthermore, if grinding is used instead, cracks may form at the contact surfaces of the different materials, severely impacting the quality and reliability of the final product.

[0048] refer to Figure 4 , Figure 4 This is a schematic diagram of the packaging structure 4a according to an embodiment of the present invention.

[0049] like Figure 4 As shown, the packaging structure 4a of this utility model may include a first substrate 201 and a second substrate 202.

[0050] The first substrate 201 includes a first molding layer 2011, a first passive component 2012 embedded in the first molding layer 2011, and a first circuit layer 2013. One end of the first passive component 2012 is connected to the first circuit layer 2013, and the other end is exposed by the first molding layer 2011.

[0051] The second substrate 202 is disposed above the first substrate 201. The second substrate 202 includes a second molding layer 2021 and a second passive element 2022 embedded in the second molding layer 2021. One end of the second passive element 2022 is exposed by the second molding layer 2021 and is electrically connected to the first circuit layer 2013 of the first substrate 201.

[0052] Here, the first substrate 201 and the second substrate 202 may include organic and / or inorganic materials. Organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0053] The first mold sealing layer 2011 and the second mold sealing layer 2021 can be formed from various molding compounds. For example, the molding compound can be one or more of the following materials in combination: epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0054] The first passive element 2012 and the second passive element 2022 may include, for example, resistors, capacitors, inductors, transformers, etc., without specific limitations.

[0055] Here, the first passive element 2012 and the second passive element 2022 can be different passive elements or the same passive element.

[0056] Here, the first mold cover 2011 can protect the first passive component 2012 and the first circuit layer 2013.

[0057] Similarly, the second mold sealing layer 2021 can protect the second passive element 2022.

[0058] Here, on the one hand, by electrically connecting one end of the second passive element 2022 to the first circuit layer 2013 of the first substrate 201, the electrical connection between the first substrate 201 and the second substrate 202 can be achieved through the first passive element 2012 and the second passive element 2022. That is, the first passive element 2012 and the second passive element 2022 can be regarded as copper pillars (electrical connectors) to achieve the electrical connection between the first substrate 201 and the second substrate 202. On the other hand, by fabricating multilayer substrates layer by layer, a multilayer embedded structure can be achieved, and the problem of product damage caused by laser through-hole technology can be avoided.

[0059] In some alternative embodiments, the package structure 4a may also include metal paste 204 disposed between the second passive element 2022 and the first circuit layer 2013.

[0060] Thus, the electrical connection and mechanical fixation between the second passive element 2022 and the first circuit layer 2013 can be achieved through the metal paste 204.

[0061] In some alternative embodiments, the first substrate 201 may further include a first active element 2014, which is embedded within the first molding layer 2011.

[0062] Here, the first mold sealing layer 2011 can also protect the first active element 2014.

[0063] In some alternative embodiments, metal paste 204 may also be provided between the first active element 2014 and the first circuit layer 2013.

[0064] Thus, the electrical connection and mechanical fixation between the first active element 2014 and the first circuit layer 2013 can also be achieved through the metal paste 204.

[0065] In some alternative implementations, there is a gap between the first active element 2014 and the first passive element 2012.

[0066] In this way, the independence and stability of the functions of the first active element 2014 and the first passive element 2012 can be ensured, direct electrical interference between the two can be avoided, and the gap can also facilitate heat dissipation, preventing excessive local temperature from affecting the performance or lifespan of the first active element 2014 and the first passive element 2012.

[0067] In some alternative implementations, the second passive element 2022 is disposed above the first passive element 2012.

[0068] This provides a shorter conductive path, shortens the electrical signal transmission distance, reduces line impedance, and thus improves the overall circuit response speed and performance.

[0069] In some alternative embodiments, in the first substrate 201, two adjacent first active elements 2014 are separated by a first passive element 2012.

[0070] In this way, signal crosstalk or current interference between two adjacent active elements 2014 can be prevented, thereby improving the stability and performance of the overall circuit. Furthermore, placing the first passive element 2012 between two adjacent first active elements 2014 can also provide additional mechanical support for the package structure 4a, increasing the overall stability of the package structure 4a.

[0071] In some alternative embodiments, the first substrate 201 further includes a fourth circuit layer 2015, and one end of the first passive element 2012 exposed by the first molding layer 2011 is electrically connected to the fourth circuit layer 2015 of the first substrate 201.

[0072] In some alternative embodiments, the second substrate 202 may further include a second active element 2024 embedded within the second molding layer 2021.

[0073] Here, the second mold sealing layer 2021 can also protect the second active element 2024.

[0074] In some alternative implementations, the second active element 2024 is disposed above the first active element 2014.

[0075] Thus, the integration of the second active element 2024 with the first active element 2014 in the vertical direction increases the package density. The stacked structure also helps to shorten the interconnection distance between the second active element 2024 and the first active element 2014, thereby improving signal transmission speed and overall circuit performance.

[0076] In some alternative embodiments, the first active element 2014 is electrically connected to the first substrate 201, and the second active element 2024 is electrically connected to the first substrate 201.

[0077] Thus, an electrical connection between the first active element 2014 and the second active element 2024 can be achieved through the first substrate.

[0078] In some alternative embodiments, the second substrate 202 may further include a second circuit layer 2023, with the other end of the second passive element 2022 electrically connected to the second circuit layer 2023.

[0079] Here, one end of the second passive element 2022 is electrically connected to the first circuit layer 2013 of the first substrate 201, and the other end is electrically connected to the second circuit layer 2023.

[0080] Thus, through the second passive element 2022, an electrical connection can be achieved between the first circuit layer 2013 and the second circuit layer 2023, that is, an electrical connection can be achieved between the first substrate 201 and the second substrate 202.

[0081] In some alternative embodiments, the packaging structure 4a may further include a third substrate 203 disposed above the second substrate 202, including a third passive element 2032 electrically connected to the second substrate 202.

[0082] In some optional embodiments, the third substrate 203 may further include a third molding layer 2031 and a third active element 2034, wherein the third active element 2034 and the third passive element 2032 are embedded in the third molding layer 2031, and one end of the third passive element 2032 is exposed by the third molding layer 2031 and electrically connected to the second circuit layer 2023 of the second substrate 202.

[0083] In some alternative embodiments, the third substrate 203 may also include a third circuit layer 2033, with the other end of the third passive element 2032 electrically connected to the third circuit layer 2033.

[0084] Similarly, the third substrate 203 may include organic and / or inorganic materials. Organic materials may include, for example, polyamide (PA), polyimide (PI), epoxy resin, poly-p-phenylene benzobisoxazole (PBO) fiber, FR-4 epoxy glass cloth laminate, PP (PrePreg, also known as prepreg or semi-cured resin, semi-cured sheet), ABF (Ajinomoto Build-up Film), etc. Inorganic materials may include, for example, silicon (Si), glass, ceramic, silicon oxide, silicon nitride, tantalum oxide, etc.

[0085] The third molding layer 2031 can be formed from various molding compounds. For example, the molding compound can be one or more of the following materials: epoxy resin, filler, catalyst, pigment, release agent, flame retardant, coupling agent, hardener, low stress absorber, adhesion promoter, ion trapping agent, etc.

[0086] The third passive element 2032 may include, for example, resistors, capacitors, inductors, transformers, etc., without specific limitations.

[0087] The third passive element 2032 can be a different passive element from the first passive element 2012 and the second passive element 2022, or it can be the same passive element.

[0088] Here, the third module sealing layer 2031 can protect the third active element 2034, the third passive element 2032 and the third circuit layer 2033.

[0089] One end of the third passive element 2032 is electrically connected to the second circuit layer 2023 of the second substrate 202, and the other end is electrically connected to the third circuit layer 2033.

[0090] Thus, the electrical connection between the second circuit layer 2023 and the third circuit layer 2033 can be achieved through the third passive element 2032, that is, the electrical connection between the second substrate 202 and the third substrate 203 is achieved.

[0091] Similarly, metal paste 204 can also be disposed between the third passive element 2032 and the third circuit layer 2033. In this way, the electrical connection and mechanical fixation between the third active element 2032 and the third circuit layer 2033 can also be achieved through metal paste 204.

[0092] Here, at least one substrate structure similar to the first substrate, the second substrate, and the third substrate can also be superimposed on the third substrate 203, without limitation.

[0093] In this way, by fabricating multi-layer substrates one by one, a multi-layer embedded structure can be achieved, and the problem of product damage caused by laser through-hole technology can be avoided.

[0094] In some alternative embodiments, the packaging structure 4a may also include a fourth active element 205, a fourth passive element 206, and a fourth molding layer 207.

[0095] The fourth active element 205 and the fourth passive element 206 are disposed above the third substrate 203 and electrically connected to the third substrate 203.

[0096] The fourth mold sealing layer 207 is configured to cover the fourth active element 205 and the fourth passive element 206.

[0097] Here, the fourth molding layer 207 can be formed from various molding compounds, which will not be elaborated here.

[0098] The fourth mold sealing layer 207 can protect the fourth active element and the fourth passive element 206.

[0099] It should be noted that when at least one substrate structure similar to the first substrate, the second substrate and the third substrate is superimposed on the third substrate 203, the fourth active element 205 and the fourth passive element 206 can be disposed on the top substrate and electrically connected to the top substrate.

[0100] In some alternative embodiments, the package structure 4a may also include solder balls 208 disposed below the first substrate 201.

[0101] In this way, electrical connection and mechanical fixation between the package structure 4a and the external circuit can be achieved.

[0102] The above describes the packaging structure 4a of one embodiment of the present invention.

[0103] refer to Figure 5 , Figure 5 This is a schematic diagram of the packaging structure 5a according to an embodiment of the present invention. Figure 5 The package structure 5a shown is similar to Figure 4 The packaging structure 4a shown differs in that:

[0104] The first substrate 201, the second substrate 202, and the third substrate 203 may not include the first active element 2014, the second active element 2024, and the third active element 2034.

[0105] The same effect as the packaging structure 4a can be achieved. On the one hand, one end of the second passive element 2022 is electrically connected to the first circuit layer 2013 of the first substrate 201. The first passive element 2012 and the second passive element 2022 can be used to achieve the electrical connection between the first substrate 201 and the second substrate 202. That is, the first passive element 2012 and the second passive element 2022 can be regarded as copper pillars (electrical connectors) to achieve the electrical connection between the first substrate 201 and the second substrate 202. On the other hand, by fabricating multi-layer substrates layer by layer, a multi-layer embedded structure can be achieved, and the problem of product damage caused by laser through-hole technology can be avoided.

[0106] The above describes the packaging structure 5a of one embodiment of the present invention.

[0107] refer to Figure 6 , Figure 6 This is a schematic diagram of the packaging structure 6a according to an embodiment of the present invention. Figure 6 The package structure 6a shown is similar to Figure 4 The packaging structure 4a shown differs in that:

[0108] The first passive element 2012, the second passive element 2022, and the third passive element 2032 in the first substrate 201, the second substrate 202, and the third substrate 203 are replaced with metal pillars 213.

[0109] The same effect as the packaging structure 4a can be achieved. By fabricating multi-layer substrates layer by layer, a multi-layer embedded structure can be achieved, which can avoid the problem of product damage caused by laser through-hole technology. At the same time, the metal pillar 213 has good mechanical strength and thermal conductivity, which helps to improve the reliability of the packaging structure 6a.

[0110] The above describes the packaging structure 6a of one embodiment of the present invention.

[0111] refer to Figure 7 , Figure 7This is a schematic diagram of the packaging structure 7a according to an embodiment of the present invention. Figure 7 The package structure 7a shown is similar to Figure 4 The packaging structure 4a shown differs in that:

[0112] The first passive element 2012, the second passive element 2022 and the third passive element 2032 in the first substrate 201 and the second substrate 202 are replaced with metal pillars 213, and the first substrate 201 and the second substrate 202 do not include the first active element 2014 and the second active element 2024.

[0113] The same effect as the packaging structure 4a can be achieved. By fabricating multi-layer substrates layer by layer, a multi-layer embedded structure can be achieved, while avoiding the problem of product damage caused by laser through-hole technology.

[0114] The above describes the packaging structure 7a of one embodiment of the present invention.

[0115] refer to Figures 8-28 , Figures 8-28 This is a schematic diagram of the manufacturing steps of the packaging structure 4a according to an embodiment of the present invention.

[0116] refer to Figure 8 It provides a first carrier 209, a first dielectric layer 210 and a fourth circuit layer 2015.

[0117] Here, the first dielectric layer 210 can be disposed on the first carrier 209, and the fourth circuit layer 2015 can be disposed on the first dielectric layer 210.

[0118] refer to Figure 9 A first passive element 2012 and a first active element 2014 are provided on the fourth circuit layer 2015.

[0119] Here, the first passive element 2012 and the first active element 2014 can be disposed on the fourth circuit layer 2015 using metal paste 204.

[0120] refer to Figure 10 It provides a second carrier 211, a second dielectric layer 212 and a first circuit layer 2013, and connects one end of the first passive element 2012 to the first circuit layer 2013.

[0121] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the first circuit layer 2013 can be disposed on the second dielectric layer 212.

[0122] refer to Figure 11Filler material is filled between the first circuit layer 2013 and the fourth circuit layer 2015 to form the first molding layer 2011, thereby forming the first substrate 201.

[0123] The first substrate 201 may include a first molding layer 2011, a first passive element 2012, a first circuit layer 2013, a first active element 2014, and a fourth circuit layer 2015.

[0124] refer to Figure 12 Remove the first carrier 209 and the second carrier 211.

[0125] refer to Figure 13 Solder ball openings are fabricated on the first dielectric layer 210 and C4 (Controlled Collapse Chip Connection) openings are fabricated on the second dielectric layer 212.

[0126] refer to Figure 14 When only the first substrate 201 is present, a fourth active element 205, a fourth passive element 206 and a fourth molding layer 207 can be provided on the second dielectric layer 212, and solder balls 208 can be provided on the first dielectric layer 210.

[0127] Specifically, the C4 aperture is aligned with the first circuit layer 2013, enabling electrical connection between the fourth active element 205, the fourth passive element 206, and the first circuit layer 2013. The fourth molded layer 207 can cover the fourth active element 205 and the fourth passive element 206. Furthermore, solder balls 208 can be placed at the solder ball openings in the first dielectric layer 210 to achieve, for example,... Figure 14 The encapsulation structure shown is electrically connected to and mechanically fixed to the external circuit.

[0128] refer to Figure 15 When it is necessary to set the second substrate 202 on the first substrate 201, it can be done Figure 12 The second dielectric layer 212 is further removed on this basis.

[0129] refer to Figure 16 A second passive element 2022 and a second active element 2024 are provided on the first line layer 2013.

[0130] Similarly, the second passive element 2022 and the second active element 2024 can be disposed on the first circuit layer 2013 by means of metal paste 204.

[0131] refer to Figure 17 It provides a second carrier 211, a second dielectric layer 212 and a second circuit layer 2023, and connects one end of the second passive element 2022 to the second circuit layer 2023.

[0132] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the second circuit layer 2023 can be disposed on the second dielectric layer 212.

[0133] refer to Figure 18 A filler material is filled between the first circuit layer 2013 and the second circuit layer 2023 to form a second molding layer 2021, thereby forming a second substrate 202.

[0134] The second substrate 202 may include a second molding layer 2021, a second passive element 2022, a second circuit layer 2023, and a second active element 2024.

[0135] refer to Figure 19 Remove the second carrier 211.

[0136] refer to Figure 20 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0137] refer to Figure 21 A fourth active element 205, a fourth passive element 206 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0138] refer to Figure 22 When a third substrate 203 needs to be disposed on the second substrate 202, it can be... Figure 19 The second dielectric layer 212 is further removed on this basis.

[0139] refer to Figure 23 A third passive element 2032 and a third active element 2034 are provided on the second line layer 2023.

[0140] Similarly, the third passive element 2032 and the third active element 2034 can be disposed on the second circuit layer 2023 by means of metal paste 204.

[0141] refer to Figure 24 It provides a second carrier 211, a second dielectric layer 212 and a third circuit layer 2033, and connects one end of the third passive element 2032 to the third circuit layer 2033.

[0142] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the third circuit layer 2033 can be disposed on the second dielectric layer 212.

[0143] refer to Figure 25 Filler material is filled between the second circuit layer 2023 and the third circuit layer 2033 to form a third molding layer 2031, thereby forming a third substrate 203.

[0144] The third substrate 203 may include a third molding layer 2031, a third passive element 2032, a third circuit layer 2033, and a third active element 2034.

[0145] refer to Figure 26 Remove the second carrier 211.

[0146] refer to Figure 27 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0147] refer to Figure 28 A fourth active element 205, a fourth passive element 206 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0148] refer to Figure 29-49 , Figures 29-49 This is a schematic diagram of the manufacturing steps of the packaging structure 5a according to an embodiment of the present invention.

[0149] refer to Figure 29 It provides a first carrier 209, a first dielectric layer 210 and a fourth circuit layer 2015.

[0150] Here, the first dielectric layer 210 can be disposed on the first carrier 209, and the fourth circuit layer 2015 can be disposed on the first dielectric layer 210.

[0151] refer to Figure 30 A first passive element 2012 is set on the fourth circuit layer 2015.

[0152] Here, the first passive element 2012 can be placed on the fourth circuit layer 2015 using metal paste 204.

[0153] refer to Figure 31 It provides a second carrier 211, a second dielectric layer 212 and a first circuit layer 2013, and connects one end of the first passive element 2012 to the first circuit layer 2013.

[0154] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the first circuit layer 2013 can be disposed on the second dielectric layer 212.

[0155] refer to Figure 32 Filler material is filled between the first circuit layer 2013 and the fourth circuit layer 2015 to form the first molding layer 2011, thereby forming the first substrate 201.

[0156] The first substrate 201 may include a first molding layer 2011, a first passive component 2012, a first circuit layer 2013, and a fourth circuit layer 2015.

[0157] refer to Figure 33 Remove the first carrier 209 and the second carrier 211.

[0158] refer to Figure 34 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0159] refer to Figure 35 When only the first substrate 201 is present, a fourth active element 205 and a fourth molding layer 207 can be provided on the second dielectric layer 212, and solder balls 208 can be provided on the first dielectric layer 210.

[0160] refer to Figure 36 When it is necessary to set the second substrate 202 on the first substrate 201, it can be done Figure 33 The second dielectric layer 212 is further removed on this basis.

[0161] refer to Figure 37 A second passive element 2022 is set on the first line layer 2013.

[0162] refer to Figure 38 It provides a second carrier 211, a second dielectric layer 212 and a second circuit layer 2023, and connects one end of the second passive element 2022 to the second circuit layer 2023.

[0163] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the second circuit layer 2023 can be disposed on the second dielectric layer 212.

[0164] refer to Figure 39 A filler material is filled between the first circuit layer 2013 and the second circuit layer 2023 to form a second molding layer 2021, thereby forming a second substrate 202.

[0165] Here, one end of the second passive element 2022 is exposed by the second molding layer 2021 and electrically connected to the first circuit layer 2013 of the first substrate 201. The second molding layer 2021 can protect the second passive element 2022 and the second circuit layer 2023.

[0166] The second substrate 202 may include a second molding layer 2021, a second passive element 2022, and a second circuit layer 2023.

[0167] refer to Figure 40 Remove the second carrier 211.

[0168] refer to Figure 41 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0169] refer to Figure 42 A fourth active element 205 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0170] refer to Figure 43 When a third substrate 203 needs to be disposed on the second substrate 202, it can be... Figure 40 The second dielectric layer 212 is further removed on this basis.

[0171] refer to Figure 44 A third passive element 2032 is set on the second line layer 2023.

[0172] Similarly, the third passive element 2032 can be disposed on the second circuit layer 2023 using metal paste 204.

[0173] refer to Figure 45 It provides a second carrier 211, a second dielectric layer 212 and a third circuit layer 2033, and connects one end of the third passive element 2032 to the third circuit layer 2033.

[0174] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the third circuit layer 2033 can be disposed on the second dielectric layer 212.

[0175] refer to Figure 46 Filler material is filled between the second circuit layer 2023 and the third circuit layer 2033 to form a third molding layer 2031, thereby forming a third substrate 203.

[0176] The third substrate 203 may include a third molding layer 2031, a third passive element 2032, and a third circuit layer 2033.

[0177] refer to Figure 47 Remove the second carrier 211.

[0178] refer to Figure 48 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0179] refer to Figure 49 A fourth active element 205 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0180] refer to Figures 50-70 , Figures 50-70This is a schematic diagram of the manufacturing steps of the packaging structure 6a according to an embodiment of the present invention.

[0181] refer to Figure 50 The system provides a second carrier 211, a second dielectric layer 212 and a first circuit layer 2013, and provides metal pillars 213 on the first circuit layer 2013 and metal paste 204 on the metal pillars 213.

[0182] refer to Figure 51 It provides a first carrier 209, a first dielectric layer 210, and a fourth circuit layer 2015, and a first active element 2014 disposed on the fourth circuit layer 2015.

[0183] refer to Figure 52 ,Will Figure 50 and Figure 51 The structure is bonded so that the first circuit layer 2013 is electrically connected to the fourth circuit layer 2015 through metal pillars 213 and metal paste 204.

[0184] refer to Figure 53 Filler material is filled between the first circuit layer 2013 and the fourth circuit layer 2015 to form the first molding layer 2011, thereby forming the first substrate 201.

[0185] The first substrate 201 may include a first molding layer 2011, a metal pillar 213, a first circuit layer 2013, a first active element 2014, and a fourth circuit layer 2015.

[0186] refer to Figure 54 Remove the first carrier 209 and the second carrier 211.

[0187] refer to Figure 55 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0188] refer to Figure 56 When only the first substrate 201 is present, a fourth active element 205 and a fourth molding layer 207 can be provided on the second dielectric layer 212, and solder balls 208 can be provided on the first dielectric layer 210.

[0189] refer to Figure 57 When it is necessary to set the second substrate 202 on the first substrate 201, it can be done Figure 54 The second dielectric layer 212 is further removed on this basis.

[0190] refer to Figure 58 A second active element 2024 is provided on the first line layer 2013.

[0191] refer to Figure 59The system provides a second carrier 211, a second dielectric layer 212 and a first circuit layer 2013, and provides metal pillars 213 on the first circuit layer 2013 and metal paste 204 on the metal pillars 213.

[0192] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the second circuit layer 2023 can be disposed on the second dielectric layer 212. The second circuit layer 2023 is electrically connected to the first circuit layer 2013 through metal pillars 213 and metal paste 204.

[0193] refer to Figure 60 A filler material is filled between the first circuit layer 2013 and the second circuit layer 2023 to form a second molding layer 2021, thereby forming a second substrate 202.

[0194] Here, the second substrate 202 may include a second molding layer 2021, a metal pillar 213, a second circuit layer 2023, and a second active element 2024.

[0195] refer to Figure 61 Remove the second carrier 211.

[0196] refer to Figure 62 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0197] refer to Figure 63 A fourth active element 205 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0198] refer to Figure 64 When a third substrate 203 needs to be disposed on the second substrate 202, it can be... Figure 61 The second dielectric layer 212 is further removed on this basis.

[0199] refer to Figure 65 A third active element 2034 is set on the second line layer 2023.

[0200] refer to Figure 66 The system provides a second carrier 211, a second dielectric layer 212 and a third circuit layer 2033, and provides metal pillars 213 on the third circuit layer 2013 and metal paste 204 on the metal pillars 213.

[0201] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the third circuit layer 2033 can be disposed on the second dielectric layer 212. The third circuit layer 2033 is electrically connected to the second circuit layer 2023 through metal pillars 213 and metal paste 204.

[0202] refer to Figure 67 Filler material is filled between the second circuit layer 2023 and the third circuit layer 2033 to form a third molding layer 2031, thereby forming a third substrate 203.

[0203] The third substrate 203 may include a third molding layer 2031, metal pillars 213, a third circuit layer 2033, and a third active element 2034.

[0204] refer to Figure 68 Remove the second carrier 211.

[0205] refer to Figure 69 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0206] refer to Figure 70 A fourth active element 205 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0207] refer to Figures 71-89 , Figures 71-89 This is a schematic diagram of the manufacturing steps of the packaging structure 7a according to an embodiment of the present invention.

[0208] refer to Figure 71 It provides a second carrier 211 and a second dielectric layer 212.

[0209] The second dielectric layer 212 is disposed on the second carrier 211.

[0210] refer to Figure 72 A seed layer 214 is provided in the second dielectric layer 212.

[0211] refer to Figure 73 A dry film 215 is coated on the seed layer 214, and the required pattern area of ​​the first circuit layer 2013 is formed by exposure and development processes, thereby exposing the area where the first circuit layer 2013 is to be formed.

[0212] refer to Figure 74 The first circuit layer 2013 is formed by electroplating within the patterned area defined after development.

[0213] refer to Figure 75 A dry film 215 is coated again on the first circuit layer 2013, and the required pattern area of ​​metal pillars 213 and metal paste 204 is formed by exposure and development process, thereby exposing the area where metal pillars 213 and metal paste 204 are to be formed.

[0214] refer to Figure 76 Metal pillars 213 and metal paste 204 are formed by electroplating within the patterned area defined after development.

[0215] refer to Figure 77 Remove the remaining dry film and cut it to form individual pieces, such as... Figure 77 The structure shown.

[0216] refer to Figure 78 It provides a first carrier 209, a first dielectric layer 210 and a fourth circuit layer 2015.

[0217] refer to Figure 79 ,Will Figure 77 and Figure 78 The structure is bonded so that the first circuit layer 2013 is electrically connected to the fourth circuit layer 2015 through metal pillars 213 and metal paste 204.

[0218] refer to Figure 80 Filler material is filled between the first circuit layer 2013 and the fourth circuit layer 2015 to form the first molding layer 2011, thereby forming the first substrate 201.

[0219] The first substrate 201 may include a first molding layer 2011, metal pillars 213, a first circuit layer 2013 and a fourth circuit layer 2015.

[0220] refer to Figure 81 Remove the first carrier 209 and the second carrier 211.

[0221] refer to Figure 82 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0222] refer to Figure 83 When only the first substrate 201 is present, a fourth active element 205 and a fourth molding layer 207 can be provided on the second dielectric layer 212, and solder balls 208 can be provided on the first dielectric layer 210.

[0223] refer to Figure 84 When it is necessary to set the second substrate 202 on the first substrate 201, it can be done Figure 81 The second dielectric layer 212 is further removed on this basis.

[0224] refer to Figure 85 The system provides a second carrier 211, a second dielectric layer 212, and a second circuit layer 2023, and provides metal pillars 213 on the second circuit layer 2023 and metal paste 204 on the metal pillars 213.

[0225] Here, the second dielectric layer 212 can be disposed on the second carrier 211, and the second circuit layer 2023 can be disposed on the second dielectric layer 212. The second circuit layer 2023 is electrically connected to the first circuit layer 2013 through metal pillars 213 and metal paste 204.

[0226] refer to Figure 86 A filler material is filled between the first circuit layer 2013 and the second circuit layer 2023 to form a second molding layer 2021, thereby forming a second substrate 202.

[0227] Here, the second substrate 202 may include a second molding layer 2021, metal pillars 213, and a second circuit layer 2023.

[0228] refer to Figure 87 Remove the second carrier 211.

[0229] refer to Figure 88 Solder ball openings are formed on the first dielectric layer 210 and C4 openings are formed on the second dielectric layer 212.

[0230] refer to Figure 89 A fourth active element 205 and a fourth molding layer 207 are disposed on the second dielectric layer 212, and solder balls 208 are disposed on the first dielectric layer 210.

[0231] Although the present invention has been described and illustrated with reference to specific embodiments thereof, such description and illustration are not limiting of the invention. It will be readily understood by those skilled in the art that various changes can be made and equivalent elements can be substituted within the embodiments without departing from the true spirit and scope of the invention as defined by the appended claims. Illustrations may not be drawn to scale. Differences may exist between the technical representation of the invention and actual implementation due to variables in the manufacturing process, etc. Other embodiments of the invention may exist that are not specifically described. The description and illustrations should be considered illustrative rather than restrictive. Modifications can be made to adapt particular circumstances, materials, compositions, methods, or processes to the objectives, spirit, and scope of the invention. All such modifications fall within the scope of the appended claims. While the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations can be combined, subdivided, or reordered to form equivalent methods without departing from the teachings of the invention. Therefore, unless specifically indicated herein, the order and grouping of operations do not limit the invention.

Claims

1. A packaging structure, characterized in that, The packaging structure includes: The first substrate includes a first molding layer, a first passive component embedded in the first molding layer, and a first circuit layer, wherein one end of the first passive component is connected to the first circuit layer, and the other end is exposed by the first molding layer. A second substrate is disposed above the first substrate. The second substrate includes a second molding layer and a second passive element embedded in the second molding layer. One end of the second passive element is exposed by the second molding layer and electrically connected to the first circuit layer of the first substrate.

2. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: Metal paste is applied between the second passive element and the first circuit layer.

3. The packaging structure according to claim 1, characterized in that, The packaging structure further includes: A third substrate is disposed above the second substrate and includes a third passive element, which is electrically connected to the second substrate.

4. The packaging structure according to claim 1, characterized in that, The first substrate further includes a first active element, which is embedded within the first molding layer.

5. The packaging structure according to claim 4, characterized in that, The second substrate also includes a second active element, which is embedded within the second molding layer.

6. The packaging structure according to claim 3, characterized in that, The second substrate further includes a second circuit layer, and the other end of the second passive element is electrically connected to the second circuit layer.

7. The packaging structure according to claim 6, characterized in that, The third substrate further includes a third molding layer and a third active element, wherein the third active element and the third passive element are embedded in the third molding layer, and one end of the third passive element is exposed by the third molding layer and electrically connected to the second circuit layer of the second substrate.

8. The packaging structure according to claim 7, characterized in that, The third substrate further includes a third circuit layer, and the other end of the third passive element is electrically connected to the third circuit layer.

9. The packaging structure according to claim 4, characterized in that, There is a gap between the first active element and the first passive element.

10. The packaging structure according to claim 1, characterized in that, The second passive element is disposed above the first passive element.

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