Semiconductor package element

Abstract

The application discloses a semiconductor packaging element, which comprises an electronic integrated circuit, a mold sealing layer covering the electronic integrated circuit, a first circuit layer arranged above the mold sealing layer, a photonic integrated circuit arranged above the first circuit layer, the photonic integrated circuit being electrically connected to the electronic integrated circuit through the first circuit layer, and a light guide element arranged above the photonic integrated circuit, wherein the light guide element enables the photonic integrated circuit to vertically emit light towards the light guide element. The semiconductor packaging element is balanced, the risk of fracture of the photonic integrated circuit is reduced, and warping is reduced.

Description

Technical Field

[0001] This application relates to a semiconductor packaging element. Background Technology

[0002] Silicon photonics (SiPh) is an innovative technology that integrates optics and electronics onto a single chip, serving as a core technology for applications such as high-speed data transmission, precise sensing, and quantum computing. Photonic integrated circuits (PICs) are a key component, receiving laser light from a light source and converting the optical signal into a data signal usable in various applications through modulation, wavelength division, and photoelectric conversion. The structure of a photonic integrated circuit resembles an "optical highway," with its core being an optical path system composed of optical waveguides. These waveguides, made of high-refractive-index materials (such as silicon), are used to effectively confine and guide the transmission of light. When laser light from an external light source enters the waveguide, the optical signal is transmitted to a modulator, where an electrical signal is encoded into the optical signal through electro-optic or thermo-optic effects. The modulated optical signal continues to transmit, undergoing wavelength division or filtering, and finally reaches the detector, where it is converted back into an electrical signal for use by downstream circuits.

[0003] Figure 1 A schematic diagram of the bonding of a prior art electronic integrated circuit 11 and a photonic integrated circuit 12 is shown. Figure 2 It shows Figure 1 A magnified view of region A in the middle. See also... Figure 1 and Figure 2 In silicon photonics technology, during the hybrid bond process 100, pressure 110 and temperature 120 are applied to bond the copper pads 121 of the photonic integrated circuit 12 to the copper pads 111 of the electronic integrated circuit 11. However, due to the heating and recrystallization of the copper pads (e.g., 121), a protrusion occurs at the center point, causing the upper and lower parts to fail to bond and resulting in warpage. Furthermore, excessive pressure 110 can cause the lower photonic integrated circuit 12 to crack, while insufficient pressure 110 will prevent bonding. These problems pose a high risk when bonding electronic integrated circuits 11 and photonic integrated circuits 12 of different sizes, due to stress concentration. Whenever hybrid bonding is performed, the photonic integrated circuit 12 is at risk of cracking. Utility Model Content

[0004] To address the above problems, this application proposes a semiconductor packaging element, at least one balanced semiconductor packaging element, to reduce the risk of breakage of photonic integrated circuits and reduce warpage.

[0005] The technical solution of this application is implemented as follows:

[0006] According to one aspect of this application, a semiconductor packaging element is provided, comprising: an electronic integrated circuit and a molding layer covering the electronic integrated circuit; a first circuit layer stacked on top of the molding layer; a photonic integrated circuit stacked on top of the first circuit layer, wherein the photonic integrated circuit is electrically connected to the electronic integrated circuit through the first circuit layer; and a light guide element stacked on top of the photonic integrated circuit; wherein the light guide element causes the photonic integrated circuit to emit light perpendicularly toward the light guide element.

[0007] In some embodiments, the semiconductor package element further includes a second circuit layer, with the molding layer stacked on top of the second circuit layer.

[0008] In some embodiments, the semiconductor package element further includes a via that penetrates the photonic integrated circuit and is electrically connected to the first line layer.

[0009] In some embodiments, the side of the molding layer is flush with the side of the photonic integrated circuit.

[0010] In some embodiments, the semiconductor packaging element further includes a first conductive post that penetrates the molding layer and electrically connects the first circuit layer to the second circuit layer, and a second conductive post disposed above the electronic integrated circuit and electrically connects the electronic integrated circuit and the first circuit layer.

[0011] In some embodiments, the lower surface of the molding layer is flush with the lower surface of the electronic integrated circuit.

[0012] In some embodiments, the first conductive post is a copper post, and the second conductive post is a copper post.

[0013] In some embodiments, the semiconductor package element further includes a via disposed in the photonic integrated circuit and electrically connected to a first circuit layer located below the via, and the via is connected to a pad located above the via.

[0014] In some embodiments, the photonic integrated circuit further includes a waveguide connected to one of the pads and laterally oriented toward the light-guiding element.

[0015] In some embodiments, the waveguide is configured to laterally direct light from the photonic integrated circuit to the light-guiding element.

[0016] In some embodiments, the upper surface of the photonic integrated circuit is provided with a bump and recess, and the light guide element is connected to the photonic integrated circuit through the bump and recess.

[0017] In some embodiments, solder balls are disposed below the second circuit layer.

[0018] In some embodiments, the second conductive pillars are arranged on both sides of the electronic integrated circuit.

[0019] In some embodiments, the second conductive post is a cylinder that penetrates the upper and lower sides of the mold seal layer.

[0020] In some embodiments, the top surface of the second conductive post is flush with the top surface of the first conductive post, and the bottom surface of the second conductive post extends beyond the bottom surface of the first conductive post and contacts the second circuit layer.

[0021] In some embodiments, when viewed from above, the light guide element is surrounded by a photonic integrated circuit.

[0022] In some embodiments, along the vertical light emission direction, the projection of the electronic integrated circuit onto the bottom surface of the photonic integrated circuit falls within the bottom surface of the photonic integrated circuit.

[0023] In some embodiments, the upper surface of the pad is a flat plane.

[0024] In some embodiments, the upper surface of the pads is exposed relative to the photonic integrated circuit.

[0025] According to another aspect of this application, a semiconductor packaging element is provided, comprising: an electronic integrated circuit and a molding layer covering the electronic integrated circuit; a first circuit layer disposed above the molding layer along a first direction; a photonic integrated circuit disposed above the first circuit layer along the first direction, the photonic integrated circuit being electrically connected to the electronic integrated circuit through the first circuit layer; and a light guide element disposed above the photonic integrated circuit along the first direction; wherein the light guide element causes the photonic integrated circuit to emit light toward the light guide element along the first direction.

[0026] The beneficial effects of the above technical solution include at least: providing a balanced semiconductor packaging element, reducing the risk of photonic integrated circuit breakage, and reducing warping. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of the bonding of existing electronic integrated circuits and photonic integrated circuits is shown.

[0029] Figure 2 It shows Figure 1 An enlarged schematic diagram of region A in the middle.

[0030] Figure 3 A schematic cross-sectional view of a semiconductor package element according to some embodiments of this application is shown.

[0031] Figure 4 A schematic cross-sectional view of a silicon photonic device is shown.

[0032] Figure 5 , Figure 6 as well as Figure 7 A cross-sectional schematic diagram of another silicon photonic device is shown.

[0033] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 as well as Figure 15 A cross-sectional schematic diagram of the manufacturing process of a semiconductor packaged element according to some embodiments of this application is shown. Detailed Implementation

[0034] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application are within the scope of protection of this application.

[0035] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the present invention. These are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of the present invention. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0036] Furthermore, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0037] Figure 3 A schematic cross-sectional view of a semiconductor package element 200 according to some embodiments of this application is shown. See also Figure 3The semiconductor package element 200 includes: an electronic integrated circuit 210, and a molding layer 220 covering the electronic integrated circuit 210; a first circuit layer 230 stacked on top of the molding layer 220; a photonic integrated circuit 240 stacked on top of the first circuit layer 230, and the photonic integrated circuit 240 is electrically connected to the electronic integrated circuit 210 through the first circuit layer 230; and a light guide element 250 stacked on top of the photonic integrated circuit 240; wherein the light guide element 250 causes the photonic integrated circuit 240 to emit light perpendicularly toward the light guide element 250. Figure 3 The arrows in the diagram illustrate the light path 1000 of light emitted from the photonic integrated circuit 240 after passing through the light guide element 250, with the arrow direction indicating the orientation of the light. However, it is understood that in some embodiments, the light guide element 250 can receive perpendicularly incident light and transmit it to the photonic integrated circuit 240. In this case, the arrow direction of the light path 1000 should be aligned with... Figure 3 The orientation shown is opposite. Furthermore, the aforementioned stacking is along, for example... Figure 3 The electronic integrated circuit 210 and the photonic integrated circuit 240 are stacked vertically upwards. By connecting the electronic integrated circuit 210 and the photonic integrated circuit 240 through the first circuit layer 230, the problems of warping caused by difficulty in bonding the electronic integrated circuit 210 and the photonic integrated circuit 240 due to the use of hybrid bonding and the photonic integrated circuit 240 being prone to breakage due to excessive pressure are at least avoided. Furthermore, in the prior art, the photonic integrated circuit 240 emits light horizontally. By using a light guide element 250 to make the photonic integrated circuit 240 emit light vertically upwards, and by setting the stacked structure in this way, the overall thickness of the semiconductor package element 200 can be further increased, and the risk of breakage of the photonic integrated circuit 240 can be further reduced. At the same time, the vertical upward light emission of the photonic integrated circuit 240 in conjunction with the light guide element 250 enables the semiconductor package element 200, as a silicon photonic device, to achieve better three-dimensional (3D) packaging design.

[0038] See below. Figure 3In some embodiments, the semiconductor package element 200 further includes a second wiring layer 260, with a molding layer 220 stacked above the second wiring layer 260. The semiconductor package element may also include vias 270 that penetrate the photonic integrated circuit 240 and are electrically connected to the first wiring layer 230. It can be seen that three vias 270 are illustrated in the figure; however, the number of vias 270 can be reasonably selected according to the actual wiring requirements. In some embodiments, the side of the molding layer 220 is flush with the side of the photonic integrated circuit 240. In fact, the sides of the second wiring layer 260, the molding layer 220, the first wiring layer 230, and the photonic integrated circuit 240 can all be flush. The semiconductor package element 200 may also include a first conductive post 281 that penetrates the molding layer 220 and electrically connects the first wiring layer 230 to the second wiring layer 260, and a second conductive post 282 disposed above the electronic integrated circuit 210 and electrically connecting the electronic integrated circuit 210 and the first wiring layer 230. Figure 3 The diagram illustrates multiple first conductive pillars 281 and second conductive pillars 282. The lower surface of the molding layer 220 may be flush with the lower surface of the electronic integrated circuit 210. In some embodiments, the first conductive pillars 281 and second conductive pillars 282 are both copper pillars, but other suitable conductive materials may also be used to form the first conductive pillars 281 and second conductive pillars 282. The second conductive pillars 282 may be arranged on both sides of the electronic integrated circuit 210. Furthermore, in some embodiments, the second conductive pillars 282 are cylinders penetrating the upper and lower sides of the molding layer 220, and the top surface of the second conductive pillars 282 may be flush with the top surface of the first conductive pillars 281, while the bottom surface of the second conductive pillars 282 extends beyond the bottom surface of the first conductive pillars 281 and contacts the second circuit layer 260. The vias 270 disposed in the photonic integrated circuit 240 may also be connected to the pads 290 located above the vias 270. In fact, the pads 290 may be disposed on the upper surface of the photonic integrated circuit 240, and the vias 270 penetrate the photonic integrated circuit 240 as described above. However, pad 290 can be as Figure 3As shown, a via 270 is embedded in the photonic integrated circuit 240 and extends vertically downward from the lower surface of the pad 290 to the lower surface of the photonic integrated circuit 240. In some embodiments, the photonic integrated circuit 240 further includes a waveguide 310 connected to one of the pads 290 and laterally directed toward the light guide element 250. In some embodiments, the upper surface of the pad 290 is configured as a flat plane. In some embodiments, the upper surface of the pad 290 is exposed relative to the photonic integrated circuit 240. The waveguide 310 may be made of a material with a high refractive index, such as silicon. In some embodiments, the waveguide 310 is configured to laterally direct light from the photonic integrated circuit 240 toward the light guide element 250, and the waveguide 310 may also be configured to laterally direct light from the light guide element 250 toward a light receiver of the photonic integrated circuit 240. The upper surface of the photonic integrated circuit 240 may also be provided with a bump 320 through which the light guide element 250 is fitted and connected to the photonic integrated circuit 240. Since the light guide element 250 is not easily bonded to the upper surface of the photonic integrated circuit 240, the bonding force between the light guide element 250 and the photonic integrated circuit 240 can be strengthened by providing the protrusions and recesses 320 to cooperate with the light guide element 250. Furthermore, because the light coupling of the light guide element 250 is easily misaligned, strengthening the bonding force between the light guide element 250 and the photonic integrated circuit 240 allows the light guide element 250 to be precisely positioned at the light emission location, ensuring that the light path 1000 remains unchanged. In fact, the light guide element 250 consists of a glass assembly 251 and optical adhesive 252, with the glass assembly 251 bonded to the upper surface of the photonic integrated circuit 240 via the optical adhesive 252. In some embodiments, the optical path 1000 may be as follows: light is incident laterally from the waveguide 310 onto the glass assembly 251, then its direction is changed by a prism (not shown) disposed within the glass assembly 251 and located on its lower surface, so that it is incident on the upper surface of the glass assembly 251 and reflected by the upper surface of the glass assembly 251 to other prisms. This process of incident light through multiple prisms and incident light onto the upper surface of the glass assembly 251 and reflected by the upper surface of the glass assembly 251 is repeated, and finally, the light is emitted vertically upward from the glass assembly 251. In some embodiments, solder balls 330 are also disposed below the second circuit layer 260 for subsequent connection to other devices. When viewed from above, the light guide element 250 may be surrounded by the photonic integrated circuit 240. In some embodiments, along the direction of vertical light emission, the projection of the electronic integrated circuit 210 onto the bottom surface of the photonic integrated circuit 240 falls within the bottom surface of the photonic integrated circuit 240.

[0039] This application also provides a semiconductor package element 200, which can be seen together with it. Figure 3To understand this, the semiconductor package element 200 includes: an electronic integrated circuit 210, and a molding layer 220 covering the electronic integrated circuit 210; a first circuit layer 230 disposed above the molding layer 220 along a first direction (also referred to as the aforementioned stacking direction F); a photonic integrated circuit 240 disposed above the first circuit layer 230 along the first direction, and the photonic integrated circuit 240 is electrically connected to the electronic integrated circuit 210 through the first circuit layer 230; and a light guide element 250 disposed above the photonic integrated circuit 240 along the first direction; wherein, the light guide element 250 causes the photonic integrated circuit 240 to emit light towards the light guide element 250 along the first direction.

[0040] Figure 4 A schematic cross-sectional view of a silicon photonic device 400 is shown. See also... Figure 4 The photonic integrated circuit 420 is connected to the electronic integrated circuit 410 via a line layer 430. A waveguide element 440 is also shown, allowing light from the photonic integrated circuit 420 to be emitted laterally horizontally, and the light path 1100 of the photonic integrated circuit 420 is shown. Although the photonic integrated circuit 420 and the electronic integrated circuit 410 avoid a series of problems associated with mixed bonding, compared to the semiconductor package element 200 according to embodiments of this application, the silicon photonic device 400 results in a longer photonic integrated circuit 420 because the waveguide element 440 of the photonic integrated circuit 420 needs to extend laterally to avoid the underlying line layer 430, and the sidewalls of the photonic integrated circuit 420 cannot be aligned with the line layer 430. Furthermore, it should be understood that neither the photonic integrated circuit 240 according to embodiments of this application, nor... Figure 4 The photonic integrated circuits 420 shown are relatively thin and fragile. Making the photonic integrated circuits 420 longer and having an irregular shape, as shown in the silicon photonic device 400, undoubtedly increases the risk of the photonic integrated circuits 420 breaking.

[0041] Figure 5 , Figure 6 as well as Figure 7 A cross-sectional schematic diagram of another silicon photonic device 500 is shown. See also Figure 5 The diagram illustrates a silicon photonic device 500, which includes an electronic integrated circuit 510 and a photonic integrated circuit 520, connected by a hybrid bonding method. It is understood that to achieve the lateral and then vertical emission of light from the photonic integrated circuit 520 via a waveguide 540, the photonic integrated circuit 520 is elongated, and a light guide element 540 is disposed on the upper surface of the photonic integrated circuit 520, adjacent to the electronic integrated circuit 510, through which light is emitted vertically. Figure 5 The optical path 1200 of the photonic integrated circuit 520 is shown. See also... Figure 6To avoid the mixed bonding of the electronic integrated circuit 510 and the photonic integrated circuit 520, which would make it difficult for the electronic integrated circuit 510 and the photonic integrated circuit 520 to bond and cause the photonic integrated circuit 520 to break easily under excessive pressure, a molding layer 550 can be provided to mold the light guide element 540 and the electronic integrated circuit 510, exposing the upper surface of the light guide element 540. By providing the molding layer 550, the structure of the silicon photonic device 500 is strengthened and the risk of breakage of the photonic integrated circuit 520 is reduced. Further, see... Figure 7 To further enhance the structure of the silicon photonic device 500, a dummy semiconductor layer 560 can be stacked on top of the molding layer 550. However, regardless of... Figure 5 , Figure 6 Or Figure 7 Due to the hybrid bonding between the electronic integrated circuit 510 and the photonic integrated circuit 520, whether only one molding layer 550 is added, or both a molding layer 550 and a pseudo-semiconductor layer 560 are added, the photonic integrated circuit 520 faces the risk of cracking due to excessive pressure. Furthermore, by elongating the photonic integrated circuit 520 and placing the electronic integrated circuit 510 adjacent to the light guide element 540, as mentioned above, whether it is the photonic integrated circuit 240 according to the embodiments of this application, or... Figures 5 to 7 The photonic integrated circuits 520 shown are relatively thin and fragile. Making the photonic integrated circuits 520 longer undoubtedly increases the risk of breakage.

[0042] Figure 8 , Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 as well as Figure 15 A schematic cross-sectional view of a semiconductor packaged element 200 during manufacturing according to some embodiments of this application is shown. See also Figure 8 It provides a second line layer 260. And in the next step, such as... Figure 9 As shown, a plurality of solder balls 330 are formed on the lower surface of the second circuit layer 260. Figure 10 In this process, the electronic integrated circuit 210 is bonded to the upper surface of the second circuit layer 260. And... Figure 11 In this process, a second conductive pillar 282 is grown on the upper surface of the electronic integrated circuit 210, and a first conductive pillar 281 is grown around the electronic integrated circuit 210. Figure 12 The molding layer 220 forming the packaged electronic integrated circuit 210 is shown. Figure 13In this process, a first circuit layer 230 is formed above the molding layer 220, and a first conductive post 281 and a second conductive post 282 are connected to the first circuit layer 230. Figure 14 The diagram illustrates bonding a photonic integrated circuit 240 to the upper surface of a first circuit layer 230. Prior to bonding, a bump 320 can be pre-formed on the upper surface of the photonic integrated circuit 240, which can be formed, for example, by etching. Figure 15 In this process, the light guide element 250 is bonded to the upper surface of the photonic integrated circuit 240 to form a semiconductor package element 200. Specifically, optical adhesive 252 can be filled on the uneven portion 320 first, and then the glass assembly 251 can be bonded to the photonic integrated circuit 240 through the optical adhesive 252.

[0043] The above-mentioned technical solutions provided in this application provide at least one balanced semiconductor packaging element that reduces the risk of breakage and warping of photonic integrated circuits.

[0044] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A semiconductor packaged element, characterized in that, include: Electronic integrated circuit, and a molding layer covering the electronic integrated circuit; The first circuit layer is stacked on top of the molding layer; A photonic integrated circuit is stacked on top of the first circuit layer, and the photonic integrated circuit is electrically connected to the electronic integrated circuit through the first circuit layer; A light guide element is stacked on top of the photonic integrated circuit; The light guide element causes the photonic integrated circuit to emit light perpendicularly toward the light guide element.

2. The semiconductor packaged element according to claim 1, characterized in that, It also includes a second circuit layer, with the molding layer stacked on top of the second circuit layer.

3. The semiconductor packaged element according to claim 1, characterized in that, It also includes vias that penetrate the photonic integrated circuit and are electrically connected to the first line layer.

4. The semiconductor packaged element according to claim 1, characterized in that, The side of the molding layer is flush with the side of the photonic integrated circuit.

5. The semiconductor package element according to claim 2, characterized in that, It also includes a first conductive post that penetrates the molding layer and electrically connects the first circuit layer and the second circuit layer, and a second conductive post disposed above the electronic integrated circuit and electrically connects the electronic integrated circuit and the first circuit layer.

6. The semiconductor package element according to claim 5, characterized in that, The lower surface of the molding layer is flush with the lower surface of the electronic integrated circuit.

7. The semiconductor packaged element according to claim 1, characterized in that, The upper surface of the photonic integrated circuit is provided with a concave-convex portion, and the light guide element is fitted and connected to the photonic integrated circuit through the concave-convex portion.

8. The semiconductor package element according to claim 5, characterized in that, The top surface of the second conductive post is flush with the top surface of the first conductive post, and the bottom surface of the second conductive post extends beyond the bottom surface of the first conductive post and contacts the second circuit layer.

9. The semiconductor packaged element according to claim 1, characterized in that, When viewed from above, the light guide element is surrounded by the photonic integrated circuit.

10. A semiconductor packaged element, characterized in that, include: Electronic integrated circuit, and a molding layer covering the electronic integrated circuit; A first circuit layer is disposed above the sealing layer along a first direction; A photonic integrated circuit is disposed above the first circuit layer along the first direction, and the photonic integrated circuit is electrically connected to the electronic integrated circuit through the first circuit layer; A light guide element is positioned above the photonic integrated circuit along the first direction; The light guide element causes the photonic integrated circuit to emit light along the first direction toward the light guide element.

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