stack structure

Abstract

The utility model provides a kind of stack structure including first bonding structure, first die and second die.First die is configured on the first side of first bonding structure, and first die includes second bonding structure.First encapsulation material covers first die.Second die is configured on the second side opposite to first side of first bonding structure, and second die includes third bonding structure and die perforation.Second encapsulation material covers second die.Second bonding structure of first die is combined with first bonding structure, and third bonding structure of second die is combined with first bonding structure between first and second die and first and second encapsulation material.

Description

Technical Field

[0001] This utility model relates to a stack structure. Background Technology

[0002] With the trend of high-density integration of various component dies and / or components, technologies involving the 3D integration of different components and components at the wafer level have been developed. Utility Model Content

[0003] In some embodiments of this invention, a stacked structure including a support structure, a first die, and a second die is provided. The support structure has a first surface and a second surface opposite to the first surface, and a dielectric layer on the first surface. The support structure includes a recess from the first surface that fills the dielectric layer, and a non-metallic alignment mark located in the recess. The first die is disposed above the support structure and is encapsulated by a first encapsulating material. A portion of the first encapsulating material is located between the first die and the support structure. The second die is disposed on a first bonding structure and is encapsulated by a second encapsulating material. The second die includes a second bonding structure and through die vias. The first die and the second die are located on opposite sides of the first bonding structure. The first bonding structure is bonded to the first die and to the second bonding structure of the second die, such that the first and second dies are electrically connected.

[0004] In some embodiments of this utility model, a stacked structure including a first bonding structure, a first die, and a second die is provided. The first die is disposed on a first side of the first bonding structure and includes a second bonding structure. A first encapsulating material covers the first die. The second die is disposed on a second side of the first bonding structure opposite to the first side and includes a third bonding structure and a die perforation. A second encapsulating material covers the second die. The second bonding structure of the first die is bonded to the first bonding structure, and the third bonding structure of the second die is bonded to the first bonding structure located between the first and second dies and the first and second encapsulating materials.

[0005] To make the above-mentioned features and advantages of this utility model more apparent and understandable, specific embodiments are described below, and detailed descriptions are provided in conjunction with the accompanying drawings. Attached Figure Description

[0006] When with attachment Figure 1 Upon reading this document, the best understanding of all aspects of this utility model can be obtained from the following detailed description. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, for clarity, the dimensions of the various features can be arbitrarily increased or decreased.

[0007] Figures 1 to 9Schematic cross-sectional views are shown illustrating various stages of a method for manufacturing a three-dimensional stack structure according to some embodiments of the present invention.

[0008] Figure 10 This is a perspective view of an exemplary three-dimensional stack structure according to some embodiments of the present invention.

[0009] Figures 11 to 15 Schematic cross-sectional views are shown illustrating various stages of a method for manufacturing a three-dimensional stack structure according to some embodiments of the present invention.

[0010] Figure 16 A schematic cross-sectional view of an exemplary 3D stack structure according to some embodiments of the present invention is shown. Detailed Implementation

[0011] The following description provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify the content of this invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features so that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be reused in various instances of this invention. Such reuse is for the sake of brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Additionally, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one component or feature shown in the figures and another component or feature. These spatially relative terms are intended to cover different orientations of the device in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0013] Other features and processes may also be included. For example, test structures may be included to aid in the verification testing of 3D packaged or three-dimensional integrated circuit (3DIC) devices. These test structures may, for example, include test pads formed in a redistribution layer or on a substrate to enable testing of the 3D package or 3DIC, use of probes and / or probe cards, and similar operations. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods described herein can be combined with test methods including intermediate verification of known good dies to improve yield and reduce costs.

[0014] It should be understood that the following embodiments of this invention provide applicable concepts that can be presented in a wide variety of specific contexts. The specific embodiments discussed herein are merely illustrative and relate to three-dimensional (3D) integrated structures or assemblies, and do not limit the scope of this invention. Embodiments of this invention describe exemplary manufacturing processes for 3D stacked structures and the 3D stacked structures thus manufactured. Some embodiments of this invention relate to 3D stacked structures formed using wafer bonding structures and stacked wafers and / or dies. Other embodiments relate to 3D integrated structures or assemblies including post-passivation interconnect (PPI) structures or interposers and other electrically connected components, including wafer-to-wafer assembled structures, die-to-wafer assembled structures, package-on-package assembled structures, die-to-die assembled structures, and die-to-substrate assembled structures. The wafer or die may include one or more types of integrated circuits or electrical components on a silicon / germanium-on-insulator substrate on a bulk semiconductor substrate or insulating layer. These embodiments are intended to provide further illustration but are not intended to limit the scope of this invention.

[0015] Figures 1 to 9A schematic cross-sectional view is shown illustrating each stage of a manufacturing method for forming a three-dimensional stack structure according to some embodiments of the present invention.

[0016] exist Figure 1 In some embodiments, a first carrier C100 with a groove RC1 is provided. In some embodiments, the first carrier C100 is or includes a wafer, and the wafer can be a blank semiconductor wafer (with no components formed) of any suitable size / shape. In some embodiments, the first carrier C100 is a substantially circular dummy wafer formed from a semiconductor material such as bulk silicon. In some embodiments, the groove RC1 is formed by partially removing the first carrier C100 by performing an etching process (such as dry etching) in conjunction with a photolithography process using a photomask pattern. In some alternative embodiments, the first carrier C100 can be a glass carrier, a ceramic carrier, or any carrier suitable for carrying a reconstructed wafer or stacked structure to manufacture a die stack structure and / or package.

[0017] In some embodiments, a plurality of grooves RC1 may be formed as grooves or cavities of the same size or geometry. In some embodiments, grooves RC1 may be formed as grooves or cavities of different sizes and / or various geometries. In some embodiments, such as Figure 1The top view shows some schematic top views of the groove RC1, which can be individually formed as a hollow square hole, a hollow rectangular annular groove, or an L-shaped groove. In some embodiments, the depth of the groove RC1 ranges from about 100 nanometers to about 500 nanometers. Subsequently, a first dielectric layer B100 covering the groove RC1 is formed over the first carrier C100. For example, depending on the depth of the groove RC1 and the thickness of the first dielectric layer B100, the first dielectric layer B100 fills the groove RC1. Alternatively, the first dielectric layer B100 is formed to conformally cover the groove RC1 without filling it. In some embodiments, the material of the first dielectric layer B100 includes silicon dioxide, silicon nitride, silicon oxynitride (SiON), or combinations thereof. In some embodiments, the first dielectric layer B100 can be formed by performing a chemical vapor deposition (CVD) process, such as low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), and high-density plasma CVD (HDPCVD). In some embodiments, the first dielectric layer B100 is formed of silicon oxynitride and has a thickness ranging from about 200 nanometers to about 800 nanometers or from about 400 nanometers to about 600 nanometers. After forming the first dielectric layer B100 covering the recess RC1, a first alignment mark AM1 is formed at the location of the recess RC1. Unlike common metallic alignment, the first alignment mark AM1 is a non-metallic or dielectric alignment mark, consisting of the recess RC1 and the dielectric material of the first dielectric layer B100 located at the location of the recess RC1. In some embodiments, the first alignment mark AM1 is an integral alignment mark for wafer-level alignment.

[0018] Reference Figure 2 At least one first die 200 is provided and disposed on a first dielectric layer B100 above a carrier C100. For example, the first die 200 is placed on the first carrier C100 with its front surface 200F facing the first carrier C100 and its back surface 200B away from the first carrier C100. Figure 2In some embodiments, the first die 200 includes a first semiconductor substrate 202, a first device layer 203 formed in the first semiconductor substrate 202, a first metallization structure 204, and a passivation layer 206 covering the first metallization structure 204 and located above the first semiconductor substrate 202. In some embodiments, the first die 200 is a semiconductor die made of a semiconductor wafer (such as a bulk silicon wafer or a silicon-on-insulator (SOI) wafer) or other semiconductor materials (such as III-V semiconductor materials). In some embodiments, the first semiconductor substrate 202 includes a bulk semiconductor substrate and / or other types of semiconductor substrates, such as multilayer or gradient substrates. In some embodiments, the first semiconductor substrate 202 includes elemental semiconductor materials such as silicon or germanium, compound semiconductor materials such as silicon carbide, gallium arsenide, indium arsenide, or indium phosphide, or alloy semiconductor materials such as silicon germanium, silicon germanium carbide, gallium arsenide phosphide, or indium gallium phosphide. In some embodiments, the first device layer 203 includes active components (e.g., transistors, memory, diodes, or the like) formed therein and optional passive components (e.g., resistors, capacitors, inductors, or the like).

[0019] like Figure 2 As shown, in some embodiments, the first metallization structure 204 is embedded in an insulating layer 205 formed on a first semiconductor substrate 202. In some embodiments, the insulating layer 205 includes one or more low dielectric constant dielectric layers, and the first metallization structure 204 includes an interconnect structure of multiple metallization layers. In one embodiment, the interconnect structure includes interconnecting metal wires, vias, and contact pads, and the topmost metallization layer of the first metallization structure 204 includes a top metal pad 2040. In some embodiments, the material of the metallization structure 204 includes aluminum (Al), aluminum alloys, copper (Cu), copper alloys, titanium (Ti), nickel (Ni), or combinations thereof.

[0020] In an exemplary embodiment, some components in the first device layer 203 may be electrically connected to the first metallization structure 204, while other components are electrically interconnected through the first metallization structure 204. The first metallization structure 204 shown herein is for illustrative purposes only, and the metallization structure 204 may include other configurations and may include one or more through-holes and / or inlay structures.

[0021] In some embodiments, the material of the passivation layer 206 includes silicon dioxide, silicon nitride, undoped silicate glass, or a combination thereof. In some embodiments, the passivation layer 206 can be formed by performing a CVD process, such as subatmospheric pressure CVD (SACVD), plasma-enhanced chemical vapor deposition (PECVD), and high-density plasma-enhanced chemical vapor deposition (HDPCVD). For example, the material of the insulating layer 205 is different from the material of the passivation layer 206. It is understood that the number of first dies 200 is merely an example, and the first dies 200 can be dies of the same type or different types. In some embodiments, although... Figure 2 Only one die is shown, but it can be understood that multiple dies of the same or different types are provided and packaged. Figure 10 In some embodiments, the first die 200 is considered as the first layer die for reconstructing the wafer structure.

[0022] In some embodiments, such as Figure 3 As shown, an encapsulation material 150 is formed on a first carrier C100 to completely cover a first die 200, forming a reconstructed wafer structure W150. In some embodiments, the first die 200 is completely covered and not exposed from the encapsulation material 150. In some embodiments, the encapsulation material 150 comprises an oxide material (e.g., silicon dioxide) or a TEOS oxide material with better gap-filling properties, using tetraethoxysilane (TEOS) as the source material. In some embodiments, the encapsulation material 150 is formed by performing a CVD process, such as SACVD, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), and high-density plasma chemical vapor deposition (HDPCVD). In some embodiments, the encapsulation material 150 comprises a resin material, such as epoxy resin, phenolic resin, silicone resin, or the like, selectively containing or not containing fillers. In some embodiments, the encapsulation material 150 is formed by a compression molding process. In some embodiments, the encapsulation material 150 is formed by an over-molding process. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may be selectively performed to planarize the encapsulation material 150 without exposing the first die 200. Figure 3In this design, the encapsulating material 150 covers the back surface and sidewalls of the first die 200. For example, the thickness T2 of the encapsulating material 150 is greater than the thickness T1 of the first die 200, such that a portion of the encapsulating material 150 covers the back surface 200B of the first die 200, and the portion of the encapsulating material 150 above the back surface 200B has a thickness T3 (greater than zero), where T2 is the sum of T1 and T3 (i.e., T3 + T1 = T2). It can be understood that if different types of dies with various thicknesses are molded by the encapsulating material 150, the encapsulating material 150 completely covers the different types of dies without exposing any dies from the encapsulating material 150.

[0023] Reference Figure 4 In some embodiments, a second carrier C300 with a groove RC2 is provided. In some embodiments, the second carrier C300 is or includes a wafer, and the wafer can be a blank semiconductor dummy wafer (with no components formed) of any suitable size / shape. In some embodiments, the second carrier C300 is a substantially circular dummy wafer formed of a semiconductor material (e.g., bulk silicon). In some embodiments, the groove RC2 is formed by partially removing the second carrier C300 using an etching process (e.g., dry etching) combined with a photolithography process using a photomask pattern. In some embodiments, the second carrier C300 serves as a support structure and carrier for carrying reconstructed wafers or stacked structures to manufacture die stacked structures and / or packages.

[0024] In some embodiments, a plurality of grooves RC2 may be formed as grooves or cavities of the same size or the same geometry. In some embodiments, grooves RC2 may be formed as grooves or cavities of different sizes and / or various geometries. In some embodiments, such as Figure 4The upper portion shows some schematic top views of the groove RC2, which can be formed as a hollow rectangular annular groove, a hollow square hole, or an inverted L-shaped groove. In some embodiments, the depth of the groove RC2 ranges from about 100 nanometers to 500 nanometers. Subsequently, a second dielectric layer B300 covering the groove RC2 is formed on the second carrier C300. For example, the second dielectric layer B300 fills the groove RC2 according to the depth of the groove RC2 and the thickness of the second dielectric layer B300. In one embodiment, the second dielectric layer B300 is formed on the second carrier C300 with a thickness of T4 and fills the groove RC2 with a thickness T5 (greater than T4). In some embodiments, the material of the second dielectric layer B300 includes silicon dioxide, silicon nitride, silicon oxynitride (SiON), or combinations thereof. In some embodiments, the second dielectric layer B300 is formed of silicon oxynitride with a thickness ranging from about 200 nanometers to about 600 nanometers. In some embodiments, the material of the second dielectric layer B300 is different from the material of the encapsulation material 150. After forming the second dielectric layer B300 covering the groove RC2, a second alignment mark AM2 is formed at the location of the groove RC2. In some embodiments, the second alignment mark AM2 is a non-metallic or dielectric alignment mark, composed of the groove RC2 and the dielectric material of the second dielectric layer B300 located at the location of the groove RC2. In some embodiments, the second alignment mark AM2 is a global alignment mark for wafer-level alignment.

[0025] exist Figure 5 In this configuration, the second carrier C300 is disposed on the reconstructed wafer structure W150, and the second dielectric layer B300 directly contacts and adheres to the encapsulation material 150. During the placement of the second carrier C300, an overall alignment process is performed by aligning alignment marks AM1 and AM2. For example, the second alignment mark AM2 is perpendicularly aligned with the corresponding first alignment mark AM1 to assist in overall alignment. In some embodiments, the patterns of alignment marks AM1 and AM2 are mutually matching patterns. In some embodiments, such as Figure 5 As shown in the schematic top view, alignment mark AM1 is shaped like an "L," while alignment mark AM2 is shaped like an inverted "L," allowing the projections of the two alignment marks to be used for precise alignment and as a reference for alignment calibration. Similarly, as... Figure 5 As shown in the schematic top view at the top, the alignment mark AM1 has a pattern shape like a square ring, while the alignment mark AM2 has a rectangular shape but is smaller in size, so that the projection of the alignment mark AM2 falls within the projection range of the alignment mark AM1 for alignment calibration.

[0026] Subsequently, Figure 6In the process, the entire stack structure is flipped, and then the first carrier C100 is removed, exposing the passivation layer 206 and the encapsulation material 150. After removing the first carrier C100, a bonding structure 250 is integrally formed on the reconstructed wafer structure W150 and on the passivation layer 206 and the encapsulation material 150. In some embodiments, the bonding structure 250 includes a bonding dielectric material 252, contact pads 254 embedded in the bonding dielectric material 252, and bonding pad vias 256 that penetrate the passivation layer 206 and connect to the top metal pad 2040. In some embodiments, the material of the bonding dielectric material 252 includes silicon dioxide, silicon nitride, undoped silicate glass, or a combination thereof. In some embodiments, the bonding dielectric material 252 can be formed by performing a chemical vapor deposition process, such as subatmospheric pressure chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition. In some embodiments, some contact pads 254 are connected to bonding pad vias 256 and electrically connected to the top metal pads 2040 of the first die 200 to electrically connect the first die 200 to the bonding structure 250. Typically, most of the contact pads 254 and bonding pad vias 256 are located within the bonding region to facilitate bonding. In some embodiments, the contact pads 254 include electrically floating contact pads 254F located outside the bonding region, which can serve as alignment marks for other die displacements. In some embodiments, the formation of the bonding structure 250 may involve an alignment process using alignment mark AM2 as a marker, and the position of the electrically floating contact pads 254F may correspond to and / or be perpendicularly aligned to the position of the lower alignment mark AM2. In some embodiments, the top metal pad 2040 is an input / output (I / O) pad or an aluminum pad. In an exemplary embodiment, the bonding pad vias 256 and contact pads 254 are formed by the same process and made of the same metal material. For example, metallic materials include copper, copper alloys, aluminum, aluminum alloys, titanium, nickel, or combinations thereof.

[0027] Reference Figure 7 In some embodiments, at least one second die 400 is provided and configured on a bonding structure 250 on a reconstructed wafer structure W150. During die 400 displacement, an alignment process is performed using an electrically floating pad 254F as an alignment mark and / or a lower alignment mark AM2 as an alignment mark. For example, the second die 400 is placed at a predetermined position on the bonding structure 250, with its front surface 400F facing the bonding structure 250 and its back surface 400B away from the bonding structure 250. Figure 7In some embodiments, the second die 400 includes a second semiconductor substrate 402, a second device layer 403 formed in the second semiconductor substrate 402, a second metallization structure 404, and a second bonding structure 450 on the second metallization structure 404 and the second semiconductor substrate 402. It is understood that multiple dies 400 may be included; only one second die 400 is shown as an example, and multiple second dies 400 may include dies of the same type or different types. Figure 10 In some embodiments, the second die 400 is considered as a second die that reconstructs the wafer structure.

[0028] In some embodiments, the second die 400 is a semiconductor die made of a semiconductor wafer (e.g., a bulk silicon wafer or a silicon-on-insulator (SOI) wafer) or other semiconductor materials (e.g., III-V semiconductor materials). In some embodiments, the second semiconductor substrate 402 includes a bulk semiconductor substrate and / or other types of semiconductor substrates, such as multilayer or gradient substrates. In some embodiments, the second semiconductor substrate 402 includes elemental semiconductor materials, compound semiconductor materials, or alloy semiconductor materials. In some embodiments, the second device layer 403 includes active components (e.g., transistors, memory, diodes, or similar components) formed therein and optional passive components (e.g., resistors, capacitors, inductors, or similar components).

[0029] like Figure 7 As shown, in some embodiments, the second metallization structure 404 is embedded in an insulating layer 405 formed on the second semiconductor substrate 402. In some embodiments, the second metallization structure 404 includes an interconnect structure of multiple metallization layers, wherein metal pads 4040 are interconnected with metal wires, vias, and contact pads. In some embodiments, the metal pads 4040 are input / output (I / O) pads or aluminum pads. In some embodiments, the second metallization structure 404 further includes substrate through-holes (TSVs) 4042 embedded in the second semiconductor substrate 402. In some embodiments, the material of the metallization structure 404 includes Al, aluminum alloys, Cu, copper alloys, Ti, Ni, or combinations thereof.

[0030] In an exemplary embodiment, some components in the second device layer 403 may be electrically connected to the second metallization structure 404, while some components are electrically interconnected through the second metallization structure 404. The second metallization structure 404 shown herein is for illustrative purposes only, and the metallization structure 404 may include other configurations and may include one or more through-hole and / or inlay structures.

[0031] In some embodiments, the bonding structure 450 includes a bonding dielectric material 452, contact pads 454 embedded in the bonding dielectric material 452, and bonding pad vias 456 connected to metal pads 4040. In some embodiments, the contact pads 454 are connected to the bonding pad vias 456 and electrically connected to the metal pads 4040 of the second die 400. In some embodiments, the material of the bonding dielectric material 452 includes silicon dioxide, silicon nitride, undoped silicate glass, or combinations thereof. In some embodiments, the bonding dielectric material 452 can be formed by performing a CVD process (e.g., SACVD, PECVD, or HDPCVD). In an exemplary embodiment, the bonding pad vias 456 and the contact pads 454 are formed by the same process and made of the same metallic material, such as Cu, copper alloys, Al, aluminum alloys, Ti, Ni, or combinations thereof.

[0032] exist Figure 7 In this process, the span of the second die 400 is smaller than that of the first die 200, and since the bonding structure 250 is an integral bonding structure formed on the entire reconstructed wafer structure W150, some contact pads 254 are located outside the bonding area between the first die 200 and the second die 400.

[0033] In some embodiments, the first die 200 and the second die 400 have different functions. In some embodiments, the first die 200 and the second die 400 have similar functions but different sizes. In some embodiments, the first die 200 and the second die 400 each include one or more memory chips, such as high-bandwidth memory chips, dynamic random access memory (DRAM) chips, or static random access memory (SRAM) chips. In some alternative embodiments, the first die 200 and the second die 400 each include one or more application-specific integrated circuit (ASIC) chips, analog chips, sensor chips, wireless application chips (e.g., Bluetooth chips), radio frequency (RF) chips, or voltage regulator chips.

[0034] Then, in some embodiments, such as Figure 7As shown, a bonding process is performed to bond bonding structures 250 and 450 to each other, thereby bonding the first die 200 and the second die 400. In some embodiments, the bonding process includes a two-stage bonding process. In some embodiments, a low-temperature heating process at a temperature of about 100 degrees Celsius to about 200 degrees Celsius is performed to heat and establish a dielectric-to-dielectric bond between bonding dielectric materials 252 and 452, and a high-temperature heating process at a temperature of about 200 degrees Celsius to about 300 degrees Celsius is performed to heat and establish a metal-to-metal bond between metal contact pads 254 and 454. In some embodiments, the first die 200 and the second die 400 are bonded and electrically connected through the bonded contact pads 254, 454 and the first metallization structure 204 and the second metallization structure 404. Furthermore, it can be considered that the first die 200 is bonded to the bonding structure 250 through the connected contact pads 254 and the bonding pad vias 256.

[0035] After the bonding process, bonding structure 450 and bonding structure 250 are bonded, and the bonding interface BF (indicated by dashed lines) exists between bonding structures 250 and 450. That is, contact pad 454 is bonded to contact pad 254, and bonding dielectric material 452 is bonded to bonding dielectric material 252. A partially enlarged schematic diagram of the bonding structure is shown below. Figure 7 At the top, the bonded contact pads 254 and 454 are connected to the metal pads 2040 and 4040 via bonding pad vias 256 and 456, respectively. Through the arrangement of the overall bonding structure 250, bonding of individual dies to the reconfigured wafer can be achieved without forming a local bonding structure within the first die 200, further reducing the overall thickness of the stack structure. In some embodiments, an asymmetric stacking scheme appears on both sides of the bonding interface BF. The bonding pad via 256 penetrates the passivation layer 206 and extends through the insulating layer 205 to reach the metal pad 2040, while the bonding pad via 456 extends through the insulating layer 405 to reach the metal pad 4040.

[0036] In some embodiments, such as Figure 8As shown, an encapsulation material 350 is formed on the bonding structure 250 to completely cover the second die 400, forming a reconstructed wafer structure W350. In some embodiments, the second die 400 is covered at least on its sides by the encapsulation material 350. In some embodiments, the encapsulation material 350 comprises an oxide material (such as silicon dioxide) or a TEOS oxide material with better gap-filling properties, using tetraethoxysilane (TEOS) as the source material. In some embodiments, the encapsulation material 350 is formed by performing a CVD process, such as SACVD, LPCVD, PECVD, or HDPCVD. In some embodiments, the encapsulation material 350 comprises a resin material, such as epoxy resin, phenolic resin, silicone resin, or the like, selectively containing or not containing fillers. In some embodiments, the encapsulation material 350 is formed by a compression molding process or an over-molding process. In some embodiments, thinning and planarization processes are performed to thin the second die 400 and planarize the encapsulation material 350 until the substrate via 4042 of the second die 400 is exposed. In some embodiments, the second die 400 may be thinned to a desired thickness, removing a portion of the semiconductor substrate 402 from the back surface until the substrate via 4042 is exposed. In some embodiments, the thinning process may include a polishing process, an etching process, or a combination thereof. In some embodiments, the planarization process includes one or more chemical mechanical planarization processes. After the thinning and planarization processes, the treated back surface 400B' of the thinned second die 400 is coplanar and flush with the top surface 350S of the planarized encapsulation material 350. (Refer to...) Figure 8 The encapsulation material 350 covers the sidewalls of the second die 400, but exposes the back surface 400B' of the thinned second die 400 and the end of the substrate via 4042. For example, the thickness of the encapsulation material 350 is substantially the same as the thickness of the thinned second die 400.

[0037] Reference Figure 8 and Figure 9In some embodiments, a redistribution layer (RDL) 500 is formed on the reconstructed wafer structure W350, covering the second die 400 and the encapsulation material 350. The redistribution layer (RDL) 500 is formed over the entire reconstructed wafer structure W350 and is electrically connected to the underlying second die 400 via a substrate via 4042 and a metallization structure 404, and further electrically connected to the underlying first die 200 of the reconstructed wafer structure W150 via bonding structures 250, 450 and a metallization structure 204. In some embodiments, the redistribution layer 500 includes a redistribution pattern 504 embedded in at least one dielectric material layer 502. It can be seen that the configuration of the redistribution pattern or the number of dielectric material layers is not limited by the illustrations herein. The redistribution pattern 504 includes wiring patterns, vias, and bump pads, for example. In some embodiments, connectors 550 are formed on the redistribution layer 500. In some embodiments, the dielectric material layer 502 is made of silicon dioxide, silicon nitride, benzocyclobutene (BCB), epoxy resin, polyimide (PI), or polybenzoxazole (PBO). In some embodiments, the connector 550 includes conductive bumps (microbumps or gold bumps), controlled collapse chip connection (C4) bumps, solder balls, ball grid array (BGA) bumps, or combinations thereof. In some embodiments, the connector 550 is made of copper, aluminum, lead-free alloys (e.g., gold, silver, aluminum, tin, or copper alloys) or lead-containing alloys (e.g., lead-tin alloys). The connector 550 may be formed by ball bonding, C4 process, electroplating process, and / or other suitable processes. The connector 550 is electrically connected to the first and second dies 200, 400 via the redistribution layer 500.

[0038] Subsequently, in some embodiments, such as Figure 8 and Figure 9 As shown, after forming the redistribution layer 500, a stack structure including reconstructed wafer structures W350 and W150, a support structure C300, and the redistribution layer 500 is obtained. In some embodiments, reference is made to... Figure 8 and Figure 9A monomerization process can be performed to cut the stacked structure (reconstructed wafer structures W350, W150, support structure C300, and redistribution layer 500) into individual stacked structures 25. In some embodiments, the monomerization process includes a wafer dicing or sawing process that cuts through the second carrier C300, dielectric layer B300, reconstructed wafer structure W350, and redistribution layer 500. During the monomerization process, the dicing or sawing process does not cut into alignment mark AM2 or electrically floating contact pad 254F.

[0039] Reference Figure 9 Each stack structure 25 includes a support 300S (a portion of the second carrier C300), at least one first die 200 encapsulated by a first encapsulant 150F (a portion of the encapsulant material 150), an auxiliary dielectric layer 302 disposed between the first encapsulant 150F and the support 300S, a bonding structure 250 disposed on the first encapsulant 150F and the first die 200, at least one second die 400 disposed on the bonding structure 250 and laterally encapsulated by a second encapsulant 350F (a portion of the encapsulant material 350), a redistribution layer 500 disposed on the second die 400 and the second encapsulant 350F, and a connector 550 disposed on the redistribution layer 500. In some embodiments, within the stack structure 25, the bonding structure 250 is bonded to the bonding structure 450 of the second die 400, and the first die 200 is electrically connected to the second die 400 through the bonding structure 250 connected to the first die 200. In some embodiments, for the stack structure 25, the auxiliary dielectric layer 302 includes a non-metallic dielectric alignment mark AM2 formed adjacent to the first and second dies 200, 400 and in the groove RC2 of the support 300S. Furthermore, in the stack structure 25, the bonding structure 250 includes an electrically floating metallic alignment mark 254F located adjacent to the first and second dies 200, 400 and directly above the alignment mark AM2.

[0040] In some embodiments, accurate alignment is achieved by forming non-metallic alignment marks AM1 / AM2, resulting in a more compact stack structure with reduced height (thickness) because a thicker dielectric layer is not required and metal / metal alignment marks are not used. Furthermore, a reliable bond is established through an integrally formed bonding structure with shorter connection paths. Moreover, alignment marks embedded in the bonding structure are designed to further improve alignment and enhance the yield and reliability of the 3D stack structure 25.

[0041] Although the steps of the method are shown and described as a series of actions or events, it should be understood that the order in which these actions or events are shown should not be construed as limiting. Furthermore, not all shown processes or steps are necessary to carry out one or more embodiments of this invention.

[0042] Figure 10 This is a perspective view of an exemplary three-dimensional stacked structure according to some embodiments of the present invention. The stacked structure can be formed using a manufacturing process similar to that described above, except that multiple and different types of individual dies are provided. In some embodiments, multiple dies 20A and multiple dies 20B are provided as a first layer of dies to form a reconstructed wafer or panel structure, and then multiple dies 10A and multiple dies 10B are provided as a second layer of dies and stacked and bonded to a bonding structure 36 to form a two-layer reconstructed wafer or panel structure. Most of the manufacturing process is similar to or the same as described in the preceding paragraphs, and will not be described in detail here.

[0043] Reference Figure 10 In some embodiments, the stack structure 35 includes a redistribution layer (RDL) 40, connectors 42 are disposed above and below the redistribution layer 40, a lower structure T2 includes at least one die 10A and at least one die 10B laterally covered by an encapsulation material 38, a bonding structure 36 is disposed on the lower structure T2, an upper structure T1 includes at least one die 20A and at least one die 20B encapsulated by an encapsulation material 34, an auxiliary dielectric layer 32 is disposed on the upper structure T1, and a support 30 is located on the auxiliary dielectric layer 32. In some embodiments, dies 10A and 10B are electrically connected to the lower redistribution layer 40 through substrate vias 10AV and 10BV, respectively.

[0044] For example, support 30 is similar to or the same as support 300S described above, and similar materials and forming methods can be used to manufacture support 30. Similarly, encapsulation material 34 or 38 is similar to or the same as encapsulation material 150F, 350F; bonding structures 16A, 16B are similar to bonding structure 450; bonding structure 36 is similar to bonding structure 250; bonding films 26A, 26B are similar to passivation layer 206; auxiliary dielectric layer 32 is similar to or the same as auxiliary dielectric layer 302; and redistribution layer 40 and connector 42 are similar to or the same as redistribution layer 500 and connector 550, respectively. Therefore, the same or similar materials and forming methods can be used. For simplicity, detailed descriptions are omitted.

[0045] Reference Figure 10The bonding structures 16A and 16B of dies 10A and 10B are bonded to bonding structure 36, while dies 20A and 20B are connected to bonding structure 36. Through the arrangement of the overall bonding structure 36, there is fusion bonding between the bonding films 26A and 26B of individual dies 20A and 20B and the overall bonding structure 36, but dies 20A and 20B do not form local bonding structures therein.

[0046] In some embodiments, Figure 10 In this structure, independent dies 20A and 20B of different thicknesses are arranged side-by-side on the bonding structure 36, and the encapsulating material 34 covers and completely encapsulates dies 20A and 20B (covering the sidewalls and back surfaces of dies 20A and 20B). Figure 10 It can be seen that for the thinner die 20B, there is a larger distance between the back surface of die 20B and the auxiliary dielectric layer 32, compared to a smaller distance between the back surface of die 20A and the auxiliary dielectric layer 32.

[0047] In some embodiments, within the stack structure 35, a non-metallic alignment mark AM3 is formed in a recess RC3 of the support 30, located adjacent to and between dies 20A, 20B, 10A, and 10B. Furthermore, in the stack structure 35, the bonding structure 36 includes an electrically floating metallic mark 364 located adjacent to and between dies 20A, 20B, 10A, and 10B, and directly above the alignment mark AM3.

[0048] It is understood that the number of dies 10A, 10B, 20A, and 20B can be one, two, or more, but this invention is not limited thereto. In some embodiments, dies 20A / 20B and dies 10A / 10B have different functions. In some embodiments, dies 20A / 20B and dies 10A / 10B have the same or similar functions. In some embodiments, die 20A or 20B includes a memory chip, such as a high-bandwidth memory chip, a dynamic random access memory (DRAM) chip, or a static random access memory (SRAM) chip. In some alternative embodiments, die 10A or 10B includes an application-specific integrated circuit (ASIC) chip, an analog chip, a sensor chip, a wireless application chip such as a Bluetooth chip, a radio frequency (RF) chip, or a voltage regulator chip. In one embodiment, die 20A or 20B includes a memory chip, while die 10A or 10B includes an ASIC chip. Although Figure 10 It is not explicitly shown that some conductive features of dies 20A, 20B, 10A and 10B are electrically interconnected, making dies 20A, 20B, 10A and 10B electrically connected.

[0049] Because the 3D stack structure 25 or 35 includes multiple dies stacked on top of each other and connected face-to-face by an integral bonding structure, the stacked dies are integrated in a compact form. In some embodiments, the 3D stack structure 25, 35 may be regarded as an integrated circuit (IC) die or a system-on-a-chip (SoIC) die.

[0050] Figures 11 to 15 This is a schematic cross-sectional view illustrating various stages of a method for manufacturing a three-dimensional stack structure according to some embodiments of the present invention.

[0051] Reference Figure 11 A bonding structure 1150 is formed on a carrier C1. In some embodiments, the carrier C1 is a sacrificial carrier, such as a dummy wafer. In one embodiment, the carrier C1 comprises a blank semiconductor material substrate. In some embodiments, the carrier C is a glass substrate, a metal plate, a plastic support plate, or the like, but other suitable substrate materials may be used as long as the material is compatible with subsequent process steps. In some embodiments, the bonding structure 1150 includes a bonding dielectric material 1152 and bonding pads 1154 embedded in the bonding dielectric material 1152. Figure 11 As shown, the thickness of the bonding dielectric material 1152 is greater than the thickness of the bonding pad 1154, so that the bottom of the bonding pad 1154 is completely covered by the bonding dielectric material 1152. The material and method of forming the bonding structure 1150 are similar to those of the bonding structures 250 or 450.

[0052] Subsequently, referring to Figure 11 In some embodiments, at least one die 1120 is provided and configured onto a bonding structure 1150. In some embodiments, an alignment process is first performed using an electrically floating marker 1154F as an alignment marker. In some embodiments, after the alignment process, the die 1120 is configured in a predetermined position on the bonding structure 1150. In some embodiments, the die 1120 is configured on the bonding structure 1150 with its front surface 1120F facing the bonding structure 1150 and its back surface 1120B away from the bonding structure 1150. Figure 11In some embodiments, die 1120 includes a substrate 1122, a device layer 1123 formed on the substrate 1122, a metallization structure 1124, and a bonding structure 1126 on the metallization structure 1124 and the substrate 1122. In one embodiment, bonding structure 1126 includes bonding dielectric material 1126D and bonding pads 1126P embedded in the bonding dielectric material 1126D, the bonding pads 1126P being connected to the metallization structure 1124. Subsequently, a bonding process is performed to bond bonding structures 1126 and 1150 to each other, thereby bonding die 1120 to bonding structure 1150. In some embodiments, the bonding process establishes a dielectric-to-dielectric bond between bonding dielectric materials 1126D and 1152, and a metal-to-metal bond between metal bonding pads 1126P and 1154. Figure 11 As shown, the bonding structure 1150 includes electrically floating marks 1154F located outside the bonding region R1 of the die 1120 and the bonding structure 1150. For example, the electrically floating marks 1154F located outside the bonding region can serve as alignment marks for other die displacements.

[0053] In some embodiments, Figure 11 In this process, an encapsulation material 1130 is formed on the bonding structure 1150 and the carrier C1 to completely cover the die 1120, forming a reconstructed wafer structure W1150. In some embodiments, the die 1120 is completely covered and not exposed from the encapsulation material 1130. In some embodiments, the encapsulation material 1130 comprises an oxide material (e.g., TEOS oxide material). In some embodiments, the encapsulation material 1130 is formed by performing a CVD process, such as SACVD, LPCVD, PECVD, and HDPCVD. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), may be selectively performed to planarize the encapsulation material 1130 without exposing the die 1120.

[0054] exist Figure 11 In this configuration, encapsulating material 1130 covers the back surface 1120B and sidewalls of die 1120. For example, the thickness of encapsulating material 1130 is greater than the thickness of die 1120, so a portion of encapsulating material 1130 remains on and covers the back surface 1120B of die 1120. It can be understood that if different types of dies with varying thicknesses are covered by encapsulating material, the encapsulating material completely covers the different types of dies without exposing any dies from the encapsulating material.

[0055] Reference Figure 12In some embodiments, another carrier C300' is provided, with a dielectric layer B300' located between the carrier C300' and the reconstructed wafer structure W1150. In some embodiments, the carrier C300' is formed with grooves (shown in dashed lines) and has alignment marks similar to those in the carrier C300. In some embodiments, the carrier C300' is formed without grooves. In some embodiments, the carrier C300' and dielectric layer B300' are similar to the second carrier C300 and dielectric layer B300, using the same or similar materials and forming methods. In some embodiments, the carrier C300' serves as a support structure for a stacked structure, used in methods of manufacturing die stacked structures and / or packages.

[0056] In some embodiments, refer to Figure 13 The entire stack structure is flipped and the carrier C1 is removed. After removing the carrier C1, an etching process is performed on the exposed bonding structure 1150 to partially remove the bonding dielectric material 1152 until the bonding pad 1154 is exposed.

[0057] Subsequently, referring to Figure 13 In some embodiments, at least one die 1140 is provided and configured onto a bonding structure 1150. During the placement of the die 1140, an alignment process is first performed using an electrically floating marker 1154F as an alignment marker. In some embodiments, after the alignment process, the die 1140 is configured in a predetermined position on the bonding structure 1150, with its front surface 1140F facing the bonding structure 1150 and its back surface 1140B away from the bonding structure 1150. Figure 13 In some embodiments, die 1140 includes a substrate 1142, a device layer 1143, substrate vias (TSVs) 1145, a metallization structure 1144 formed on the substrate 1142, and a bonding structure 1146 located on the metallization structure 1144 and the substrate 1142. In an embodiment, bonding structure 1146 includes a bonding dielectric material 1146D and bonding pads 1146P embedded in the bonding dielectric material 1146D, the bonding pads 1146P being connected to the metallization structure 1144. Subsequently, a bonding process is performed to bond bonding structures 1146 and 1150 to each other to bond die 1140 to bonding structure 1150. In some embodiments, a dielectric-to-dielectric bond is established between bonding dielectric materials 1146D and 1152, and a metal-to-metal bond is established between metal bonding pads 1146P and 1154. Figure 13 In the process, through the bonding structure, dies 1120 and 1140 are bonded to bonding structure 1150, and bonded to each other through the bonded bonding pads 1126P, 1154 and 1146P, to achieve a triple stack bonding scheme.

[0058] After the bonding process, bonding structure 1146 and bonding structure 1150 are bonded together, and a bonding interface BF2 (indicated by a dashed line) exists between bonding structures 1146 and 1150. Bonding structure 1126 and bonding structure 1150 are bonded together, and a bonding interface BF1 (indicated by a dashed line) exists between bonding structures 1126 and 1150. For example... Figure 13 As shown in the enlarged schematic diagram at the top, bonding pads 1146P and 1126P are bonded to the bonding pad 1154 located in the middle, and bonding dielectric materials 1146D and 1126D located on both sides of the bonding dielectric material 1152 are bonded to the bonding dielectric material 1152. Figure 13 The enlarged schematic diagram of the bonding structure shown above reveals three bonding pads 1146P, 1154, and 1126P, and three layers of dielectric bonding materials 1146D, 1152, and 1126D stacked and bonded together, with two bonding interfaces BF1 and BF2 in between. Through the arrangement of the overall bonding structure 1150, a strong and reliable bond between individual dies within the reconfigurable wafer can be achieved.

[0059] In some alternative embodiments, after removing the carrier C1 and performing an etching process to partially remove the bonding dielectric material 1152 until the bonding pads 1154 are exposed, another bonding structure 2150 (in) Figure 16 The die 1140 is directly formed on the exposed bonding structure 1150, and after the bonding structure 2150 is formed, the die 1140 is aligned and placed in a predetermined position on the bonding structure 2150. Similarly, by performing one or more bonding processes, the bonding structure 1146 is bonded to the bonding structure 2150, the bonding structure 2150 is bonded to the bonding structure 1150, and the bonding structure 1150 is bonded to the bonding structure 1126, thereby bonding and electrically connecting the dies 1120 and 1140. Therefore, as Figure 16 As shown in the enlarged schematic diagram at the top, there is a joint interface BF2 (indicated by a dashed line) between joint structures 1146 and 2150, a joint interface BF3 (indicated by a dashed line) between joint structures 2150 and 1150, and a joint interface BF1 (indicated by a dashed line) between joint structures 1126 and 1150.

[0060] Reference Figure 14An encapsulation material 1160 is formed on the bonding structure 1150 to completely cover the die 1140, forming a reconstructed wafer structure W1350. In some embodiments, the die 1140 is covered by the encapsulation material 1160 at least laterally. In some embodiments, the encapsulation material 1160 comprises an oxide material (e.g., silicon dioxide) or a TEOS oxide material with good gap-filling properties formed by CVD using tetraethyl orthosilicate (TEOS) as the source material. In some embodiments, the encapsulation material 1160 comprises a resin material, such as epoxy resin, phenolic resin, silicone resin, or the like, selectively containing or without fillers, formed by a molding process. In some embodiments, thinning and planarization processes are performed to thin the die 1140 and planarize the encapsulation material 1160 until the substrate vias 1145 of the die 1140 are exposed. In some embodiments, the thinning and planarization processes are similar to those previously described and will not be repeated here. After the thinning and planarization processes, the back surface 1140B' of the thinned die 1140 is coplanar and flush with the top surface of the planarized encapsulation material 1160. (Refer to...) Figure 14 Encapsulation material 1160 covers the sidewalls of die 1140, but exposes the back surface 1140B' of the thinned die 1140 and the end of the substrate via 1145. For example, the thickness of encapsulation material 1160 is substantially the same as the thickness of thinned die 1140.

[0061] exist Figure 14 and Figure 15 In some embodiments, a redistribution layer (RDL) 1170 is formed on the reconstructed wafer structure W1350, covering the die 1140 and the encapsulation material 1160. The redistribution layer (RDL) 1170 is formed over the entire reconstructed wafer structure W1350 and is electrically connected to the underlying die 1140 via a substrate via 1145 and a metallization structure 1144, and further electrically connected to the underlying die 1120 of the reconstructed wafer structure W1150 via bonding structures 1146, 1150, 1126 and the metallization structure 1124. In some embodiments, the redistribution layer 1170 includes a redistribution pattern embedded in a dielectric material, the configuration of which or the number of layers of dielectric material is not limited by the illustrations herein. In some embodiments, a connector 1180 is formed on the redistribution layer 1170. The materials and formation methods of the redistribution layer 1170 and the connector 1180 are similar to those of the RDL and connector described above, and will not be repeated in detail here. The connector 1180 is electrically connected to the cores 1120 and 1140 via the redistribution layer 1170.

[0062] Subsequently, in some embodiments, reference is made to Figure 14 and Figure 15After forming the redistribution layer 1170 and the connector 1180, a monomerization process can be performed to dicing the stack structure (reconstructed wafer structures W1350, W1150, support C300', and redistribution layer 1170) into individual stack structures 45. In some embodiments, the monomerization process includes a wafer dicing process or a sawing process, see reference to Figure 14 and Figure 15 The process cuts through the redistribution layer 1170, reconstructs the wafer structure W1350, and cuts through the carrier C300' and its dielectric layer B300'. During the monomerization process, the dicing or sawing process does not cut into the electrically floating marker 1154F.

[0063] Reference Figure 15 Each stack structure 45 includes a support C300', a dielectric layer B300', at least one die 1120 encapsulated by an encapsulating material 1130 (a portion of the encapsulating material 1130), a bonding structure 1150 disposed on the die 1120 and the encapsulating material 1130, at least one die 1140 disposed on the bonding structure 1150 and laterally covered by an encapsulating material 1160 (a portion of the encapsulating material 1160), a redistribution layer 1170 disposed on the die 1140 and the encapsulating material 1160, and a connector 1180 disposed on the redistribution layer 1170. In some embodiments, within the stack structure 45, the bonding structure 1150 is bonded to bonding structures 1146 and 1126 of the dies 1140 and 1120, respectively, and the dies 1120 and 1140 are electrically connected through bonding structures 1126, 1150, and 1146. Within the stack structure 45, the bonding structure 1150 includes an electrically floating mark 1154F located adjacent to the bonded dies 1120, 1140. In some embodiments, for the stack structure 45, if the support C300' provides a non-metallic alignment mark as previously described, the position of the electrically floating mark 1154F may correspond to and be perpendicularly aligned with the non-metallic dielectric alignment mark.

[0064] Figure 16 A schematic cross-sectional view of an exemplary 3D stack structure according to some embodiments of the present invention is shown. As described above, Figure 16 The manufacture of the exemplary structure shown can follow Figures 11 to 15 The manufacturing process described includes forming an additional bonding structure 2150 before placing the die 1140.

[0065] exist Figure 16In the 3D stack structure 60, there are support members C300', dielectric layer B300', at least one die 1120 encapsulated by encapsulation material 1130 (a part of encapsulation material 1130), bonding structures 2150 and 1150 disposed on die 1120 and encapsulation material 1130, at least one die 1140 disposed on bonding structure 2150 and laterally covered by encapsulation material 1160 (a part of encapsulation material 1160), redistribution layer 1170 disposed on die 1140 and encapsulation material 1160, and connector 1180 disposed on redistribution layer 1170. In some embodiments, within the stack structure 60, an additional bonding structure 2150 is bonded to bonding structure 1150, and bonding structures 1146 and 1126 of dies 1140 and 1120 are bonded to bonding structures 2150 and 1150, respectively, and dies 1120 and 1140 are electrically connected through bonding structures 1126, 1150, 2150, and 1146. The main structural difference between the 3D stack structure 60 and the 3D stack structure 45 is that the additional integral bonding structure 2150 is formed between bonding structure 1150 and die 1140 and the lateral encapsulation material 1160. In some embodiments, the material of bonding structure 2150 is similar to the material of bonding structure 1150. In some embodiments, the material of bonding dielectric material 2152 is different from the material of bonding dielectric material 1152. Apart from the similar manufacturing process described above, bonding structure 2150 is formed as an integral bonding structure on the reconstructed wafer structure and is formed directly on bonding structure 1150. In some embodiments, when the bonding structure 2150 is formed, the bonding pads 2154 are exposed from the bonding dielectric material 2152, and etching or planarization is optional. Other subsequent manufacturing processes are similar to or the same as those described in the previous embodiments, and details are omitted here.

[0066] like Figure 16 As shown in the schematic enlarged view at the top, bonding pads 1146P and 1126P are bonded to bonding pads 2154 and 1154 located in the middle, respectively, and bonding pads 1154 and 2154 are bonded to each other. Furthermore, bonding dielectric materials 1146D and 1126D located on both sides of the bonding dielectric material stack 2152 and 1152 are bonded to bonding dielectric materials 2152 and 1152, respectively. Figure 16 In the enlarged schematic diagram of the bonding structure shown above, four bonding pads 1146P, 2154, 1154 and 1126P and four layers of dielectric bonding materials 1146D, 2152, 1152 and 1126D are stacked and bonded to each other, with three bonding interfaces BF1, BF3 and BF2 in between, thus realizing a quadruple stack bonding scheme.

[0067] In an exemplary embodiment, the 3D stack structures 25, 35, 45, and 60 described above may undergo additional processing in subsequent processes to connect with further connecting structures before cutting. These subsequent processes may be modified according to the product design and are not described in detail here.

[0068] In an exemplary embodiment, an integral bonding structure with embedded alignment marks is formed to assist die placement. A thinner sacrificial carrier can be used to achieve better heat dissipation because the sacrificial carrier requires fewer or no alignment marks. Furthermore, through the arrangement of one or more integral bonding structures, precise alignment and reliable bonding can be established simultaneously, thereby significantly improving production yield and reliability.

[0069] In some embodiments of this invention, a stacked structure including a support structure, a first die, and a second die is provided. The support structure has a first surface and a second surface opposite to the first surface, and a dielectric layer on the first surface. The support structure includes a recess from the first surface that fills the dielectric layer, and a non-metallic alignment mark located in the recess. The first die is disposed above the support structure and is encapsulated by a first encapsulating material. A portion of the first encapsulating material is located between the first die and the support structure. The second die is disposed on a first bonding structure and is encapsulated by a second encapsulating material. The second die includes a second bonding structure and through die vias. The first die and the second die are located on opposite sides of the first bonding structure. The first bonding structure is bonded to the first die and to the second bonding structure of the second die, such that the first and second dies are electrically connected.

[0070] In some embodiments of this utility model, a stacked structure including a first bonding structure, a first die, and a second die is provided. The first die is disposed on a first side of the first bonding structure and includes a second bonding structure. A first encapsulating material covers the first die. The second die is disposed on a second side of the first bonding structure opposite to the first side and includes a third bonding structure and a die perforation. A second encapsulating material covers the second die. The second bonding structure of the first die is bonded to the first bonding structure, and the third bonding structure of the second die is bonded to the first bonding structure located between the first and second dies and the first and second encapsulating materials.

[0071] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this utility model, and are not intended to limit it. Although the utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this utility model.

Claims

1. A stack structure, characterized in that, include: A support structure having a first surface and a second surface opposite to the first surface and a dielectric layer on the first surface, wherein the support structure includes a groove recessed from the first surface and filled by the dielectric layer, and a non-metallic alignment mark located at the groove; A first die is disposed above the support structure and encapsulated by a first encapsulation body, wherein a portion of the first encapsulation body is located between the first die and the support structure; The first bonding structure is disposed on the first encapsulation body and the first die; as well as A second die is disposed on the first bonding structure and encapsulated by a second encapsulator, wherein the second die includes a second bonding structure and a die perforation, wherein the first die and the second die are located on opposite sides of the first bonding structure, and the first bonding structure is bonded to the first die and to the second bonding structure of the second die, thereby electrically connecting the first die and the second die.

2. The stack structure according to claim 1, characterized in that, The first bonding structure includes a first bonding dielectric material and a first bonding pad embedded in the first bonding dielectric material.

3. The stack structure according to claim 2, characterized in that, The first die includes a passivation layer in contact with the first bonding dielectric material, and a first metallization structure therein, wherein the bonding pad via is located between the first bonding pad and the first metallization structure of the first bonding structure.

4. The stack structure according to claim 2, characterized in that, The second bonding structure includes a second bonding dielectric material and a second bonding pad embedded in the second bonding dielectric material, and the bonding interface is located between the first bonding structure and the second bonding structure.

5. The stack structure according to claim 1, characterized in that, The first bonding structure includes an electrical floating pad located next to the bonding region between the first bonding structure and the first and second dies.

6. The stack structure according to claim 1, characterized in that, It also includes a redistribution layer located on the second die and the second encapsulation, and electrically connected to the die perforation of the second die.

7. A stack structure, characterized in that, include: First combination structure; A first die is disposed on a first side of the first bonding structure, wherein the first die includes a second bonding structure; The first encapsulating material covers the area around the first core tube; The second die is disposed on the second side of the first bonding structure opposite to the first side, wherein the second die includes a third bonding structure and a die perforation. as well as The second sealing material covers the area around the second core. Wherein, the second bonding structure of the first die is bonded to the first bonding structure, and the third bonding structure of the second die is bonded to the first bonding structure located between the first die and the second die and the first encapsulation material and the second encapsulation material.

8. The stack structure according to claim 7, characterized in that, The first bonding structure includes an electrically floating marker located next to the bonding area between the first bonding structure and the first die and the second die.

9. The stack structure according to claim 7, characterized in that, It also includes a redistribution layer located on the second die and the second encapsulation material, and electrically connected to the die perforation of the second die.

10. The stack structure according to claim 7, characterized in that, The first bonding structure includes a first bonding dielectric layer and a first bonding pad embedded therein, the second bonding structure includes a second bonding dielectric layer and a second bonding pad embedded therein, and the first interface is located between the bonded first bonding dielectric layer and the second bonding dielectric layer and the bonded first bonding pad and the second bonding pad.

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