Substrateless vertical fan-out package structure

Abstract

The utility model discloses a kind of vertical fan-out packaging structures without substrate, it is related to semiconductor packaging technical field, include dry film type plastic packaging resin, metal wiring layer, memory chip and epoxy resin;Metal wiring layer is below dry film type plastic packaging resin, and it is parallelly arranged with dry film type plastic packaging resin, and packaging space is formed between metal wiring layer and dry film type plastic packaging resin;Memory chip has multiple, multiple memory chip is sequentially staggered and stacked on the bottom surface of dry film type plastic packaging resin along vertical direction, and it is ladder-shaped;The packaging structure of the present scheme memory chip is staggered and stacked and is ladder-shaped along vertical direction, the staggered position of adjacent memory chip is set bonding wire and is connected with metal wiring layer, without relying on a large number of gold finger, more chip can be stacked, it is favorable to improve storage capacity;Meanwhile, bonding wire is connected with metal wiring layer vertically downward, greatly shorten the length of line, reduce the loss in signal transmission process, to reduce power consumption.

Description

Technical Field

[0001] This utility model relates to a substrate-free vertical fan-out packaging structure, belonging to the field of semiconductor packaging technology. Background Technology

[0002] The semiconductor memory industry has always played a crucial role in the wave of globalization. With the rise of emerging technologies such as AI, autonomous driving, and smart terminals, the market demand for memory products is becoming increasingly diversified and differentiated. Traditional wire bonding technology still occupies a pivotal position in the manufacturing of electronic products. The core of wire bonding packaging lies in using metal wires (often made of gold, silver alloys, copper, or palladium-copper wires) to tightly connect the bonding pads on the chip to the metal leads on the packaging substrate.

[0003] Traditional wire bonding packaging requires a substrate as a carrier to mount the chip onto the substrate. The connection between the chip and the substrate is achieved by arranging gold fingers on the substrate. When there are many chip layers, more gold fingers are needed to conduct signals. When the appearance of the packaged product is finalized, due to physical limitations, it is impossible to stack more chips. Moreover, this design has a relatively long wire length, which cannot achieve lower power consumption or larger capacity. Utility Model Content

[0004] To address the aforementioned technical problems, the purpose of this utility model is to propose a substrate-free vertical fan-out packaging structure.

[0005] The technical solution of this utility model is implemented as follows: a substrate-free vertical fan-out packaging structure includes a dry film encapsulating resin, a metal wiring layer, a memory chip, and an epoxy resin; the metal wiring layer is located below the dry film encapsulating resin and is arranged parallel to the dry film encapsulating resin, and an encapsulation space is formed between the metal wiring layer and the dry film encapsulating resin.

[0006] The memory chips are multiple, and the memory chips are stacked vertically and staggered on the bottom surface of the dry film encapsulating resin in a stepped manner; bonding wires are provided at the staggered positions of adjacent memory chips, and the bonding wires on each memory chip extend vertically downward and connect to the upper surface of the metal wiring layer.

[0007] The epoxy resin is located in the encapsulation space formed between the metal wiring layer and the dry film encapsulation resin. The epoxy resin is used to encapsulate all the memory chips and bonding wires in the encapsulation space.

[0008] Preferably, adjacent memory chips and the topmost memory chip are bonded and fixed with dry film encapsulation resin using DAF film.

[0009] Preferably, a plurality of solder balls are uniformly disposed on the lower surface of the metal wiring layer.

[0010] Preferably, the dry film encapsulating resin, the metal wiring layer, and the epoxy resin are all flush on both sides.

[0011] Preferably, the bonding wire is a gold wire.

[0012] Due to the application of the above technical solution, this utility model has the following advantages compared with the prior art:

[0013] In the packaging structure of this utility model, memory chips are stacked in a staggered manner along the vertical direction in a stepped shape. Bonding wires are set at the staggered positions of adjacent memory chips to connect with the metal wiring layer. This eliminates the need for a large number of gold fingers, enabling the stacking of more chips and improving storage capacity. At the same time, the bonding wires are connected vertically downward to the metal wiring layer, which greatly shortens the wire length, reduces signal loss during transmission, and thus reduces power consumption. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this utility model, the drawings used in the description of the embodiments of this utility model will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the content of the embodiments of this utility model and these drawings without creative effort.

[0015] Appendix Figure 1 This is a schematic diagram of a substrate-free vertical fan-out packaging structure according to the present invention.

[0016] In the diagram: 1. Dry film encapsulating resin; 2. Metal wiring layer; 3. Memory chip; 4. Epoxy resin; 5. Bonding wire; 6. DAF film; 7. Solder ball. Detailed Implementation

[0017] To make the technical problems solved by this utility model, the technical solutions adopted, and the technical effects achieved clearer, the technical solutions of the embodiments of this utility model will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0018] In the description of this utility model, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "straight," "horizontal," "inner," and "outer," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this utility model. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. The terms "first position" and "second position" refer to two different positions.

[0019] In the description of this utility model, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to fixed connections or detachable connections; mechanical connections or electrical connections; direct connections or indirect connections through an intermediate medium; and internal connections between two components. Those skilled in the art can understand the specific meaning of the above terms in this utility model based on the specific circumstances.

[0020] As attached Figure 1 As shown, the substrate-free vertical fan-out packaging structure of this utility model includes a dry film encapsulating resin 1, a metal wiring layer 2, a memory chip 3, and an epoxy resin 4.

[0021] The metal wiring layer 2 is located below the dry film encapsulation resin 1 (Dry film EMC) and is arranged parallel to the dry film encapsulation resin 1. An encapsulation space is formed between the metal wiring layer 2 and the dry film encapsulation resin 1. This encapsulation space provides a space for accommodating the stacking of memory chips 3 and the connection of bonding wires 5.

[0022] In this embodiment, to ensure the integrity and consistency of the encapsulation structure, the two sides of the dry film encapsulation resin 1, the metal wiring layer 2, and the epoxy resin 4 are kept flush to avoid assembly or application problems caused by structural misalignment.

[0023] There are multiple memory chips 3, which are stacked vertically in a staggered manner on the bottom surface of the dry film encapsulating resin 1 in a stepped shape. In this embodiment, there are 4 memory chips 3. The topmost memory chip 3 is bonded and fixed to the dry film encapsulating resin 1 and to adjacent memory chips 3 by a DAF film 6. The DAF film 6 has good adhesive properties and can ensure the stability of the connection between memory chips 3. In use, the number of memory chips 3 can be increased or decreased according to the actual situation, which is not limited here.

[0024] Bonding wires 5 are provided at staggered positions on adjacent memory chips 3. The bonding wires 5 on each memory chip 3 extend vertically downward and are connected to the upper surface of the metal wiring layer 2. In this embodiment, the bonding wires 5 are made of gold wire, which has excellent conductivity and can ensure efficient signal transmission. Of course, the bonding wires 5 can also be made of materials commonly used in the art, such as copper wire. Each memory chip 3 is provided with two bonding wires 5 connected to the metal wiring layer 2 to further improve the stability of signal transmission.

[0025] In this structure, the memory chips 3 are stacked in a staggered manner along the vertical direction in a stepped shape. The staggered positions of adjacent memory chips 3 are provided with bonding wires 5 to connect with the metal wiring layer 2. This eliminates the need for a large number of gold fingers, enabling the stacking of more chips and improving storage capacity. At the same time, the bonding wires 5 are connected vertically downward to the metal wiring layer 2, which greatly shortens the wire length, reduces signal loss during transmission, and thus reduces power consumption.

[0026] The epoxy resin 4 is located in the encapsulation space formed between the metal wiring layer 2 and the dry film encapsulation resin 1. The epoxy resin 4 is used to encapsulate all the memory chips 3 and bonding wires 5 in the encapsulation space. After the epoxy resin 4 is cured, it forms a hard protective layer that can isolate external moisture, dust and other pollutants, and enhance the impact resistance of the structure.

[0027] Furthermore, the metal wiring layer 2 not only serves as the connection carrier for the bonding wires 5, but also undertakes the function of signal distribution. Multiple solder balls 7 are uniformly arranged on its lower surface. The solder balls 7 serve as the connection interface between the package structure and the external circuit board, and electrical connection is achieved through reflow soldering.

[0028] The packaging process of this utility model is as follows:

[0029] Step 1

[0030] Carrier preparation:

[0031] The glass substrate is placed horizontally on the encapsulation platform, and the dry film encapsulating resin 1 is placed on the glass substrate and fixed. The glass substrate has good flatness and high temperature resistance and can be used as a temporary support carrier. In this embodiment, the dry film encapsulating resin 1 can be placed flat on the glass substrate by vacuum adsorption or mechanical fixation to ensure that there is no relative displacement between the dry film encapsulating resin 1 and the glass substrate.

[0032] Step Two

[0033] Chip stacking:

[0034] Multiple memory chips 3 are staggered and mounted on top of dry film encapsulation resin 1 layer by layer through DAF film 6. It should be noted that the memory chips 3 are temporarily stacked upwards at this time and will eventually be flipped. The misalignment accuracy of the chips is strictly controlled during mounting to ensure the formation of a stepped structure.

[0035] Step 3

[0036] Bonded connection:

[0037] Vertical bonding lines 5 are applied to the pads at staggered positions on each memory chip 3, and temporarily suspended until subsequent connection.

[0038] Step Four

[0039] Molding:

[0040] All memory chips 3 and bonding wires 5 are encapsulated inside epoxy resin 4, so that all memory chips 3 and bonding wires 5 are completely wrapped, and then cured by heating to form a molded body.

[0041] Step 5

[0042] Wiring and Connections:

[0043] The upper surface of epoxy resin 4 (i.e. the side away from the glass substrate) is ground to expose the bonding wires 5, and the circuit is rearranged on the bonding wires 5 to form a metal wiring layer 2.

[0044] Step Six

[0045] External interface preparation:

[0046] Solder balls 7 are implanted on the upper surface of the metal wiring layer 2 using a ball-planting process. The position of the solder balls 7 corresponds to the wiring pattern of the metal wiring layer 2, thereby conducting the signal.

[0047] Step Seven

[0048] Structural flipping and separation:

[0049] Flip the package from step S6 180° so that the dry film encapsulation resin 1 is on top, the metal wiring layer 2 and the solder balls 7 are on the bottom, and finally remove the glass substrate to complete the fabrication.

[0050] The above embodiments are only for illustrating the technical concept and features of this utility model. Their purpose is to enable those skilled in the art to understand the content of this utility model and implement it. They should not be used to limit the protection scope of this utility model. All equivalent changes or modifications made in accordance with the spirit and essence of this utility model should be covered within the protection scope of this utility model.

Claims

1. A substrate-free vertical fan-out packaging structure, characterized in that: It includes a dry film encapsulating resin (1), a metal wiring layer (2), a memory chip (3), and an epoxy resin (4); the metal wiring layer (2) is located below the dry film encapsulating resin (1) and is arranged parallel to the dry film encapsulating resin (1), and an encapsulation space is formed between the metal wiring layer (2) and the dry film encapsulating resin (1); There are multiple memory chips (3), and the multiple memory chips (3) are stacked in a staggered manner along the vertical direction on the bottom surface of the dry film encapsulation resin (1) in a stepped shape; bonding lines (5) are provided at the staggered positions of adjacent memory chips (3), and the bonding lines (5) on each memory chip (3) extend vertically downward and are connected to the upper surface of the metal wiring layer (2). The epoxy resin (4) is located in the encapsulation space formed between the metal wiring layer (2) and the dry film encapsulation resin (1). The epoxy resin (4) is used to encapsulate all the memory chips (3) and bonding wires (5) in the encapsulation space. The adjacent memory chips (3) and the topmost memory chip (3) are bonded and fixed with the dry film encapsulation resin (1) by a DAF film (6).

2. The substrate-free vertical fan-out packaging structure according to claim 1, characterized in that: The lower surface of the metal wiring layer (2) is uniformly provided with a plurality of solder balls (7).

3. The substrate-free vertical fan-out packaging structure according to claim 1, characterized in that: The dry film encapsulating resin (1), the metal wiring layer (2), and the epoxy resin (4) are all flush on both sides.

4. The substrate-free vertical fan-out packaging structure according to claim 1, characterized in that: The bonding wire (5) is a gold wire.

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