An infrared detector signal processing device and system based on a domestic chip

Abstract

The utility model provides a kind of infrared detector signal processing device and system based on domestic chip, by adopting FPGA chip as the main control chip of equipment, based on the characteristics of logic parallel processing simultaneously carries out image data processing, ADC and peripheral chip control such as FLASH, monitor equipment environment temperature and humidity, collect the data after infrared detector by ADC analog-digital conversion, and carry out correction and bad element processing and other processing, output to equipment exterior by optical fiber transceiver module, realize the purpose of improving the multitasking processing capacity of infrared imaging related equipment.The utility model uses optical fiber to carry out equipment communication and data transmission, with transmission distance far, transmission loss low, not by electromagnetic interference ability.The utility model uses the chip of nationwide production, with higher self-controllability.

Description

Technical Field

[0001] This utility model belongs to the field of infrared signal processing technology, specifically relating to an infrared detector signal processing device and system based on domestically produced chips. Background Technology

[0002] Infrared imaging technology is commonly used in critical sectors such as defense, aerospace, and power. To address the severe international situation and ensure national and supply chain security, it is necessary to localize infrared imaging equipment. Existing infrared imaging systems typically require parallel processing of large amounts of data, including processing and converting analog data such as image data, temperature data, and humidity data collected by sensors. Their multi-tasking capabilities are insufficient to meet the requirements. Utility Model Content

[0003] The technical problem to be solved by this utility model is to provide an infrared detector signal processing device and system based on domestically produced chips, which can improve the multi-task processing capability of infrared imaging related equipment.

[0004] The technical solution adopted by this utility model to solve the above-mentioned technical problems is as follows: an infrared detector signal processing device based on domestically produced chips, including: FPGA, FLASH, infrared detector, ADC, DDR3, temperature and humidity sensor and fiber optic transceiver module; the FPGA is connected to the FLASH through a QSPI interface; the detector control terminal of the FPGA is connected to the driver terminal of the infrared detector; the FPGA is connected to the register configuration interface of the ADC through an SPI port; the data interface of the ADC is connected to the FPGA through a serial differential pair interface; the FPGA is connected to the DDR3 through a bidirectional data port; the FPGA is connected to the temperature and humidity sensor through an IIC interface; the FPGA is connected to the fiber optic transceiver module through a GTX high-speed interface.

[0005] According to the above scheme, FLASH includes an FPGA runtime program storage unit, a parameter storage unit, a correction data storage unit, and a bad data storage unit.

[0006] According to the above scheme, DDR3 includes a correction data storage unit and a bad metadata storage unit.

[0007] According to the above scheme, the FPGA includes an image correction unit, a bad element replacement unit, and a spatiotemporal noise reduction unit.

[0008] According to the above scheme, the temperature measurement range of the temperature and humidity sensor is -45 to 130℃, and the relative humidity measurement range is 0 to 100%.

[0009] Furthermore, it also includes a power supply chip; the power supply chip includes a first power supply, a second power supply, and a third power supply.

[0010] Furthermore, the first power supply is connected to the FPGA through a 1VDC output port, to the FPGA and ADC through a 1.8VDC output port, and to the FPGA, FLASH and temperature and humidity sensor through a 3.3VDC output port.

[0011] Furthermore, the second power supply is connected to the FPGA through 2VDC and 2.5VDC output ports, to the FPGA and DDR3 through a 1.35VDC output port, and to the fiber optic transceiver module through a 3.3VDC output port.

[0012] Furthermore, a third power supply is connected to the ADC via a 1.8VDC output port.

[0013] An infrared detector signal processing system based on domestically produced chips includes an infrared detector signal processing device based on domestically produced chips.

[0014] The beneficial effects of this utility model are as follows: 1. This utility model discloses an infrared detector signal processing device and system based on domestically produced chips. By using an FPGA chip as the main control chip of the device, and based on the characteristics of parallel logic processing, it simultaneously performs image data processing, ADC and FLASH control, etc. It collects the data of the infrared detector after analog-to-digital conversion by ADC, and outputs it to the outside of the device through an optical fiber transceiver module, thereby achieving the purpose of improving the multi-task processing capability of infrared imaging related equipment.

[0015] 2. This utility model uses optical fiber for device communication and data transmission, which has the ability to transmit over long distances, with low transmission loss and immunity to electromagnetic interference.

[0016] 3. This utility model uses domestically produced chips, which have a high degree of independent controllability.

[0017] Of course, any product implementing this utility model does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of an embodiment of the present utility model.

[0020] Figure 2 This is a schematic diagram of the power supply chip according to an embodiment of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this utility model and are not intended to limit this utility model.

[0022] Example 1 See Figure 1 An infrared detector signal processing device based on domestically produced chips includes an FPGA chip, an ADC chip, a FLASH chip, a DDR3 chip, an optical fiber transceiver module, a temperature and humidity sensor, and a power supply chip. The FPGA is the main control chip and is connected to the DDR3, FLASH, optical fiber transceiver module, temperature and humidity sensor, and ADC. The power supply chip is connected to the FPGA, DDR3, FLASH, ADC, temperature and humidity sensor, etc., to supply power to the chips in the device.

[0023] The FPGA is used to drive the infrared detector, acquire ADC data, and perform image correction, bad element replacement, and spatiotemporal noise reduction on the ADC data, and finally output it to the fiber optic transceiver module. The FLASH memory is connected to the FPGA via the QSPI interface and is used to store the program running on the FPGA and the parameters, calibration data, and bad data stored during device use. The ADC chip is used to convert the analog signal output by the infrared detector into a digital signal. The ADC chip has two types of connection interfaces with the FPGA: one is the SPI interface, and the other is the serial differential pair interface. The FPGA configures the registers of the ADC chip through the SPI interface. The ADC chip outputs digital signals to the FPGA through the serial differential pair interface. There are two DDR3 chips, each containing 16 data bits and 14 address bits. DDR3 is used to store the data required when the device is working, including the correction data needed when the FPGA performs correction and the bad data needed when the FPGA performs bad element replacement. When the device is powered on, the FPGA chip reads the correction data and bad data from the FLASH chip and writes them into DDR3. The fiber optic transceiver module is connected to the GTX high-speed interface of the FPGA chip through TX and RX signals. It is used to convert the electrical signals output by the FPGA into optical signals for external data transmission through optical fiber, and to convert the optical signals received from external systems into electrical signals and output them to the FPGA. The power supply chip includes a first power supply, a second power supply, and a third power supply. The first power supply outputs 1V to power the FPGA, 1.8V to power the FPGA and ADC, and 3.3V to power the FPGA, FLASH, and temperature and humidity sensor. The second power supply outputs 2V and 2.5V to power the FPGA, 1.35V to power the FPGA and DDR3, and 3.3V to power the fiber optic transceiver module. The third power supply outputs 1.8V to power the ADC. The temperature and humidity sensor is used to measure the internal temperature and humidity of the equipment. It can measure the temperature in the range of -45 to 130℃ and the relative humidity in the range of 0 to 100%. The FPGA reads and writes the registers of the temperature and humidity sensor through the IIC bus. The FPGA chip, ADC chip, FLASH chip, DDR3 chip, fiber optic transceiver module, power chip, temperature and humidity sensor, and power chip are all domestically produced components.

[0024] The workflow of this embodiment is as follows: When the device is powered on, the FPGA loads and runs the program from the FLASH, and reads the correction data and bad data from the FLASH chip and writes them into DDR3; During normal operation, the FPGA outputs drive signals to control the infrared detector. The infrared detector outputs an analog signal; The ADC performs analog-to-digital conversion on analog signals and outputs digital signals that are then fed into the FPGA. After the FPGA processes the data, including correction and bad element handling, it outputs the data to the fiber optic transceiver module. Finally, the signal is output to the outside of the device through the fiber optic transceiver module. The fiber optic transceiver module converts the electrical signal output by the FPGA into an optical signal and transmits the data to the outside through the optical fiber. It also converts the optical signal received from the external system into an electrical signal and outputs it to the FPGA.

[0025] This embodiment uses an FPGA chip as the main control chip of the device. Based on the characteristics of parallel logic processing, it simultaneously performs image data processing, controls peripheral chips such as ADC and FLASH, collects data from the infrared detector after analog-to-digital conversion by ADC, and performs correction and bad element processing. The data is then output to the outside of the device through the fiber optic transceiver module, thereby improving the multi-task processing capability of infrared imaging-related equipment.

[0026] Example 2 The principle and structure of this embodiment are the same as those of Embodiment 1, except that each step is applied to a specific instance.

[0027] The device includes an FPGA chip, an ADC chip, a FLASH chip, a DDR3 chip, a fiber optic transceiver module, and a power supply chip. The FPGA is the main control chip of this device and is connected to the DDR3, FLASH, fiber optic transceiver module, temperature and humidity sensor, temperature sensor, and ADC. In this embodiment, the FPGA chip is Shenzhen Guowei SMQ7K325T, the FLASH chip is GigaDevice GD25S513MD, the DDR3 chip is Shenzhen Guowei SM41J128M16M, the fiber optic transceiver module is AVIC Optoelectronic OEA02-D23-311-613, the power supply chip is either Shenzhen Guowei SM4644MPY or Galileo Electronics GED1963, the temperature and humidity sensor is Zhongke Yinhexin GXHT31, the temperature sensor is Zhongke Yinhexin GX18B20U, and the ADC chip is Aerospace Minxin AS9653.

[0028] See Figure 2 There are three power supply chips of two models, referred to as Power Supply 1, Power Supply 2, and Power Supply 3. Under normal power supply conditions, Power Supply 1 outputs 1V (VCC1V), 1.8V (VCC1V8), and 3.3V (VCC3V3); Power Supply 2 outputs 2V (VCC2V), 2.5V (VCC2V5), 1.35V (VCC1V35), and 3.3V (VCCMT); Power Supply 3 outputs 1.8V (VAD1V8).

[0029] VCC1V powers the FPGA, VCC1V8 powers the FPGA and ADC, VCC3V3 powers the FPGA, FLASH, and temperature and humidity sensor, VCC2V powers the FPGA, VCCMT powers the fiber optic transceiver module, VCC2V5 powers the FPGA, VCC1V35 powers the FPGA and DDR3, and VAD1V8 powers the ADC.

[0030] After the device is powered on, the FPGA loads the program from the FLASH and reads the parameters used by the device during operation. It reads the bad element information and calibration table data from the FLASH and writes them into DDR3. The FPGA chip configures the ADC chip registers through the SPI interface to make it work normally. The FPGA chip uses AURORA IP to initialize the connection with the external device through the optical fiber and performs the temperature sensor reset operation through the IIC port.

[0031] During operation, the infrared detector outputs four analog signals. The ADC converts these analog signals into four digital signals, which are then input to the FPGA chip. The FPGA chip reads the calibration table data and bad element information from the DDR3 memory, performs calibration and bad element processing on the ADC input data, and then outputs it to the external FPGA via the AURORA IP. The data is then converted into optical signals and transmitted to the external system via a fiber optic transceiver module. Simultaneously, the FPGA chip acquires data from the temperature sensor to obtain the internal temperature and humidity information of the device, and monitors the infrared detector housing temperature. Monitoring data can be uploaded to the external system in real time via fiber optic cable, and the external system can also control and remotely update the device via fiber optic cable.

[0032] This embodiment uses optical fiber for device communication and data transmission, which has the ability to transmit over long distances, with low transmission loss and immunity to electromagnetic interference; this embodiment uses domestically produced chips, which have a high degree of autonomy and controllability.

[0033] Example 3 This embodiment is used to implement the principle of the above product embodiment to construct an infrared detector signal processing system based on a domestic chip, including an infrared detector signal processing device based on a domestic chip, as well as a host computer and other devices that use the output signal of the device.

[0034] It should be noted that, depending on the implementation needs, the various components described in this application can be divided into more components, or two or more components or parts of the operation of components can be combined into new components to achieve the purpose of this utility model.

[0035] The above embodiments are only used to illustrate the design concept and features of this utility model, and their purpose is to enable those skilled in the art to understand the content of this utility model and implement it accordingly. The protection scope of this utility model is not limited to the above embodiments. Therefore, all equivalent changes or modifications made based on the principles and design ideas disclosed in this utility model are within the protection scope of this utility model.

Claims

1. A signal processing device for an infrared detector based on a domestically produced chip, characterized in that: Includes FPGA, FLASH, infrared detector, ADC, DDR3, temperature and humidity sensor and fiber optic transceiver module; The FPGA connects to the FLASH memory via the QSPI interface; The detector control terminal of the FPGA is connected to the driver terminal of the infrared detector; The FPGA connects to the ADC's register configuration interface via an SPI port; the ADC's data interface connects to the FPGA via a serial differential pair interface. The FPGA connects to DDR3 via a bidirectional data port; The FPGA connects to the temperature and humidity sensor via the IIC interface; The FPGA is connected to the fiber optic transceiver module via the GTX high-speed interface.

2. The infrared detector signal processing device based on a domestically produced chip according to claim 1, characterized in that: FLASH includes FPGA runtime program storage unit, parameter storage unit, correction data storage unit, and bad data storage unit.

3. The infrared detector signal processing device based on a domestically produced chip according to claim 1, characterized in that: DDR3 includes a correction data storage unit and a bad metadata storage unit.

4. The infrared detector signal processing device based on a domestically produced chip according to claim 1, characterized in that: An FPGA includes an image correction unit, a bad pixel replacement unit, and a spatiotemporal noise reduction unit.

5. The infrared detector signal processing device based on a domestically produced chip according to claim 1, characterized in that: The temperature and humidity sensor has a temperature measurement range of -45 to 130℃ and a relative humidity measurement range of 0 to 100%.

6. The infrared detector signal processing device based on a domestically produced chip according to claim 5, characterized in that: It also includes a power supply chip; the power supply chip includes a first power supply, a second power supply, and a third power supply.

7. The infrared detector signal processing device based on a domestically produced chip according to claim 6, characterized in that: The first power supply is connected to the FPGA through a 1VDC output port, to the FPGA and ADC through a 1.8VDC output port, and to the FPGA, FLASH and temperature and humidity sensor through a 3.3VDC output port.

8. The infrared detector signal processing device based on a domestically produced chip according to claim 6, characterized in that: The second power supply is connected to the FPGA through 2VDC and 2.5VDC output ports, to the FPGA and DDR3 through a 1.35VDC output port, and to the fiber optic transceiver module through a 3.3VDC output port.

9. The infrared detector signal processing device based on a domestically produced chip according to claim 6, characterized in that: The third power supply is connected to the ADC via a 1.8VDC output port.

10. A signal processing system for an infrared detector based on a domestically produced chip, characterized in that: The invention includes an infrared detector signal processing device based on a domestically produced chip, as described in any one of claims 1 to 9.

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