A digital phase difference detection system based on DSP

Abstract

The utility model discloses a digital phase difference detection system based on DSP belongs to signal processing technical field. In order to solve the precision low, stability poor because of RC device temperature drift of existing analog phase difference detection circuit, and because of the low pass filter leading to the technical problem of big response delay, the utility model provides a novel system structure. The system includes: a former stage signal conditioning module that input analog signal is converted to square wave, a core processing module adopts the microcontroller of built -in high frequency timer, and the time stamp of square wave edge is accurately recorded through input capture function, and the phase difference is calculated with the pure digital operation mode instead of traditional low pass filter, and an output module that digital result is converted to analog voltage. The utility model is with hardware time stamp capture and digital operation's structure, has replaced the analog filter circuit of being easily affected by temperature drift.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology, specifically relating to a DSP-based digital phase difference detection system. Background Technology

[0002] Phase difference detection is a fundamental and crucial technology in signal processing, widely used in power systems, communication engineering, automatic control, ultrasonic non-destructive testing, and precision instrument measurement, among many other fields. Its core task is to accurately measure the phase relationship between two signals of the same frequency along the time axis.

[0003] In existing technologies, a common method for phase difference detection is to use analog circuits. This approach typically consists of an analog multiplier or XOR gate as a phase comparator, followed by a low-pass filter (usually an RC filter circuit). The working principle is that the phase comparator outputs a pulse-width modulation (PWM) signal containing phase difference information. This signal is then smoothed by the integration of the low-pass filter, ultimately converting it into a DC voltage proportional to the phase difference. However, this purely analog implementation has inherent technical drawbacks. First, the parameters of passive components such as resistors (R) and capacitors (C) in the core low-pass filter are highly sensitive to temperature changes, resulting in temperature drift. This directly leads to unstable output of the detection system, low measurement accuracy, and difficulty in ensuring consistent results under different operating environments. Second, to obtain a smooth DC output, the time constant of the low-pass filter usually needs to be set relatively large, which inevitably leads to a long response delay. This makes the system slow to respond to dynamic changes in phase difference, resulting in poor real-time performance and making it difficult to meet the requirements of high-speed, real-time control or measurement applications.

[0004] Therefore, how to design a phase difference detection system that can overcome the influence of temperature drift in traditional analog circuits, improve measurement accuracy and stability, and significantly shorten response delay and improve system real-time performance is a technical problem that urgently needs to be solved in this field. Utility Model Content

[0005] The purpose of this invention is to address the deficiencies mentioned in the background art by proposing a DSP-based digital phase difference detection system.

[0006] The technical solution adopted in this utility model is as follows:

[0007] This utility model provides a DSP-based digital phase difference detection system, comprising:

[0008] A pre-amplifier signal conditioning module is used to convert two input analog signals of the same frequency into two square wave signals with the same phase relationship;

[0009] A core processing module is electrically connected to the output of the pre-amplifier signal conditioning module. The core processing module is equipped with a high-frequency timer as a time reference and is configured to use an input capture function to capture the signal edges of the two square wave signals respectively and record their corresponding timestamps. The core processing module is also configured to calculate the time difference between the two square wave signals based on their timestamps, measure the period of one of the square wave signals, and then obtain the phase difference between the two analog signals through digital calculation.

[0010] An output module, electrically connected to the core processing module, is used to convert the digitized phase difference result calculated by the core processing module into an analog voltage signal for output.

[0011] As a preferred technical solution of this utility model: the radar-visual fusion flow meter is installed at equal intervals under the bridge and above the water.

[0012] As a preferred technical solution of this utility model: the radar-visual fusion flow meter is installed at the edge of the water area by a bracket.

[0013] As a preferred technical solution of this utility model: the pre-stage signal conditioning module includes two high-speed comparators, and the two analog signals are respectively input to the signal input terminals of the two high-speed comparators.

[0014] As a preferred technical solution of this utility model: the signal input terminal of each of the high-speed comparators is a non-inverting input terminal, and its inverting input terminal is connected to a reference voltage for detecting the zero crossing point of the signal.

[0015] As a preferred technical solution of this utility model: the core processing module is a microcontroller that integrates a digital signal processing instruction set.

[0016] As a preferred technical solution of this utility model: the microcontroller is configured with two or more timer input capture channels, which are used to capture the two square wave signals respectively.

[0017] As a preferred technical solution of this utility model: the high-frequency timer is a free-counting timer that runs independently inside the microcontroller, the timestamp is the moment when the input capture event occurs, and the count value of the free-counting timer is latched to obtain the value.

[0018] As a preferred technical solution of this utility model, the output module is a digital-to-analog converter.

[0019] As a preferred technical solution of this utility model, the digital-to-analog converter is integrated inside the microcontroller of the core processing module.

[0020] As a preferred embodiment of this utility model, it further includes a power supply module for providing operating voltage to the front-end signal conditioning module and the core processing module.

[0021] The DSP-based digital phase difference detection system provided by this invention has the following advantages compared with the prior art:

[0022] This invention employs a core processing module to capture the timestamp of the shaped square wave signal using a high-frequency timer, and internally calculates the phase difference entirely through digital computation. The entire core calculation process is based on a stable crystal oscillator clock and does not rely on any analog components such as resistors and capacitors that are susceptible to ambient temperature effects. This fundamentally eliminates measurement errors caused by component temperature drift, resulting in extremely high accuracy and excellent operational stability in the detection results.

[0023] Furthermore, the phase difference calculation and result output of this invention can be completed within a single signal cycle, and the processing speed depends only on the operation clock frequency of the core processing module, typically at the microsecond level. Compared to the millisecond-level charging and discharging time delay of the low-pass filter in traditional analog schemes, this invention achieves an order-of-magnitude improvement in response speed, greatly reduces output latency, possesses excellent real-time performance, and can accurately capture and respond to instantaneous changes in phase difference. Attached Figure Description

[0024] Figure 1 This is an overall structural block diagram of one embodiment of the present utility model.

[0025] Explanation of reference numerals in the attached diagram: 101, pre-amplifier signal conditioning module; 102, core processing module; 103, output module; 104, power supply module. Detailed Implementation

[0026] It should be noted that, unless otherwise specified, the embodiments and features described in this embodiment can be combined with each other. The technical solutions of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this utility model, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this utility model without creative effort are within the scope of protection of this utility model.

[0027] Please see Figure 1 , Figure 1This is an overall structural block diagram of a DSP-based digital phase difference detection system according to one embodiment of the present invention. The system can detect the phase difference between two input analog signals with high precision and real-time performance, and output an analog voltage proportional to the phase difference.

[0028] Specifically, the digital phase difference detection system described in this embodiment includes: a pre-stage signal conditioning module 101, a core processing module 102, an output module 103, and a power supply module 104.

[0029] The input terminal of the pre-amplifier signal conditioning module 101 is used to receive two external analog ultrasonic signals of the same frequency, such as the first analog signal Phase_A_In and the second analog signal Phase_B_In. Its main function is to convert these two sinusoidal signals with a phase difference into digital square wave signals with the same phase relationship. The output terminal of this module is electrically connected to the signal acquisition pin of the core processing module 102.

[0030] The core processing module 102 is the control and calculation core of the entire system. It is electrically connected between the pre-amplifier signal conditioning module 101 and the output module 103. Its function is to accurately capture the edge time points of the two square wave signals output by the pre-amplifier signal conditioning module 101, timestamp them based on a high-frequency clock, and quickly calculate the period and phase difference of the two signals through the built-in digital signal processing (DSP) algorithm.

[0031] The output module 103 is electrically connected to the core processing module 102 and is used to convert the digitized phase difference result calculated by the core processing module 102 into a linear and continuous analog voltage signal V_OUT for output, so that it can be used by subsequent circuits or for display.

[0032] The power supply module 104 provides a stable and clean operating voltage for all active devices in the system, such as the pre-amplifier signal conditioning module 101 and the core processing module 102.

[0033] The internal circuit structure, component selection, and pin-level connection relationships of each module will be described in detail below.

[0034] In this embodiment, the pre-amplifier signal conditioning module 101 includes two high-speed comparators, specifically the Texas Instruments (TI) TLV3201 chip. This model is chosen because it has a fast response time of 40ns, ensuring accurate capture of the zero-crossing point of the input signal; simultaneously, its built-in hysteresis function is equivalent to a Schmitt trigger, effectively preventing oscillations in the output signal near the comparison threshold caused by noise or slow changes in the input signal, thus ensuring clear and stable edges of the shaped square wave.

[0035] For the processing path of the first analog signal Phase_A_In, Phase_A_In is sent to the non-inverting input (IN+) of the first TLV3201 comparator. A reference voltage is applied to the inverting input (IN-) of the comparator. In this embodiment, this reference voltage can be obtained by dividing the 3.3V power supply using two precision resistors, resulting in a value of 1.65V, which is half of the power supply voltage, used to accurately detect the zero-crossing point of the sinusoidal signal. The first square wave signal Phase_A_SQ generated by the output (OUT) of this comparator is transmitted to the core processing module 102. Similarly, the processing path of the second analog signal Phase_B_In also uses the same circuit structure, that is, Phase_B_In is connected to the non-inverting input (IN+) of the second TLV3201 comparator, the 1.65V reference voltage is connected to its inverting input (IN-), and the second square wave signal Phase_B_SQ generated by its output (OUT) is also transmitted to the core processing module 102.

[0036] The core component of the core processing module 102 is a microcontroller (MCU), specifically an STMicroelectronics STM32G474RET6 chip with a built-in DSP instruction set and floating-point unit (FPU). This MCU is based on a high-performance ARM Cortex-M4 core, and its integrated hardware resources are well-suited to the technical solution of this invention. Its built-in high-resolution timer (HRTIM) or multiple general-purpose advanced timers support nanosecond-level input capture, which is crucial for achieving high-precision timestamp recording.

[0037] The specific pin connections are as follows: The first square wave signal, Phase_A_SQ, output from the pre-amplifier signal conditioning module 101, is connected to pin PA8 of the STM32G474RET6 microcontroller. This pin is configured in software for the input capture function of channel 1 (TIM1_CH1) of Timer 1. The second square wave signal, Phase_B_SQ, output from the pre-amplifier signal conditioning module 101, is connected to pin PB4 of the microcontroller. This pin is configured for the input capture function of channel 1 (TIM3_CH1) of Timer 3.

[0038] In this embodiment, the output module 103 cleverly utilizes the 12-bit resolution digital-to-analog converter (DAC) integrated on-chip by the STM32G474RET6 microcontroller, eliminating the need for any external DAC chip. The microcontroller's PA4 pin is configured as the analog output channel of DAC1 (DAC1_OUT1), which directly serves as the final analog voltage output V_OUT of the entire system. This design greatly simplifies the peripheral circuitry, reduces hardware costs and power consumption, and improves system integration.

[0039] In this embodiment, the power module 104 employs a low-dropout linear regulator (LDO), such as the AMS1117-3.3. An externally input 5V DC power supply is connected to the input pin (VIN) of the AMS1117-3.3, while its output pin (VOUT) outputs a stable 3.3V DC voltage. This 3.3V voltage serves as the main power supply, uniformly powering all digital power pins (VDD) and analog power pins (VDDA) of the STM32G474RET6 microcontroller, as well as the power supply pins (VCC) of the two TLV3201 comparators. To ensure the purity and stability of the power supply, a 100nF decoupling capacitor is connected in parallel to ground near each power pin of the microcontroller.

[0040] Based on the above hardware structure, the overall working principle and operation process of this utility model embodiment are described as follows:

[0041] The first step is signal shaping. When the two analog ultrasonic signals, Phase_A_In and Phase_B_In, with a phase difference, are input to the pre-amplifier signal conditioning module 101, they are processed by two TLV3201 high-speed comparators. When the instantaneous voltage of the input signal rises from a reference voltage below 1.65V to above 1.65V, the comparator outputs a high level; conversely, when the signal voltage drops from above 1.65V to below 1.65V, the comparator outputs a low level. Thus, the two analog sine waves are accurately converted into two square wave signals, Phase_A_SQ and Phase_B_SQ, with steep edges and distinct logic levels, and these two square wave signals completely retain the phase relationship between the original signals.

[0042] The second step is timestamp capture. Inside the core processing module 102, a high-precision general-purpose timer (e.g., TIM2) is first configured as the system's time base. Assuming the microcontroller's main frequency is 170MHz, TIM2 can be configured to freely increment at a frequency of 170MHz, and its count value (CNT) acts like a high-resolution "time ruler." Simultaneously, timers TIM1 and TIM3 are configured in input capture mode and set to be triggered by the rising edge event of their respective channels (TIM1_CH1 and TIM3_CH1). When the first square wave signal, Phase_A_SQ, has a rising edge on the PA8 pin, the hardware logic of TIM1 will instantly and automatically copy (latch) the current count value of TIM2 into the capture / compare register (CCR1) of TIM1, recording it as the timestamp Timestamp_A. Similarly, when the second square wave signal Phase_B_SQ has a rising edge on the PB4 pin, the hardware logic of TIM3 automatically latches the current count value of TIM2 into the capture / compare register (CCR1) of TIM3, denoted as Timestamp_B. To accurately measure the signal period, TIM1 can be configured to capture two rising edges consecutively, with the timestamp of the second capture denoted as Timestamp_A_Next. The signal period count value is then T_Period = Timestamp_A_Next - Timestamp_A. The entire capture process is automatically completed by the timer hardware without CPU software intervention, ensuring nanosecond-level accuracy of the timestamp. To further reduce the CPU load, a DMA (Direct Memory Access) controller can be configured to automatically move the timestamp data from the CCR register to a predetermined variable in memory after each capture event, achieving zero-CPU-occupancy data acquisition.

[0043] The third step is phase difference calculation. After a complete signal cycle is measured (e.g., when Timestamp_A_Next is captured), an interrupt can be triggered to notify the CPU to perform calculations. The CPU reads the latest timestamps Timestamp_A, Timestamp_B, and the period value T_Period from memory. The software first verifies whether the period value T_Period is within a preset reasonable range to ensure the frequency of the input signal is valid. Subsequently, the time difference count value T_Diff = Timestamp_B - Timestamp_A between the rising edges of the two signals is calculated. Here, the software logic needs to handle the case where the TIM2 counter overflows (flips back to 0 from its maximum value) between two captures. This can be achieved by judging the size relationship of the timestamps and performing corresponding compensation calculations, which is a standard processing method well known to those skilled in the art. Finally, high-speed floating-point operations are performed using the DSP instruction set or FPU, and the phase difference between the two signals is accurately calculated according to the formula: Phase Difference (degrees) = (T_Diff / T_Period) × 360.

[0044] The fourth step is analog output. The calculated phase difference (e.g., effective range of 0-180 degrees) needs to be mapped to the DAC output range of output module 103. Taking a 12-bit DAC as an example, its digital input range is 0-4095. If a phase difference of 0-180 degrees is required to linearly correspond to a voltage output of 0-3.3V, the mapping formula is: DAC digital value = (phase difference / 180.0) × 4095. The software will limit the calculated phase difference value; for example, if it is greater than 180 degrees, it will be calculated as 180 degrees. The CPU writes the finally calculated DAC digital value into the on-chip DAC data register. The DAC hardware module will immediately convert this digital value into the corresponding analog voltage and output it stably through the PA4 pin, completing the entire detection and conversion process.

[0045] In summary, the DSP-based digital phase difference detection system provided by this invention achieves precise signal shaping through a high-speed comparator, captures high-precision hardware timestamps using a high-performance timer built into the microcontroller, and performs rapid digital calculations in conjunction with its DSP core, ultimately outputting an analog voltage through an on-chip DAC. This solution features highly integrated and simple hardware circuitry, completely eliminating the RC filter network susceptible to temperature drift found in traditional analog solutions, resulting in extremely high stability and accuracy of the measurement results. Furthermore, the entire processing flow can be completed within a single signal cycle, achieving low-latency real-time output at the millisecond or even microsecond level. The digital processing method inherently provides strong anti-interference capabilities, making it a promising application in industrial control, precision measurement, and other fields.

[0046] The above description is merely a preferred embodiment of the present utility model and is not intended to limit the present utility model in any way. Any modifications, additions, or substitutions made by those skilled in the art to the above embodiments using equivalent substitutions or transformations without departing from the scope of the technical solution described in the present utility model should be covered within the protection scope of the present utility model.

[0047] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A DSP-based digital phase difference detection system, characterized in that, include: A pre-amplifier signal conditioning module is used to convert two input analog signals of the same frequency into two square wave signals with the same phase relationship; A core processing module is electrically connected to the output of the pre-stage signal conditioning module. The core processing module is equipped with a high-frequency timer as a time reference and is configured to use an input capture function to capture the signal edges of the two square wave signals respectively and record their corresponding timestamps. The core processing module is also configured to calculate the time difference between the two square wave signals based on their timestamps, measure the period of one of the square wave signals, and then obtain the phase difference between the two analog signals through digital calculation. An output module, electrically connected to the core processing module, is used to convert the digitized phase difference result calculated by the core processing module into an analog voltage signal for output.

2. The DSP-based digital phase difference detection system according to claim 1, characterized in that, The pre-amplifier signal conditioning module includes two high-speed comparators, and the two analog signals are respectively input to the signal input terminals of the two high-speed comparators.

3. The DSP-based digital phase difference detection system according to claim 2, characterized in that, Each of the high-speed comparators has a non-inverting input terminal and its inverting input terminal connected to a reference voltage for detecting the zero-crossing point of the signal.

4. The DSP-based digital phase difference detection system according to claim 1, characterized in that, The core processing module is a microcontroller that integrates a digital signal processing instruction set.

5. The DSP-based digital phase difference detection system according to claim 4, characterized in that, The microcontroller is configured with two or more timer input capture channels, which are used to capture the two square wave signals respectively.

6. The DSP-based digital phase difference detection system according to claim 5, characterized in that, The high-frequency timer is a free-counting timer that runs independently inside the microcontroller. The timestamp is the moment when the input capture event occurs, and the count value of the free-counting timer is latched to obtain the value.

7. The DSP-based digital phase difference detection system according to claim 1, characterized in that, The output module is a digital-to-analog converter.

8. The DSP-based digital phase difference detection system according to claim 7, characterized in that, The digital-to-analog converter is integrated inside the microcontroller of the core processing module.

9. The DSP-based digital phase difference detection system according to claim 1, characterized in that, It also includes a power supply module for providing operating voltage to the pre-amplifier signal conditioning module and the core processing module.

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